base.hh revision 5338
15369Ssaidi@eecs.umich.edu/* 23005Sstever@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 33005Sstever@eecs.umich.edu * All rights reserved. 43005Sstever@eecs.umich.edu * 53005Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63005Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 73005Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83005Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93005Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103005Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113005Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123005Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133005Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143005Sstever@eecs.umich.edu * this software without specific prior written permission. 153005Sstever@eecs.umich.edu * 163005Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173005Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183005Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193005Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203005Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213005Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223005Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233005Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243005Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253005Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263005Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273005Sstever@eecs.umich.edu * 283005Sstever@eecs.umich.edu * Authors: Erik Hallnor 292710SN/A * Steve Reinhardt 302710SN/A * Ron Dreslinski 313005Sstever@eecs.umich.edu */ 322889SN/A 336654Snate@binkert.org/** 346654Snate@binkert.org * @file 356654Snate@binkert.org * Declares a basic cache interface BaseCache. 366654Snate@binkert.org */ 376654Snate@binkert.org 382667SN/A#ifndef __BASE_CACHE_HH__ 396654Snate@binkert.org#define __BASE_CACHE_HH__ 406654Snate@binkert.org 416654Snate@binkert.org#include <vector> 425457Ssaidi@eecs.umich.edu#include <string> 436654Snate@binkert.org#include <list> 446654Snate@binkert.org#include <algorithm> 455457Ssaidi@eecs.umich.edu#include <inttypes.h> 466654Snate@binkert.org 478169SLisa.Hsu@amd.com#include "base/misc.hh" 488169SLisa.Hsu@amd.com#include "base/statistics.hh" 498169SLisa.Hsu@amd.com#include "base/trace.hh" 506654Snate@binkert.org#include "mem/cache/mshr_queue.hh" 513395Shsul@eecs.umich.edu#include "mem/mem_object.hh" 526981SLisa.Hsu@amd.com#include "mem/packet.hh" 533448Shsul@eecs.umich.edu#include "mem/tport.hh" 545369Ssaidi@eecs.umich.edu#include "mem/request.hh" 553394Shsul@eecs.umich.edu#include "params/BaseCache.hh" 563444Sktlim@umich.edu#include "sim/eventq.hh" 573444Sktlim@umich.edu#include "sim/sim_exit.hh" 583444Sktlim@umich.edu 593444Sktlim@umich.educlass MSHR; 602424SN/A/** 612957SN/A * A basic cache interface. Implements some common functions for speed. 622957SN/A */ 633323Shsul@eecs.umich.educlass BaseCache : public MemObject 643005Sstever@eecs.umich.edu{ 657787SAli.Saidi@ARM.com /** 667787SAli.Saidi@ARM.com * Indexes to enumerate the MSHR queues. 675514SMichael.Adler@intel.com */ 682957SN/A enum MSHRQueueIndex { 695514SMichael.Adler@intel.com MSHRQueue_MSHRs, 705514SMichael.Adler@intel.com MSHRQueue_WriteBuffer 715514SMichael.Adler@intel.com }; 725514SMichael.Adler@intel.com 738467Snilay@cs.wisc.edu /** 748467Snilay@cs.wisc.edu * Reasons for caches to be blocked. 758467Snilay@cs.wisc.edu */ 763323Shsul@eecs.umich.edu enum BlockedCause { 773444Sktlim@umich.edu Blocked_NoMSHRs = MSHRQueue_MSHRs, 782957SN/A Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 798467Snilay@cs.wisc.edu Blocked_NoTargets, 808467Snilay@cs.wisc.edu NUM_BLOCKED_CAUSES 818467Snilay@cs.wisc.edu }; 822957SN/A 832957SN/A public: 842957SN/A /** 852957SN/A * Reasons for cache to request a bus. 862957SN/A */ 872957SN/A enum RequestCause { 888167SLisa.Hsu@amd.com Request_MSHR = MSHRQueue_MSHRs, 898167SLisa.Hsu@amd.com Request_WB = MSHRQueue_WriteBuffer, 908167SLisa.Hsu@amd.com Request_PF, 915369Ssaidi@eecs.umich.edu NUM_REQUEST_CAUSES 928167SLisa.Hsu@amd.com }; 938167SLisa.Hsu@amd.com 948167SLisa.Hsu@amd.com private: 958167SLisa.Hsu@amd.com 968167SLisa.Hsu@amd.com class CachePort : public SimpleTimingPort 978167SLisa.Hsu@amd.com { 988167SLisa.Hsu@amd.com public: 998168SLisa.Hsu@amd.com BaseCache *cache; 1008168SLisa.Hsu@amd.com 1018168SLisa.Hsu@amd.com protected: 1028168SLisa.Hsu@amd.com CachePort(const std::string &_name, BaseCache *_cache, 1038167SLisa.Hsu@amd.com const std::string &_label, 1048167SLisa.Hsu@amd.com std::vector<Range<Addr> > filter_ranges); 1058168SLisa.Hsu@amd.com 1065369Ssaidi@eecs.umich.edu virtual void recvStatusChange(Status status); 1075369Ssaidi@eecs.umich.edu 1085369Ssaidi@eecs.umich.edu virtual int deviceBlockSize(); 1095369Ssaidi@eecs.umich.edu 1105369Ssaidi@eecs.umich.edu bool recvRetryCommon(); 1118167SLisa.Hsu@amd.com 1125369Ssaidi@eecs.umich.edu typedef EventWrapper<Port, &Port::sendRetry> 1135369Ssaidi@eecs.umich.edu SendRetryEvent; 1142801SN/A 1152801SN/A const std::string label; 1165514SMichael.Adler@intel.com 1175514SMichael.Adler@intel.com public: 1185514SMichael.Adler@intel.com void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; } 1195514SMichael.Adler@intel.com 1202418SN/A void setBlocked(); 1216391Sksewell@umich.edu 1226391Sksewell@umich.edu void clearBlocked(); 1236391Sksewell@umich.edu 1246642Sksewell@umich.edu bool checkFunctional(PacketPtr pkt); 1256391Sksewell@umich.edu 1266642Sksewell@umich.edu CachePort *otherPort; 1272833SN/A 1282833SN/A bool blocked; 1292833SN/A 1302833SN/A bool mustSendRetry; 1312833SN/A 1322833SN/A /** filter ranges */ 1335514SMichael.Adler@intel.com std::vector<Range<Addr> > filterRanges; 1345514SMichael.Adler@intel.com 1352833SN/A void requestBus(RequestCause cause, Tick time) 1362833SN/A { 1372833SN/A DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 1385514SMichael.Adler@intel.com if (!waitingOnRetry) { 1395514SMichael.Adler@intel.com schedSendEvent(time); 1405514SMichael.Adler@intel.com } 1415514SMichael.Adler@intel.com } 1422833SN/A 1432833SN/A void respond(PacketPtr pkt, Tick time) { 1442833SN/A schedSendTiming(pkt, time); 1453005Sstever@eecs.umich.edu } 1462833SN/A }; 1472833SN/A 1482833SN/A public: //Made public so coherence can get at it. 1495514SMichael.Adler@intel.com CachePort *cpuSidePort; 1505514SMichael.Adler@intel.com CachePort *memSidePort; 1515514SMichael.Adler@intel.com 1525514SMichael.Adler@intel.com protected: 1532833SN/A 1542833SN/A /** Miss status registers */ 1556642Sksewell@umich.edu MSHRQueue mshrQueue; 1566642Sksewell@umich.edu 1578169SLisa.Hsu@amd.com /** Write/writeback buffer */ 1588169SLisa.Hsu@amd.com MSHRQueue writeBuffer; 1598169SLisa.Hsu@amd.com 1608169SLisa.Hsu@amd.com MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 1618169SLisa.Hsu@amd.com PacketPtr pkt, Tick time, bool requestBus) 1628169SLisa.Hsu@amd.com { 1638169SLisa.Hsu@amd.com MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 1648169SLisa.Hsu@amd.com 1658169SLisa.Hsu@amd.com if (mq->isFull()) { 1668169SLisa.Hsu@amd.com setBlocked((BlockedCause)mq->index); 1678169SLisa.Hsu@amd.com } 1688169SLisa.Hsu@amd.com 1692957SN/A if (requestBus) { 1703395Shsul@eecs.umich.edu requestMemSideBus((RequestCause)mq->index, time); 1716642Sksewell@umich.edu } 1723005Sstever@eecs.umich.edu 1733395Shsul@eecs.umich.edu return mshr; 1743395Shsul@eecs.umich.edu } 1753395Shsul@eecs.umich.edu 1763323Shsul@eecs.umich.edu void markInServiceInternal(MSHR *mshr) 1773395Shsul@eecs.umich.edu { 1783395Shsul@eecs.umich.edu MSHRQueue *mq = mshr->queue; 1798169SLisa.Hsu@amd.com bool wasFull = mq->isFull(); 1808169SLisa.Hsu@amd.com mq->markInService(mshr); 1818436SBrad.Beckmann@amd.com if (wasFull && !mq->isFull()) { 1828322Ssteve.reinhardt@amd.com clearBlocked((BlockedCause)mq->index); 1838169SLisa.Hsu@amd.com } 1848169SLisa.Hsu@amd.com } 1858169SLisa.Hsu@amd.com 1865056Ssaidi@eecs.umich.edu /** Block size of this cache */ 1873395Shsul@eecs.umich.edu const int blkSize; 1888167SLisa.Hsu@amd.com 1893005Sstever@eecs.umich.edu /** 1908169SLisa.Hsu@amd.com * The latency of a hit in this device. 1918322Ssteve.reinhardt@amd.com */ 1928322Ssteve.reinhardt@amd.com int hitLatency; 1938169SLisa.Hsu@amd.com 1944968Sacolyte@umich.edu /** The number of targets for each MSHR. */ 1954968Sacolyte@umich.edu const int numTarget; 1964968Sacolyte@umich.edu 1973005Sstever@eecs.umich.edu /** Increasing order number assigned to each incoming request. */ 1982902SN/A uint64_t order; 1993481Shsul@eecs.umich.edu 200 /** 201 * Bit vector of the blocking reasons for the access path. 202 * @sa #BlockedCause 203 */ 204 uint8_t blocked; 205 206 /** Stores time the cache blocked for statistics. */ 207 Tick blockedCycle; 208 209 /** Pointer to the MSHR that has no targets. */ 210 MSHR *noTargetMSHR; 211 212 /** The number of misses to trigger an exit event. */ 213 Counter missCount; 214 215 /** The drain event. */ 216 Event *drainEvent; 217 218 public: 219 // Statistics 220 /** 221 * @addtogroup CacheStatistics 222 * @{ 223 */ 224 225 /** Number of hits per thread for each type of command. @sa Packet::Command */ 226 Stats::Vector<> hits[MemCmd::NUM_MEM_CMDS]; 227 /** Number of hits for demand accesses. */ 228 Stats::Formula demandHits; 229 /** Number of hit for all accesses. */ 230 Stats::Formula overallHits; 231 232 /** Number of misses per thread for each type of command. @sa Packet::Command */ 233 Stats::Vector<> misses[MemCmd::NUM_MEM_CMDS]; 234 /** Number of misses for demand accesses. */ 235 Stats::Formula demandMisses; 236 /** Number of misses for all accesses. */ 237 Stats::Formula overallMisses; 238 239 /** 240 * Total number of cycles per thread/command spent waiting for a miss. 241 * Used to calculate the average miss latency. 242 */ 243 Stats::Vector<> missLatency[MemCmd::NUM_MEM_CMDS]; 244 /** Total number of cycles spent waiting for demand misses. */ 245 Stats::Formula demandMissLatency; 246 /** Total number of cycles spent waiting for all misses. */ 247 Stats::Formula overallMissLatency; 248 249 /** The number of accesses per command and thread. */ 250 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 251 /** The number of demand accesses. */ 252 Stats::Formula demandAccesses; 253 /** The number of overall accesses. */ 254 Stats::Formula overallAccesses; 255 256 /** The miss rate per command and thread. */ 257 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 258 /** The miss rate of all demand accesses. */ 259 Stats::Formula demandMissRate; 260 /** The miss rate for all accesses. */ 261 Stats::Formula overallMissRate; 262 263 /** The average miss latency per command and thread. */ 264 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 265 /** The average miss latency for demand misses. */ 266 Stats::Formula demandAvgMissLatency; 267 /** The average miss latency for all misses. */ 268 Stats::Formula overallAvgMissLatency; 269 270 /** The total number of cycles blocked for each blocked cause. */ 271 Stats::Vector<> blocked_cycles; 272 /** The number of times this cache blocked for each blocked cause. */ 273 Stats::Vector<> blocked_causes; 274 275 /** The average number of cycles blocked for each blocked cause. */ 276 Stats::Formula avg_blocked; 277 278 /** The number of fast writes (WH64) performed. */ 279 Stats::Scalar<> fastWrites; 280 281 /** The number of cache copies performed. */ 282 Stats::Scalar<> cacheCopies; 283 284 /** Number of blocks written back per thread. */ 285 Stats::Vector<> writebacks; 286 287 /** Number of misses that hit in the MSHRs per command and thread. */ 288 Stats::Vector<> mshr_hits[MemCmd::NUM_MEM_CMDS]; 289 /** Demand misses that hit in the MSHRs. */ 290 Stats::Formula demandMshrHits; 291 /** Total number of misses that hit in the MSHRs. */ 292 Stats::Formula overallMshrHits; 293 294 /** Number of misses that miss in the MSHRs, per command and thread. */ 295 Stats::Vector<> mshr_misses[MemCmd::NUM_MEM_CMDS]; 296 /** Demand misses that miss in the MSHRs. */ 297 Stats::Formula demandMshrMisses; 298 /** Total number of misses that miss in the MSHRs. */ 299 Stats::Formula overallMshrMisses; 300 301 /** Number of misses that miss in the MSHRs, per command and thread. */ 302 Stats::Vector<> mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 303 /** Total number of misses that miss in the MSHRs. */ 304 Stats::Formula overallMshrUncacheable; 305 306 /** Total cycle latency of each MSHR miss, per command and thread. */ 307 Stats::Vector<> mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 308 /** Total cycle latency of demand MSHR misses. */ 309 Stats::Formula demandMshrMissLatency; 310 /** Total cycle latency of overall MSHR misses. */ 311 Stats::Formula overallMshrMissLatency; 312 313 /** Total cycle latency of each MSHR miss, per command and thread. */ 314 Stats::Vector<> mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 315 /** Total cycle latency of overall MSHR misses. */ 316 Stats::Formula overallMshrUncacheableLatency; 317 318 /** The total number of MSHR accesses per command and thread. */ 319 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 320 /** The total number of demand MSHR accesses. */ 321 Stats::Formula demandMshrAccesses; 322 /** The total number of MSHR accesses. */ 323 Stats::Formula overallMshrAccesses; 324 325 /** The miss rate in the MSHRs pre command and thread. */ 326 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 327 /** The demand miss rate in the MSHRs. */ 328 Stats::Formula demandMshrMissRate; 329 /** The overall miss rate in the MSHRs. */ 330 Stats::Formula overallMshrMissRate; 331 332 /** The average latency of an MSHR miss, per command and thread. */ 333 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 334 /** The average latency of a demand MSHR miss. */ 335 Stats::Formula demandAvgMshrMissLatency; 336 /** The average overall latency of an MSHR miss. */ 337 Stats::Formula overallAvgMshrMissLatency; 338 339 /** The average latency of an MSHR miss, per command and thread. */ 340 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 341 /** The average overall latency of an MSHR miss. */ 342 Stats::Formula overallAvgMshrUncacheableLatency; 343 344 /** The number of times a thread hit its MSHR cap. */ 345 Stats::Vector<> mshr_cap_events; 346 /** The number of times software prefetches caused the MSHR to block. */ 347 Stats::Vector<> soft_prefetch_mshr_full; 348 349 Stats::Scalar<> mshr_no_allocate_misses; 350 351 /** 352 * @} 353 */ 354 355 /** 356 * Register stats for this object. 357 */ 358 virtual void regStats(); 359 360 public: 361 typedef BaseCacheParams Params; 362 BaseCache(const Params *p); 363 ~BaseCache() {} 364 365 virtual void init(); 366 367 /** 368 * Query block size of a cache. 369 * @return The block size 370 */ 371 int getBlockSize() const 372 { 373 return blkSize; 374 } 375 376 377 Addr blockAlign(Addr addr) const { return (addr & ~(blkSize - 1)); } 378 379 380 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 381 { 382 assert(!pkt->req->isUncacheable()); 383 return allocateBufferInternal(&mshrQueue, 384 blockAlign(pkt->getAddr()), blkSize, 385 pkt, time, requestBus); 386 } 387 388 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 389 { 390 assert(pkt->isWrite() && !pkt->isRead()); 391 return allocateBufferInternal(&writeBuffer, 392 pkt->getAddr(), pkt->getSize(), 393 pkt, time, requestBus); 394 } 395 396 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus) 397 { 398 assert(pkt->req->isUncacheable()); 399 assert(pkt->isRead()); 400 return allocateBufferInternal(&mshrQueue, 401 pkt->getAddr(), pkt->getSize(), 402 pkt, time, requestBus); 403 } 404 405 /** 406 * Returns true if the cache is blocked for accesses. 407 */ 408 bool isBlocked() 409 { 410 return blocked != 0; 411 } 412 413 /** 414 * Marks the access path of the cache as blocked for the given cause. This 415 * also sets the blocked flag in the slave interface. 416 * @param cause The reason for the cache blocking. 417 */ 418 void setBlocked(BlockedCause cause) 419 { 420 uint8_t flag = 1 << cause; 421 if (blocked == 0) { 422 blocked_causes[cause]++; 423 blockedCycle = curTick; 424 cpuSidePort->setBlocked(); 425 } 426 blocked |= flag; 427 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 428 } 429 430 /** 431 * Marks the cache as unblocked for the given cause. This also clears the 432 * blocked flags in the appropriate interfaces. 433 * @param cause The newly unblocked cause. 434 * @warning Calling this function can cause a blocked request on the bus to 435 * access the cache. The cache must be in a state to handle that request. 436 */ 437 void clearBlocked(BlockedCause cause) 438 { 439 uint8_t flag = 1 << cause; 440 blocked &= ~flag; 441 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 442 if (blocked == 0) { 443 blocked_cycles[cause] += curTick - blockedCycle; 444 cpuSidePort->clearBlocked(); 445 } 446 } 447 448 Tick nextMSHRReadyTime() 449 { 450 return std::min(mshrQueue.nextMSHRReadyTime(), 451 writeBuffer.nextMSHRReadyTime()); 452 } 453 454 /** 455 * Request the master bus for the given cause and time. 456 * @param cause The reason for the request. 457 * @param time The time to make the request. 458 */ 459 void requestMemSideBus(RequestCause cause, Tick time) 460 { 461 memSidePort->requestBus(cause, time); 462 } 463 464 /** 465 * Clear the master bus request for the given cause. 466 * @param cause The request reason to clear. 467 */ 468 void deassertMemSideBusRequest(RequestCause cause) 469 { 470 // obsolete!! 471 assert(false); 472 // memSidePort->deassertBusRequest(cause); 473 // checkDrain(); 474 } 475 476 virtual unsigned int drain(Event *de); 477 478 virtual bool inCache(Addr addr) = 0; 479 480 virtual bool inMissQueue(Addr addr) = 0; 481 482 void incMissCount(PacketPtr pkt) 483 { 484 misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; 485 486 if (missCount) { 487 --missCount; 488 if (missCount == 0) 489 exitSimLoop("A cache reached the maximum miss count"); 490 } 491 } 492 493}; 494 495#endif //__BASE_CACHE_HH__ 496