base.hh revision 13478
19241Sandreas.hansson@arm.com/* 29717Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited 39241Sandreas.hansson@arm.com * All rights reserved. 49241Sandreas.hansson@arm.com * 59241Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 69241Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 79241Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 89241Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 99241Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 109241Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 119241Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 129241Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 139241Sandreas.hansson@arm.com * 149241Sandreas.hansson@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 159241Sandreas.hansson@arm.com * All rights reserved. 169241Sandreas.hansson@arm.com * 179241Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 189241Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 199241Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 209241Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 219241Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 229241Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 239241Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 249241Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 259241Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 269241Sandreas.hansson@arm.com * this software without specific prior written permission. 279241Sandreas.hansson@arm.com * 289241Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299241Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309241Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319241Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329241Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339241Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349241Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359241Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369241Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379241Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389241Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399241Sandreas.hansson@arm.com * 409241Sandreas.hansson@arm.com * Authors: Erik Hallnor 419241Sandreas.hansson@arm.com * Steve Reinhardt 429241Sandreas.hansson@arm.com * Ron Dreslinski 439241Sandreas.hansson@arm.com * Andreas Hansson 449241Sandreas.hansson@arm.com * Nikos Nikoleris 459241Sandreas.hansson@arm.com */ 469241Sandreas.hansson@arm.com 479241Sandreas.hansson@arm.com/** 489241Sandreas.hansson@arm.com * @file 499241Sandreas.hansson@arm.com * Declares a basic cache interface BaseCache. 509241Sandreas.hansson@arm.com */ 519241Sandreas.hansson@arm.com 529241Sandreas.hansson@arm.com#ifndef __MEM_CACHE_BASE_HH__ 539241Sandreas.hansson@arm.com#define __MEM_CACHE_BASE_HH__ 549241Sandreas.hansson@arm.com 559241Sandreas.hansson@arm.com#include <cassert> 569241Sandreas.hansson@arm.com#include <cstdint> 579718Sandreas.hansson@arm.com#include <string> 589720Sandreas.hansson@arm.com 599717Sandreas.hansson@arm.com#include "base/addr_range.hh" 609719Sandreas.hansson@arm.com#include "base/statistics.hh" 619241Sandreas.hansson@arm.com#include "base/trace.hh" 629719Sandreas.hansson@arm.com#include "base/types.hh" 639719Sandreas.hansson@arm.com#include "debug/Cache.hh" 649719Sandreas.hansson@arm.com#include "debug/CachePort.hh" 659719Sandreas.hansson@arm.com#include "enums/Clusivity.hh" 669241Sandreas.hansson@arm.com#include "mem/cache/cache_blk.hh" 679241Sandreas.hansson@arm.com#include "mem/cache/mshr_queue.hh" 689241Sandreas.hansson@arm.com#include "mem/cache/tags/base.hh" 699241Sandreas.hansson@arm.com#include "mem/cache/write_queue.hh" 709241Sandreas.hansson@arm.com#include "mem/cache/write_queue_entry.hh" 719241Sandreas.hansson@arm.com#include "mem/mem_object.hh" 729241Sandreas.hansson@arm.com#include "mem/packet.hh" 739241Sandreas.hansson@arm.com#include "mem/packet_queue.hh" 749241Sandreas.hansson@arm.com#include "mem/qport.hh" 759294Sandreas.hansson@arm.com#include "mem/request.hh" 769294Sandreas.hansson@arm.com#include "params/WriteAllocator.hh" 779241Sandreas.hansson@arm.com#include "sim/eventq.hh" 789241Sandreas.hansson@arm.com#include "sim/probe/probe.hh" 799241Sandreas.hansson@arm.com#include "sim/serialize.hh" 809241Sandreas.hansson@arm.com#include "sim/sim_exit.hh" 819241Sandreas.hansson@arm.com#include "sim/system.hh" 829241Sandreas.hansson@arm.com 839241Sandreas.hansson@arm.comclass BaseMasterPort; 849241Sandreas.hansson@arm.comclass BasePrefetcher; 859241Sandreas.hansson@arm.comclass BaseSlavePort; 869241Sandreas.hansson@arm.comclass MSHR; 879241Sandreas.hansson@arm.comclass MasterPort; 889241Sandreas.hansson@arm.comclass QueueEntry; 899241Sandreas.hansson@arm.comstruct BaseCacheParams; 909241Sandreas.hansson@arm.com 919241Sandreas.hansson@arm.com/** 929524SAndreas.Sandberg@ARM.com * A basic cache interface. Implements some common functions for speed. 939241Sandreas.hansson@arm.com */ 949241Sandreas.hansson@arm.comclass BaseCache : public MemObject 959718Sandreas.hansson@arm.com{ 969718Sandreas.hansson@arm.com protected: 979241Sandreas.hansson@arm.com /** 989717Sandreas.hansson@arm.com * Indexes to enumerate the MSHR queues. 999241Sandreas.hansson@arm.com */ 1009241Sandreas.hansson@arm.com enum MSHRQueueIndex { 1019241Sandreas.hansson@arm.com MSHRQueue_MSHRs, 1029241Sandreas.hansson@arm.com MSHRQueue_WriteBuffer 1039241Sandreas.hansson@arm.com }; 1049241Sandreas.hansson@arm.com 1059241Sandreas.hansson@arm.com public: 1069241Sandreas.hansson@arm.com /** 1079241Sandreas.hansson@arm.com * Reasons for caches to be blocked. 1089241Sandreas.hansson@arm.com */ 1099524SAndreas.Sandberg@ARM.com enum BlockedCause { 1109719Sandreas.hansson@arm.com Blocked_NoMSHRs = MSHRQueue_MSHRs, 1119720Sandreas.hansson@arm.com Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 1129719Sandreas.hansson@arm.com Blocked_NoTargets, 1139241Sandreas.hansson@arm.com NUM_BLOCKED_CAUSES 1149241Sandreas.hansson@arm.com }; 1159241Sandreas.hansson@arm.com 1169241Sandreas.hansson@arm.com protected: 1179241Sandreas.hansson@arm.com 1189241Sandreas.hansson@arm.com /** 1199241Sandreas.hansson@arm.com * A cache master port is used for the memory-side port of the 1209342SAndreas.Sandberg@arm.com * cache, and in addition to the basic timing port that only sends 1219241Sandreas.hansson@arm.com * response packets through a transmit list, it also offers the 1229719Sandreas.hansson@arm.com * ability to schedule and send request packets (requests & 1239719Sandreas.hansson@arm.com * writebacks). The send event is scheduled through schedSendEvent, 1249719Sandreas.hansson@arm.com * and the sendDeferredPacket of the timing port is modified to 1259719Sandreas.hansson@arm.com * consider both the transmit list and the requests from the MSHR. 1269719Sandreas.hansson@arm.com */ 1279719Sandreas.hansson@arm.com class CacheMasterPort : public QueuedMasterPort 1289719Sandreas.hansson@arm.com { 1299719Sandreas.hansson@arm.com 1309719Sandreas.hansson@arm.com public: 1319719Sandreas.hansson@arm.com 1329241Sandreas.hansson@arm.com /** 1339241Sandreas.hansson@arm.com * Schedule a send of a request packet (from the MSHR). Note 1349241Sandreas.hansson@arm.com * that we could already have a retry outstanding. 1359241Sandreas.hansson@arm.com */ 1369241Sandreas.hansson@arm.com void schedSendEvent(Tick time) 1379241Sandreas.hansson@arm.com { 1389241Sandreas.hansson@arm.com DPRINTF(CachePort, "Scheduling send event at %llu\n", time); 1399241Sandreas.hansson@arm.com reqQueue.schedSendEvent(time); 1409719Sandreas.hansson@arm.com } 1419241Sandreas.hansson@arm.com 1429719Sandreas.hansson@arm.com protected: 1439241Sandreas.hansson@arm.com 1449717Sandreas.hansson@arm.com CacheMasterPort(const std::string &_name, BaseCache *_cache, 1459241Sandreas.hansson@arm.com ReqPacketQueue &_reqQueue, 1469241Sandreas.hansson@arm.com SnoopRespPacketQueue &_snoopRespQueue) : 1479241Sandreas.hansson@arm.com QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue) 1489719Sandreas.hansson@arm.com { } 1499719Sandreas.hansson@arm.com 1509719Sandreas.hansson@arm.com /** 1519241Sandreas.hansson@arm.com * Memory-side port always snoops. 1529241Sandreas.hansson@arm.com * 1539241Sandreas.hansson@arm.com * @return always true 1549241Sandreas.hansson@arm.com */ 1559241Sandreas.hansson@arm.com virtual bool isSnooping() const { return true; } 1569241Sandreas.hansson@arm.com }; 1579717Sandreas.hansson@arm.com 1589717Sandreas.hansson@arm.com /** 1599717Sandreas.hansson@arm.com * Override the default behaviour of sendDeferredPacket to enable 1609717Sandreas.hansson@arm.com * the memory-side cache port to also send requests based on the 1619241Sandreas.hansson@arm.com * current MSHR status. This queue has a pointer to our specific 1629241Sandreas.hansson@arm.com * cache implementation and is used by the MemSidePort. 1639241Sandreas.hansson@arm.com */ 1649719Sandreas.hansson@arm.com class CacheReqPacketQueue : public ReqPacketQueue 1659719Sandreas.hansson@arm.com { 1669719Sandreas.hansson@arm.com 1679719Sandreas.hansson@arm.com protected: 1689719Sandreas.hansson@arm.com 1699720Sandreas.hansson@arm.com BaseCache &cache; 1709719Sandreas.hansson@arm.com SnoopRespPacketQueue &snoopRespQueue; 1719241Sandreas.hansson@arm.com 1729241Sandreas.hansson@arm.com public: 1739241Sandreas.hansson@arm.com 1749717Sandreas.hansson@arm.com CacheReqPacketQueue(BaseCache &cache, MasterPort &port, 1759241Sandreas.hansson@arm.com SnoopRespPacketQueue &snoop_resp_queue, 1769717Sandreas.hansson@arm.com const std::string &label) : 1779717Sandreas.hansson@arm.com ReqPacketQueue(cache, port, label), cache(cache), 1789717Sandreas.hansson@arm.com snoopRespQueue(snoop_resp_queue) { } 1799717Sandreas.hansson@arm.com 1809717Sandreas.hansson@arm.com /** 1819719Sandreas.hansson@arm.com * Override the normal sendDeferredPacket and do not only 1829719Sandreas.hansson@arm.com * consider the transmit list (used for responses), but also 1839718Sandreas.hansson@arm.com * requests. 1849719Sandreas.hansson@arm.com */ 1859719Sandreas.hansson@arm.com virtual void sendDeferredPacket(); 1869719Sandreas.hansson@arm.com 1879719Sandreas.hansson@arm.com /** 1889719Sandreas.hansson@arm.com * Check if there is a conflicting snoop response about to be 1899719Sandreas.hansson@arm.com * send out, and if so simply stall any requests, and schedule 1909719Sandreas.hansson@arm.com * a send event at the same time as the next snoop response is 1919719Sandreas.hansson@arm.com * being sent out. 1929719Sandreas.hansson@arm.com */ 1939719Sandreas.hansson@arm.com bool checkConflictingSnoop(Addr addr) 1949719Sandreas.hansson@arm.com { 1959719Sandreas.hansson@arm.com if (snoopRespQueue.hasAddr(addr)) { 1969719Sandreas.hansson@arm.com DPRINTF(CachePort, "Waiting for snoop response to be " 1979720Sandreas.hansson@arm.com "sent\n"); 1989719Sandreas.hansson@arm.com Tick when = snoopRespQueue.deferredPacketReadyTime(); 1999719Sandreas.hansson@arm.com schedSendEvent(when); 2009719Sandreas.hansson@arm.com return true; 2019717Sandreas.hansson@arm.com } 2029241Sandreas.hansson@arm.com return false; 2039241Sandreas.hansson@arm.com } 2049241Sandreas.hansson@arm.com }; 2059718Sandreas.hansson@arm.com 2069241Sandreas.hansson@arm.com 2079241Sandreas.hansson@arm.com /** 2089241Sandreas.hansson@arm.com * The memory-side port extends the base cache master port with 2099241Sandreas.hansson@arm.com * access functions for functional, atomic and timing snoops. 2109241Sandreas.hansson@arm.com */ 2119241Sandreas.hansson@arm.com class MemSidePort : public CacheMasterPort 2129241Sandreas.hansson@arm.com { 2139718Sandreas.hansson@arm.com private: 2149241Sandreas.hansson@arm.com 2159241Sandreas.hansson@arm.com /** The cache-specific queue. */ 2169718Sandreas.hansson@arm.com CacheReqPacketQueue _reqQueue; 2179241Sandreas.hansson@arm.com 2189241Sandreas.hansson@arm.com SnoopRespPacketQueue _snoopRespQueue; 2199241Sandreas.hansson@arm.com 2209241Sandreas.hansson@arm.com // a pointer to our specific cache implementation 2219241Sandreas.hansson@arm.com BaseCache *cache; 2229241Sandreas.hansson@arm.com 2239241Sandreas.hansson@arm.com protected: 2249241Sandreas.hansson@arm.com 2259241Sandreas.hansson@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt); 2269241Sandreas.hansson@arm.com 2279241Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 2289241Sandreas.hansson@arm.com 2299241Sandreas.hansson@arm.com virtual Tick recvAtomicSnoop(PacketPtr pkt); 2309241Sandreas.hansson@arm.com 2319241Sandreas.hansson@arm.com virtual void recvFunctionalSnoop(PacketPtr pkt); 2329241Sandreas.hansson@arm.com 2339241Sandreas.hansson@arm.com public: 2349241Sandreas.hansson@arm.com 2359241Sandreas.hansson@arm.com MemSidePort(const std::string &_name, BaseCache *_cache, 2369241Sandreas.hansson@arm.com const std::string &_label); 2379241Sandreas.hansson@arm.com }; 2389241Sandreas.hansson@arm.com 2399241Sandreas.hansson@arm.com /** 2409241Sandreas.hansson@arm.com * A cache slave port is used for the CPU-side port of the cache, 2419241Sandreas.hansson@arm.com * and it is basically a simple timing port that uses a transmit 2429241Sandreas.hansson@arm.com * list for responses to the CPU (or connected master). In 2439241Sandreas.hansson@arm.com * addition, it has the functionality to block the port for 2449241Sandreas.hansson@arm.com * incoming requests. If blocked, the port will issue a retry once 2459241Sandreas.hansson@arm.com * unblocked. 2469241Sandreas.hansson@arm.com */ 2479718Sandreas.hansson@arm.com class CacheSlavePort : public QueuedSlavePort 2489241Sandreas.hansson@arm.com { 2499241Sandreas.hansson@arm.com 2509241Sandreas.hansson@arm.com public: 2519718Sandreas.hansson@arm.com 2529241Sandreas.hansson@arm.com /** Do not accept any new requests. */ 2539241Sandreas.hansson@arm.com void setBlocked(); 2549241Sandreas.hansson@arm.com 2559241Sandreas.hansson@arm.com /** Return to normal operation and accept new requests. */ 2569241Sandreas.hansson@arm.com void clearBlocked(); 2579241Sandreas.hansson@arm.com 2589241Sandreas.hansson@arm.com bool isBlocked() const { return blocked; } 2599241Sandreas.hansson@arm.com 2609241Sandreas.hansson@arm.com protected: 2619241Sandreas.hansson@arm.com 2629241Sandreas.hansson@arm.com CacheSlavePort(const std::string &_name, BaseCache *_cache, 2639241Sandreas.hansson@arm.com const std::string &_label); 2649241Sandreas.hansson@arm.com 2659241Sandreas.hansson@arm.com /** A normal packet queue used to store responses. */ 2669241Sandreas.hansson@arm.com RespPacketQueue queue; 2679241Sandreas.hansson@arm.com 2689241Sandreas.hansson@arm.com bool blocked; 2699241Sandreas.hansson@arm.com 2709718Sandreas.hansson@arm.com bool mustSendRetry; 2719718Sandreas.hansson@arm.com 2729718Sandreas.hansson@arm.com private: 2739718Sandreas.hansson@arm.com 2749718Sandreas.hansson@arm.com void processSendRetry(); 2759718Sandreas.hansson@arm.com 2769718Sandreas.hansson@arm.com EventFunctionWrapper sendRetryEvent; 2779241Sandreas.hansson@arm.com 2789718Sandreas.hansson@arm.com }; 2799241Sandreas.hansson@arm.com 2809722Ssascha.bischoff@arm.com /** 2819722Ssascha.bischoff@arm.com * The CPU-side port extends the base cache slave port with access 2829722Ssascha.bischoff@arm.com * functions for functional, atomic and timing requests. 2839241Sandreas.hansson@arm.com */ 2849718Sandreas.hansson@arm.com class CpuSidePort : public CacheSlavePort 2859241Sandreas.hansson@arm.com { 2869241Sandreas.hansson@arm.com private: 2879241Sandreas.hansson@arm.com 2889241Sandreas.hansson@arm.com // a pointer to our specific cache implementation 2899241Sandreas.hansson@arm.com BaseCache *cache; 2909241Sandreas.hansson@arm.com 2919718Sandreas.hansson@arm.com protected: 2929241Sandreas.hansson@arm.com virtual bool recvTimingSnoopResp(PacketPtr pkt) override; 2939241Sandreas.hansson@arm.com 2949241Sandreas.hansson@arm.com virtual bool tryTiming(PacketPtr pkt) override; 2959241Sandreas.hansson@arm.com 2969241Sandreas.hansson@arm.com virtual bool recvTimingReq(PacketPtr pkt) override; 2979241Sandreas.hansson@arm.com 2989241Sandreas.hansson@arm.com virtual Tick recvAtomic(PacketPtr pkt) override; 2999241Sandreas.hansson@arm.com 3009241Sandreas.hansson@arm.com virtual void recvFunctional(PacketPtr pkt) override; 3019241Sandreas.hansson@arm.com 3029241Sandreas.hansson@arm.com virtual AddrRangeList getAddrRanges() const override; 3039241Sandreas.hansson@arm.com 3049241Sandreas.hansson@arm.com public: 3059241Sandreas.hansson@arm.com 3069241Sandreas.hansson@arm.com CpuSidePort(const std::string &_name, BaseCache *_cache, 3079241Sandreas.hansson@arm.com const std::string &_label); 3089241Sandreas.hansson@arm.com 3099241Sandreas.hansson@arm.com }; 3109241Sandreas.hansson@arm.com 3119241Sandreas.hansson@arm.com CpuSidePort cpuSidePort; 3129241Sandreas.hansson@arm.com MemSidePort memSidePort; 3139241Sandreas.hansson@arm.com 3149241Sandreas.hansson@arm.com protected: 3159241Sandreas.hansson@arm.com 3169241Sandreas.hansson@arm.com /** Miss status registers */ 3179241Sandreas.hansson@arm.com MSHRQueue mshrQueue; 3189241Sandreas.hansson@arm.com 3199241Sandreas.hansson@arm.com /** Write/writeback buffer */ 3209241Sandreas.hansson@arm.com WriteQueue writeBuffer; 3219721Ssascha.bischoff@arm.com 3229721Ssascha.bischoff@arm.com /** Tag and data Storage */ 3239721Ssascha.bischoff@arm.com BaseTags *tags; 3249241Sandreas.hansson@arm.com 3259241Sandreas.hansson@arm.com /** Prefetcher */ 3269241Sandreas.hansson@arm.com BasePrefetcher *prefetcher; 3279241Sandreas.hansson@arm.com 3289241Sandreas.hansson@arm.com /** To probe when a cache hit occurs */ 3299241Sandreas.hansson@arm.com ProbePointArg<PacketPtr> *ppHit; 3309241Sandreas.hansson@arm.com 3319241Sandreas.hansson@arm.com /** To probe when a cache miss occurs */ 3329241Sandreas.hansson@arm.com ProbePointArg<PacketPtr> *ppMiss; 3339721Ssascha.bischoff@arm.com 3349241Sandreas.hansson@arm.com /** 3359721Ssascha.bischoff@arm.com * The writeAllocator drive optimizations for streaming writes. 3369241Sandreas.hansson@arm.com * It first determines whether a WriteReq MSHR should be delayed, 3379241Sandreas.hansson@arm.com * thus ensuring that we wait longer in cases when we are write 3389241Sandreas.hansson@arm.com * coalescing and allowing all the bytes of the line to be written 3399241Sandreas.hansson@arm.com * before the MSHR packet is sent downstream. This works in unison 3409241Sandreas.hansson@arm.com * with the tracking in the MSHR to check if the entire line is 3419241Sandreas.hansson@arm.com * written. The write mode also affects the behaviour on filling 3429241Sandreas.hansson@arm.com * any whole-line writes. Normally the cache allocates the line 3439241Sandreas.hansson@arm.com * when receiving the InvalidateResp, but after seeing enough 3449241Sandreas.hansson@arm.com * consecutive lines we switch to using the tempBlock, and thus 3459241Sandreas.hansson@arm.com * end up not allocating the line, and instead turning the 3469241Sandreas.hansson@arm.com * whole-line write into a writeback straight away. 3479241Sandreas.hansson@arm.com */ 3489241Sandreas.hansson@arm.com WriteAllocator * const writeAllocator; 3499241Sandreas.hansson@arm.com 3509717Sandreas.hansson@arm.com /** 3519241Sandreas.hansson@arm.com * Temporary cache block for occasional transitory use. We use 3529241Sandreas.hansson@arm.com * the tempBlock to fill when allocation fails (e.g., when there 3539241Sandreas.hansson@arm.com * is an outstanding request that accesses the victim block) or 3549241Sandreas.hansson@arm.com * when we want to avoid allocation (e.g., exclusive caches) 3559241Sandreas.hansson@arm.com */ 3569241Sandreas.hansson@arm.com TempCacheBlk *tempBlock; 3579241Sandreas.hansson@arm.com 3589584Sandreas@sandberg.pp.se /** 3599584Sandreas@sandberg.pp.se * Upstream caches need this packet until true is returned, so 3609584Sandreas@sandberg.pp.se * hold it for deletion until a subsequent call 3619241Sandreas.hansson@arm.com */ 3629241Sandreas.hansson@arm.com std::unique_ptr<Packet> pendingDelete; 3639584Sandreas@sandberg.pp.se 3649584Sandreas@sandberg.pp.se /** 3659584Sandreas@sandberg.pp.se * Mark a request as in service (sent downstream in the memory 3669241Sandreas.hansson@arm.com * system), effectively making this MSHR the ordering point. 3679241Sandreas.hansson@arm.com */ 3689241Sandreas.hansson@arm.com void markInService(MSHR *mshr, bool pending_modified_resp) 3699717Sandreas.hansson@arm.com { 3709241Sandreas.hansson@arm.com bool wasFull = mshrQueue.isFull(); 3719241Sandreas.hansson@arm.com mshrQueue.markInService(mshr, pending_modified_resp); 3729241Sandreas.hansson@arm.com 3739241Sandreas.hansson@arm.com if (wasFull && !mshrQueue.isFull()) { 3749719Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 3759719Sandreas.hansson@arm.com } 3769719Sandreas.hansson@arm.com } 3779719Sandreas.hansson@arm.com 3789241Sandreas.hansson@arm.com void markInService(WriteQueueEntry *entry) 3799241Sandreas.hansson@arm.com { 3809241Sandreas.hansson@arm.com bool wasFull = writeBuffer.isFull(); 3819719Sandreas.hansson@arm.com writeBuffer.markInService(entry); 3829719Sandreas.hansson@arm.com 3839719Sandreas.hansson@arm.com if (wasFull && !writeBuffer.isFull()) { 3849719Sandreas.hansson@arm.com clearBlocked(Blocked_NoWBBuffers); 3859719Sandreas.hansson@arm.com } 3869719Sandreas.hansson@arm.com } 3879719Sandreas.hansson@arm.com 3889719Sandreas.hansson@arm.com /** 3899719Sandreas.hansson@arm.com * Determine whether we should allocate on a fill or not. If this 3909719Sandreas.hansson@arm.com * cache is mostly inclusive with regards to the upstream cache(s) 3919719Sandreas.hansson@arm.com * we always allocate (for any non-forwarded and cacheable 3929719Sandreas.hansson@arm.com * requests). In the case of a mostly exclusive cache, we allocate 3939720Sandreas.hansson@arm.com * on fill if the packet did not come from a cache, thus if we: 3949720Sandreas.hansson@arm.com * are dealing with a whole-line write (the latter behaves much 3959719Sandreas.hansson@arm.com * like a writeback), the original target packet came from a 3969719Sandreas.hansson@arm.com * non-caching source, or if we are performing a prefetch or LLSC. 3979719Sandreas.hansson@arm.com * 3989719Sandreas.hansson@arm.com * @param cmd Command of the incoming requesting packet 3999719Sandreas.hansson@arm.com * @return Whether we should allocate on the fill 4009719Sandreas.hansson@arm.com */ 4019720Sandreas.hansson@arm.com inline bool allocOnFill(MemCmd cmd) const 4029720Sandreas.hansson@arm.com { 4039719Sandreas.hansson@arm.com return clusivity == Enums::mostly_incl || 4049719Sandreas.hansson@arm.com cmd == MemCmd::WriteLineReq || 4059719Sandreas.hansson@arm.com cmd == MemCmd::ReadReq || 4069719Sandreas.hansson@arm.com cmd == MemCmd::WriteReq || 4079719Sandreas.hansson@arm.com cmd.isPrefetch() || 4089719Sandreas.hansson@arm.com cmd.isLLSC(); 4099719Sandreas.hansson@arm.com } 4109719Sandreas.hansson@arm.com 4119719Sandreas.hansson@arm.com /** 4129719Sandreas.hansson@arm.com * Regenerate block address using tags. 4139719Sandreas.hansson@arm.com * Block address regeneration depends on whether we're using a temporary 4149719Sandreas.hansson@arm.com * block or not. 4159719Sandreas.hansson@arm.com * 4169719Sandreas.hansson@arm.com * @param blk The block to regenerate address. 4179719Sandreas.hansson@arm.com * @return The block's address. 4189719Sandreas.hansson@arm.com */ 4199719Sandreas.hansson@arm.com Addr regenerateBlkAddr(CacheBlk* blk); 4209719Sandreas.hansson@arm.com 4219719Sandreas.hansson@arm.com /** 4229719Sandreas.hansson@arm.com * Calculate access latency in ticks given a tag lookup latency, and 4239719Sandreas.hansson@arm.com * whether access was a hit or miss. 4249719Sandreas.hansson@arm.com * 4259719Sandreas.hansson@arm.com * @param blk The cache block that was accessed. 4269719Sandreas.hansson@arm.com * @param lookup_lat Latency of the respective tag lookup. 4279719Sandreas.hansson@arm.com * @return The number of ticks that pass due to a block access. 4289719Sandreas.hansson@arm.com */ 4299719Sandreas.hansson@arm.com Cycles calculateAccessLatency(const CacheBlk* blk, 4309719Sandreas.hansson@arm.com const Cycles lookup_lat) const; 4319719Sandreas.hansson@arm.com 4329719Sandreas.hansson@arm.com /** 4339719Sandreas.hansson@arm.com * Does all the processing necessary to perform the provided request. 4349719Sandreas.hansson@arm.com * @param pkt The memory request to perform. 4359241Sandreas.hansson@arm.com * @param blk The cache block to be updated. 4369241Sandreas.hansson@arm.com * @param lat The latency of the access. 4379241Sandreas.hansson@arm.com * @param writebacks List for any writebacks that need to be performed. 4389241Sandreas.hansson@arm.com * @return Boolean indicating whether the request was satisfied. 4399241Sandreas.hansson@arm.com */ 4409241Sandreas.hansson@arm.com virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 4419241Sandreas.hansson@arm.com PacketList &writebacks); 4429241Sandreas.hansson@arm.com 443 /* 444 * Handle a timing request that hit in the cache 445 * 446 * @param ptk The request packet 447 * @param blk The referenced block 448 * @param request_time The tick at which the block lookup is compete 449 */ 450 virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, 451 Tick request_time); 452 453 /* 454 * Handle a timing request that missed in the cache 455 * 456 * Implementation specific handling for different cache 457 * implementations 458 * 459 * @param ptk The request packet 460 * @param blk The referenced block 461 * @param forward_time The tick at which we can process dependent requests 462 * @param request_time The tick at which the block lookup is compete 463 */ 464 virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, 465 Tick forward_time, 466 Tick request_time) = 0; 467 468 /* 469 * Handle a timing request that missed in the cache 470 * 471 * Common functionality across different cache implementations 472 * 473 * @param ptk The request packet 474 * @param blk The referenced block 475 * @param mshr Any existing mshr for the referenced cache block 476 * @param forward_time The tick at which we can process dependent requests 477 * @param request_time The tick at which the block lookup is compete 478 */ 479 void handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk, 480 Tick forward_time, Tick request_time); 481 482 /** 483 * Performs the access specified by the request. 484 * @param pkt The request to perform. 485 */ 486 virtual void recvTimingReq(PacketPtr pkt); 487 488 /** 489 * Handling the special case of uncacheable write responses to 490 * make recvTimingResp less cluttered. 491 */ 492 void handleUncacheableWriteResp(PacketPtr pkt); 493 494 /** 495 * Service non-deferred MSHR targets using the received response 496 * 497 * Iterates through the list of targets that can be serviced with 498 * the current response. 499 * 500 * @param mshr The MSHR that corresponds to the reponse 501 * @param pkt The response packet 502 * @param blk The reference block 503 */ 504 virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, 505 CacheBlk *blk) = 0; 506 507 /** 508 * Handles a response (cache line fill/write ack) from the bus. 509 * @param pkt The response packet 510 */ 511 virtual void recvTimingResp(PacketPtr pkt); 512 513 /** 514 * Snoops bus transactions to maintain coherence. 515 * @param pkt The current bus transaction. 516 */ 517 virtual void recvTimingSnoopReq(PacketPtr pkt) = 0; 518 519 /** 520 * Handle a snoop response. 521 * @param pkt Snoop response packet 522 */ 523 virtual void recvTimingSnoopResp(PacketPtr pkt) = 0; 524 525 /** 526 * Handle a request in atomic mode that missed in this cache 527 * 528 * Creates a downstream request, sends it to the memory below and 529 * handles the response. As we are in atomic mode all operations 530 * are performed immediately. 531 * 532 * @param pkt The packet with the requests 533 * @param blk The referenced block 534 * @param writebacks A list with packets for any performed writebacks 535 * @return Cycles for handling the request 536 */ 537 virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, 538 PacketList &writebacks) = 0; 539 540 /** 541 * Performs the access specified by the request. 542 * @param pkt The request to perform. 543 * @return The number of ticks required for the access. 544 */ 545 virtual Tick recvAtomic(PacketPtr pkt); 546 547 /** 548 * Snoop for the provided request in the cache and return the estimated 549 * time taken. 550 * @param pkt The memory request to snoop 551 * @return The number of ticks required for the snoop. 552 */ 553 virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0; 554 555 /** 556 * Performs the access specified by the request. 557 * 558 * @param pkt The request to perform. 559 * @param fromCpuSide from the CPU side port or the memory side port 560 */ 561 virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side); 562 563 /** 564 * Handle doing the Compare and Swap function for SPARC. 565 */ 566 void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); 567 568 /** 569 * Return the next queue entry to service, either a pending miss 570 * from the MSHR queue, a buffered write from the write buffer, or 571 * something from the prefetcher. This function is responsible 572 * for prioritizing among those sources on the fly. 573 */ 574 QueueEntry* getNextQueueEntry(); 575 576 /** 577 * Insert writebacks into the write buffer 578 */ 579 virtual void doWritebacks(PacketList& writebacks, Tick forward_time) = 0; 580 581 /** 582 * Send writebacks down the memory hierarchy in atomic mode 583 */ 584 virtual void doWritebacksAtomic(PacketList& writebacks) = 0; 585 586 /** 587 * Create an appropriate downstream bus request packet. 588 * 589 * Creates a new packet with the request to be send to the memory 590 * below, or nullptr if the current request in cpu_pkt should just 591 * be forwarded on. 592 * 593 * @param cpu_pkt The miss packet that needs to be satisfied. 594 * @param blk The referenced block, can be nullptr. 595 * @param needs_writable Indicates that the block must be writable 596 * even if the request in cpu_pkt doesn't indicate that. 597 * @param is_whole_line_write True if there are writes for the 598 * whole line 599 * @return A packet send to the memory below 600 */ 601 virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 602 bool needs_writable, 603 bool is_whole_line_write) const = 0; 604 605 /** 606 * Determine if clean lines should be written back or not. In 607 * cases where a downstream cache is mostly inclusive we likely 608 * want it to act as a victim cache also for lines that have not 609 * been modified. Hence, we cannot simply drop the line (or send a 610 * clean evict), but rather need to send the actual data. 611 */ 612 const bool writebackClean; 613 614 /** 615 * Writebacks from the tempBlock, resulting on the response path 616 * in atomic mode, must happen after the call to recvAtomic has 617 * finished (for the right ordering of the packets). We therefore 618 * need to hold on to the packets, and have a method and an event 619 * to send them. 620 */ 621 PacketPtr tempBlockWriteback; 622 623 /** 624 * Send the outstanding tempBlock writeback. To be called after 625 * recvAtomic finishes in cases where the block we filled is in 626 * fact the tempBlock, and now needs to be written back. 627 */ 628 void writebackTempBlockAtomic() { 629 assert(tempBlockWriteback != nullptr); 630 PacketList writebacks{tempBlockWriteback}; 631 doWritebacksAtomic(writebacks); 632 tempBlockWriteback = nullptr; 633 } 634 635 /** 636 * An event to writeback the tempBlock after recvAtomic 637 * finishes. To avoid other calls to recvAtomic getting in 638 * between, we create this event with a higher priority. 639 */ 640 EventFunctionWrapper writebackTempBlockAtomicEvent; 641 642 /** 643 * Perform any necessary updates to the block and perform any data 644 * exchange between the packet and the block. The flags of the 645 * packet are also set accordingly. 646 * 647 * @param pkt Request packet from upstream that hit a block 648 * @param blk Cache block that the packet hit 649 * @param deferred_response Whether this request originally missed 650 * @param pending_downgrade Whether the writable flag is to be removed 651 */ 652 virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk, 653 bool deferred_response = false, 654 bool pending_downgrade = false); 655 656 /** 657 * Maintain the clusivity of this cache by potentially 658 * invalidating a block. This method works in conjunction with 659 * satisfyRequest, but is separate to allow us to handle all MSHR 660 * targets before potentially dropping a block. 661 * 662 * @param from_cache Whether we have dealt with a packet from a cache 663 * @param blk The block that should potentially be dropped 664 */ 665 void maintainClusivity(bool from_cache, CacheBlk *blk); 666 667 /** 668 * Handle a fill operation caused by a received packet. 669 * 670 * Populates a cache block and handles all outstanding requests for the 671 * satisfied fill request. This version takes two memory requests. One 672 * contains the fill data, the other is an optional target to satisfy. 673 * Note that the reason we return a list of writebacks rather than 674 * inserting them directly in the write buffer is that this function 675 * is called by both atomic and timing-mode accesses, and in atomic 676 * mode we don't mess with the write buffer (we just perform the 677 * writebacks atomically once the original request is complete). 678 * 679 * @param pkt The memory request with the fill data. 680 * @param blk The cache block if it already exists. 681 * @param writebacks List for any writebacks that need to be performed. 682 * @param allocate Whether to allocate a block or use the temp block 683 * @return Pointer to the new cache block. 684 */ 685 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, 686 PacketList &writebacks, bool allocate); 687 688 /** 689 * Allocate a new block and perform any necessary writebacks 690 * 691 * Find a victim block and if necessary prepare writebacks for any 692 * existing data. May return nullptr if there are no replaceable 693 * blocks. If a replaceable block is found, it inserts the new block in 694 * its place. The new block, however, is not set as valid yet. 695 * 696 * @param pkt Packet holding the address to update 697 * @param writebacks A list of writeback packets for the evicted blocks 698 * @return the allocated block 699 */ 700 CacheBlk *allocateBlock(const PacketPtr pkt, PacketList &writebacks); 701 /** 702 * Evict a cache block. 703 * 704 * Performs a writeback if necesssary and invalidates the block 705 * 706 * @param blk Block to invalidate 707 * @return A packet with the writeback, can be nullptr 708 */ 709 M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk) = 0; 710 711 /** 712 * Evict a cache block. 713 * 714 * Performs a writeback if necesssary and invalidates the block 715 * 716 * @param blk Block to invalidate 717 * @param writebacks Return a list of packets with writebacks 718 */ 719 void evictBlock(CacheBlk *blk, PacketList &writebacks); 720 721 /** 722 * Invalidate a cache block. 723 * 724 * @param blk Block to invalidate 725 */ 726 void invalidateBlock(CacheBlk *blk); 727 728 /** 729 * Create a writeback request for the given block. 730 * 731 * @param blk The block to writeback. 732 * @return The writeback request for the block. 733 */ 734 PacketPtr writebackBlk(CacheBlk *blk); 735 736 /** 737 * Create a writeclean request for the given block. 738 * 739 * Creates a request that writes the block to the cache below 740 * without evicting the block from the current cache. 741 * 742 * @param blk The block to write clean. 743 * @param dest The destination of the write clean operation. 744 * @param id Use the given packet id for the write clean operation. 745 * @return The generated write clean packet. 746 */ 747 PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id); 748 749 /** 750 * Write back dirty blocks in the cache using functional accesses. 751 */ 752 virtual void memWriteback() override; 753 754 /** 755 * Invalidates all blocks in the cache. 756 * 757 * @warn Dirty cache lines will not be written back to 758 * memory. Make sure to call functionalWriteback() first if you 759 * want the to write them to memory. 760 */ 761 virtual void memInvalidate() override; 762 763 /** 764 * Determine if there are any dirty blocks in the cache. 765 * 766 * @return true if at least one block is dirty, false otherwise. 767 */ 768 bool isDirty() const; 769 770 /** 771 * Determine if an address is in the ranges covered by this 772 * cache. This is useful to filter snoops. 773 * 774 * @param addr Address to check against 775 * 776 * @return If the address in question is in range 777 */ 778 bool inRange(Addr addr) const; 779 780 /** 781 * Find next request ready time from among possible sources. 782 */ 783 Tick nextQueueReadyTime() const; 784 785 /** Block size of this cache */ 786 const unsigned blkSize; 787 788 /** 789 * The latency of tag lookup of a cache. It occurs when there is 790 * an access to the cache. 791 */ 792 const Cycles lookupLatency; 793 794 /** 795 * The latency of data access of a cache. It occurs when there is 796 * an access to the cache. 797 */ 798 const Cycles dataLatency; 799 800 /** 801 * This is the forward latency of the cache. It occurs when there 802 * is a cache miss and a request is forwarded downstream, in 803 * particular an outbound miss. 804 */ 805 const Cycles forwardLatency; 806 807 /** The latency to fill a cache block */ 808 const Cycles fillLatency; 809 810 /** 811 * The latency of sending reponse to its upper level cache/core on 812 * a linefill. The responseLatency parameter captures this 813 * latency. 814 */ 815 const Cycles responseLatency; 816 817 /** 818 * Whether tags and data are accessed sequentially. 819 */ 820 const bool sequentialAccess; 821 822 /** The number of targets for each MSHR. */ 823 const int numTarget; 824 825 /** Do we forward snoops from mem side port through to cpu side port? */ 826 bool forwardSnoops; 827 828 /** 829 * Clusivity with respect to the upstream cache, determining if we 830 * fill into both this cache and the cache above on a miss. Note 831 * that we currently do not support strict clusivity policies. 832 */ 833 const Enums::Clusivity clusivity; 834 835 /** 836 * Is this cache read only, for example the instruction cache, or 837 * table-walker cache. A cache that is read only should never see 838 * any writes, and should never get any dirty data (and hence 839 * never have to do any writebacks). 840 */ 841 const bool isReadOnly; 842 843 /** 844 * Bit vector of the blocking reasons for the access path. 845 * @sa #BlockedCause 846 */ 847 uint8_t blocked; 848 849 /** Increasing order number assigned to each incoming request. */ 850 uint64_t order; 851 852 /** Stores time the cache blocked for statistics. */ 853 Cycles blockedCycle; 854 855 /** Pointer to the MSHR that has no targets. */ 856 MSHR *noTargetMSHR; 857 858 /** The number of misses to trigger an exit event. */ 859 Counter missCount; 860 861 /** 862 * The address range to which the cache responds on the CPU side. 863 * Normally this is all possible memory addresses. */ 864 const AddrRangeList addrRanges; 865 866 public: 867 /** System we are currently operating in. */ 868 System *system; 869 870 // Statistics 871 /** 872 * @addtogroup CacheStatistics 873 * @{ 874 */ 875 876 /** Number of hits per thread for each type of command. 877 @sa Packet::Command */ 878 Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 879 /** Number of hits for demand accesses. */ 880 Stats::Formula demandHits; 881 /** Number of hit for all accesses. */ 882 Stats::Formula overallHits; 883 884 /** Number of misses per thread for each type of command. 885 @sa Packet::Command */ 886 Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 887 /** Number of misses for demand accesses. */ 888 Stats::Formula demandMisses; 889 /** Number of misses for all accesses. */ 890 Stats::Formula overallMisses; 891 892 /** 893 * Total number of cycles per thread/command spent waiting for a miss. 894 * Used to calculate the average miss latency. 895 */ 896 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 897 /** Total number of cycles spent waiting for demand misses. */ 898 Stats::Formula demandMissLatency; 899 /** Total number of cycles spent waiting for all misses. */ 900 Stats::Formula overallMissLatency; 901 902 /** The number of accesses per command and thread. */ 903 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 904 /** The number of demand accesses. */ 905 Stats::Formula demandAccesses; 906 /** The number of overall accesses. */ 907 Stats::Formula overallAccesses; 908 909 /** The miss rate per command and thread. */ 910 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 911 /** The miss rate of all demand accesses. */ 912 Stats::Formula demandMissRate; 913 /** The miss rate for all accesses. */ 914 Stats::Formula overallMissRate; 915 916 /** The average miss latency per command and thread. */ 917 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 918 /** The average miss latency for demand misses. */ 919 Stats::Formula demandAvgMissLatency; 920 /** The average miss latency for all misses. */ 921 Stats::Formula overallAvgMissLatency; 922 923 /** The total number of cycles blocked for each blocked cause. */ 924 Stats::Vector blocked_cycles; 925 /** The number of times this cache blocked for each blocked cause. */ 926 Stats::Vector blocked_causes; 927 928 /** The average number of cycles blocked for each blocked cause. */ 929 Stats::Formula avg_blocked; 930 931 /** The number of times a HW-prefetched block is evicted w/o reference. */ 932 Stats::Scalar unusedPrefetches; 933 934 /** Number of blocks written back per thread. */ 935 Stats::Vector writebacks; 936 937 /** Number of misses that hit in the MSHRs per command and thread. */ 938 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 939 /** Demand misses that hit in the MSHRs. */ 940 Stats::Formula demandMshrHits; 941 /** Total number of misses that hit in the MSHRs. */ 942 Stats::Formula overallMshrHits; 943 944 /** Number of misses that miss in the MSHRs, per command and thread. */ 945 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 946 /** Demand misses that miss in the MSHRs. */ 947 Stats::Formula demandMshrMisses; 948 /** Total number of misses that miss in the MSHRs. */ 949 Stats::Formula overallMshrMisses; 950 951 /** Number of misses that miss in the MSHRs, per command and thread. */ 952 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 953 /** Total number of misses that miss in the MSHRs. */ 954 Stats::Formula overallMshrUncacheable; 955 956 /** Total cycle latency of each MSHR miss, per command and thread. */ 957 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 958 /** Total cycle latency of demand MSHR misses. */ 959 Stats::Formula demandMshrMissLatency; 960 /** Total cycle latency of overall MSHR misses. */ 961 Stats::Formula overallMshrMissLatency; 962 963 /** Total cycle latency of each MSHR miss, per command and thread. */ 964 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 965 /** Total cycle latency of overall MSHR misses. */ 966 Stats::Formula overallMshrUncacheableLatency; 967 968#if 0 969 /** The total number of MSHR accesses per command and thread. */ 970 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 971 /** The total number of demand MSHR accesses. */ 972 Stats::Formula demandMshrAccesses; 973 /** The total number of MSHR accesses. */ 974 Stats::Formula overallMshrAccesses; 975#endif 976 977 /** The miss rate in the MSHRs pre command and thread. */ 978 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 979 /** The demand miss rate in the MSHRs. */ 980 Stats::Formula demandMshrMissRate; 981 /** The overall miss rate in the MSHRs. */ 982 Stats::Formula overallMshrMissRate; 983 984 /** The average latency of an MSHR miss, per command and thread. */ 985 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 986 /** The average latency of a demand MSHR miss. */ 987 Stats::Formula demandAvgMshrMissLatency; 988 /** The average overall latency of an MSHR miss. */ 989 Stats::Formula overallAvgMshrMissLatency; 990 991 /** The average latency of an MSHR miss, per command and thread. */ 992 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 993 /** The average overall latency of an MSHR miss. */ 994 Stats::Formula overallAvgMshrUncacheableLatency; 995 996 /** Number of replacements of valid blocks. */ 997 Stats::Scalar replacements; 998 999 /** 1000 * @} 1001 */ 1002 1003 /** 1004 * Register stats for this object. 1005 */ 1006 void regStats() override; 1007 1008 /** Registers probes. */ 1009 void regProbePoints() override; 1010 1011 public: 1012 BaseCache(const BaseCacheParams *p, unsigned blk_size); 1013 ~BaseCache(); 1014 1015 void init() override; 1016 1017 BaseMasterPort &getMasterPort(const std::string &if_name, 1018 PortID idx = InvalidPortID) override; 1019 BaseSlavePort &getSlavePort(const std::string &if_name, 1020 PortID idx = InvalidPortID) override; 1021 1022 /** 1023 * Query block size of a cache. 1024 * @return The block size 1025 */ 1026 unsigned 1027 getBlockSize() const 1028 { 1029 return blkSize; 1030 } 1031 1032 const AddrRangeList &getAddrRanges() const { return addrRanges; } 1033 1034 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true) 1035 { 1036 MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize, 1037 pkt, time, order++, 1038 allocOnFill(pkt->cmd)); 1039 1040 if (mshrQueue.isFull()) { 1041 setBlocked((BlockedCause)MSHRQueue_MSHRs); 1042 } 1043 1044 if (sched_send) { 1045 // schedule the send 1046 schedMemSideSendEvent(time); 1047 } 1048 1049 return mshr; 1050 } 1051 1052 void allocateWriteBuffer(PacketPtr pkt, Tick time) 1053 { 1054 // should only see writes or clean evicts here 1055 assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict); 1056 1057 Addr blk_addr = pkt->getBlockAddr(blkSize); 1058 1059 WriteQueueEntry *wq_entry = 1060 writeBuffer.findMatch(blk_addr, pkt->isSecure()); 1061 if (wq_entry && !wq_entry->inService) { 1062 DPRINTF(Cache, "Potential to merge writeback %s", pkt->print()); 1063 } 1064 1065 writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++); 1066 1067 if (writeBuffer.isFull()) { 1068 setBlocked((BlockedCause)MSHRQueue_WriteBuffer); 1069 } 1070 1071 // schedule the send 1072 schedMemSideSendEvent(time); 1073 } 1074 1075 /** 1076 * Returns true if the cache is blocked for accesses. 1077 */ 1078 bool isBlocked() const 1079 { 1080 return blocked != 0; 1081 } 1082 1083 /** 1084 * Marks the access path of the cache as blocked for the given cause. This 1085 * also sets the blocked flag in the slave interface. 1086 * @param cause The reason for the cache blocking. 1087 */ 1088 void setBlocked(BlockedCause cause) 1089 { 1090 uint8_t flag = 1 << cause; 1091 if (blocked == 0) { 1092 blocked_causes[cause]++; 1093 blockedCycle = curCycle(); 1094 cpuSidePort.setBlocked(); 1095 } 1096 blocked |= flag; 1097 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 1098 } 1099 1100 /** 1101 * Marks the cache as unblocked for the given cause. This also clears the 1102 * blocked flags in the appropriate interfaces. 1103 * @param cause The newly unblocked cause. 1104 * @warning Calling this function can cause a blocked request on the bus to 1105 * access the cache. The cache must be in a state to handle that request. 1106 */ 1107 void clearBlocked(BlockedCause cause) 1108 { 1109 uint8_t flag = 1 << cause; 1110 blocked &= ~flag; 1111 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 1112 if (blocked == 0) { 1113 blocked_cycles[cause] += curCycle() - blockedCycle; 1114 cpuSidePort.clearBlocked(); 1115 } 1116 } 1117 1118 /** 1119 * Schedule a send event for the memory-side port. If already 1120 * scheduled, this may reschedule the event at an earlier 1121 * time. When the specified time is reached, the port is free to 1122 * send either a response, a request, or a prefetch request. 1123 * 1124 * @param time The time when to attempt sending a packet. 1125 */ 1126 void schedMemSideSendEvent(Tick time) 1127 { 1128 memSidePort.schedSendEvent(time); 1129 } 1130 1131 bool inCache(Addr addr, bool is_secure) const { 1132 return tags->findBlock(addr, is_secure); 1133 } 1134 1135 bool inMissQueue(Addr addr, bool is_secure) const { 1136 return mshrQueue.findMatch(addr, is_secure); 1137 } 1138 1139 void incMissCount(PacketPtr pkt) 1140 { 1141 assert(pkt->req->masterId() < system->maxMasters()); 1142 misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 1143 pkt->req->incAccessDepth(); 1144 if (missCount) { 1145 --missCount; 1146 if (missCount == 0) 1147 exitSimLoop("A cache reached the maximum miss count"); 1148 } 1149 } 1150 void incHitCount(PacketPtr pkt) 1151 { 1152 assert(pkt->req->masterId() < system->maxMasters()); 1153 hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 1154 1155 } 1156 1157 /** 1158 * Checks if the cache is coalescing writes 1159 * 1160 * @return True if the cache is coalescing writes 1161 */ 1162 bool coalesce() const; 1163 1164 1165 /** 1166 * Cache block visitor that writes back dirty cache blocks using 1167 * functional writes. 1168 */ 1169 void writebackVisitor(CacheBlk &blk); 1170 1171 /** 1172 * Cache block visitor that invalidates all blocks in the cache. 1173 * 1174 * @warn Dirty cache lines will not be written back to memory. 1175 */ 1176 void invalidateVisitor(CacheBlk &blk); 1177 1178 /** 1179 * Take an MSHR, turn it into a suitable downstream packet, and 1180 * send it out. This construct allows a queue entry to choose a suitable 1181 * approach based on its type. 1182 * 1183 * @param mshr The MSHR to turn into a packet and send 1184 * @return True if the port is waiting for a retry 1185 */ 1186 virtual bool sendMSHRQueuePacket(MSHR* mshr); 1187 1188 /** 1189 * Similar to sendMSHR, but for a write-queue entry 1190 * instead. Create the packet, and send it, and if successful also 1191 * mark the entry in service. 1192 * 1193 * @param wq_entry The write-queue entry to turn into a packet and send 1194 * @return True if the port is waiting for a retry 1195 */ 1196 bool sendWriteQueuePacket(WriteQueueEntry* wq_entry); 1197 1198 /** 1199 * Serialize the state of the caches 1200 * 1201 * We currently don't support checkpointing cache state, so this panics. 1202 */ 1203 void serialize(CheckpointOut &cp) const override; 1204 void unserialize(CheckpointIn &cp) override; 1205}; 1206 1207/** 1208 * The write allocator inspects write packets and detects streaming 1209 * patterns. The write allocator supports a single stream where writes 1210 * are expected to access consecutive locations and keeps track of 1211 * size of the area covered by the concecutive writes in byteCount. 1212 * 1213 * 1) When byteCount has surpassed the coallesceLimit the mode 1214 * switches from ALLOCATE to COALESCE where writes should be delayed 1215 * until the whole block is written at which point a single packet 1216 * (whole line write) can service them. 1217 * 1218 * 2) When byteCount has also exceeded the noAllocateLimit (whole 1219 * line) we switch to NO_ALLOCATE when writes should not allocate in 1220 * the cache but rather send a whole line write to the memory below. 1221 */ 1222class WriteAllocator : public SimObject { 1223 public: 1224 WriteAllocator(const WriteAllocatorParams *p) : 1225 SimObject(p), 1226 coalesceLimit(p->coalesce_limit * p->block_size), 1227 noAllocateLimit(p->no_allocate_limit * p->block_size), 1228 delayThreshold(p->delay_threshold) 1229 { 1230 reset(); 1231 } 1232 1233 /** 1234 * Should writes be coalesced? This is true if the mode is set to 1235 * NO_ALLOCATE. 1236 * 1237 * @return return true if the cache should coalesce writes. 1238 */ 1239 bool coalesce() const { 1240 return mode != WriteMode::ALLOCATE; 1241 } 1242 1243 /** 1244 * Should writes allocate? 1245 * 1246 * @return return true if the cache should not allocate for writes. 1247 */ 1248 bool allocate() const { 1249 return mode != WriteMode::NO_ALLOCATE; 1250 } 1251 1252 /** 1253 * Reset the write allocator state, meaning that it allocates for 1254 * writes and has not recorded any information about qualifying 1255 * writes that might trigger a switch to coalescing and later no 1256 * allocation. 1257 */ 1258 void reset() { 1259 mode = WriteMode::ALLOCATE; 1260 byteCount = 0; 1261 nextAddr = 0; 1262 } 1263 1264 /** 1265 * Access whether we need to delay the current write. 1266 * 1267 * @param blk_addr The block address the packet writes to 1268 * @return true if the current packet should be delayed 1269 */ 1270 bool delay(Addr blk_addr) { 1271 if (delayCtr[blk_addr] > 0) { 1272 --delayCtr[blk_addr]; 1273 return true; 1274 } else { 1275 return false; 1276 } 1277 } 1278 1279 /** 1280 * Clear delay counter for the input block 1281 * 1282 * @param blk_addr The accessed cache block 1283 */ 1284 void resetDelay(Addr blk_addr) { 1285 delayCtr.erase(blk_addr); 1286 } 1287 1288 /** 1289 * Update the write mode based on the current write 1290 * packet. This method compares the packet's address with any 1291 * current stream, and updates the tracking and the mode 1292 * accordingly. 1293 * 1294 * @param write_addr Start address of the write request 1295 * @param write_size Size of the write request 1296 * @param blk_addr The block address that this packet writes to 1297 */ 1298 void updateMode(Addr write_addr, unsigned write_size, Addr blk_addr); 1299 1300 private: 1301 /** 1302 * The current mode for write coalescing and allocation, either 1303 * normal operation (ALLOCATE), write coalescing (COALESCE), or 1304 * write coalescing without allocation (NO_ALLOCATE). 1305 */ 1306 enum class WriteMode : char { 1307 ALLOCATE, 1308 COALESCE, 1309 NO_ALLOCATE, 1310 }; 1311 WriteMode mode; 1312 1313 /** Address to match writes against to detect streams. */ 1314 Addr nextAddr; 1315 1316 /** 1317 * Bytes written contiguously. Saturating once we no longer 1318 * allocate. 1319 */ 1320 uint32_t byteCount; 1321 1322 /** 1323 * Limits for when to switch between the different write modes. 1324 */ 1325 const uint32_t coalesceLimit; 1326 const uint32_t noAllocateLimit; 1327 /** 1328 * The number of times the allocator will delay an WriteReq MSHR. 1329 */ 1330 const uint32_t delayThreshold; 1331 1332 /** 1333 * Keep track of the number of times the allocator has delayed an 1334 * WriteReq MSHR. 1335 */ 1336 std::unordered_map<Addr, Counter> delayCtr; 1337}; 1338 1339#endif //__MEM_CACHE_BASE_HH__ 1340