base.hh revision 13350:247e4108a5e8
1/*
2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 *          Steve Reinhardt
42 *          Ron Dreslinski
43 *          Andreas Hansson
44 *          Nikos Nikoleris
45 */
46
47/**
48 * @file
49 * Declares a basic cache interface BaseCache.
50 */
51
52#ifndef __MEM_CACHE_BASE_HH__
53#define __MEM_CACHE_BASE_HH__
54
55#include <cassert>
56#include <cstdint>
57#include <string>
58
59#include "base/addr_range.hh"
60#include "base/statistics.hh"
61#include "base/trace.hh"
62#include "base/types.hh"
63#include "debug/Cache.hh"
64#include "debug/CachePort.hh"
65#include "enums/Clusivity.hh"
66#include "mem/cache/cache_blk.hh"
67#include "mem/cache/mshr_queue.hh"
68#include "mem/cache/tags/base.hh"
69#include "mem/cache/write_queue.hh"
70#include "mem/cache/write_queue_entry.hh"
71#include "mem/mem_object.hh"
72#include "mem/packet.hh"
73#include "mem/packet_queue.hh"
74#include "mem/qport.hh"
75#include "mem/request.hh"
76#include "sim/eventq.hh"
77#include "sim/serialize.hh"
78#include "sim/sim_exit.hh"
79#include "sim/system.hh"
80
81class BaseMasterPort;
82class BasePrefetcher;
83class BaseSlavePort;
84class MSHR;
85class MasterPort;
86class QueueEntry;
87struct BaseCacheParams;
88
89/**
90 * A basic cache interface. Implements some common functions for speed.
91 */
92class BaseCache : public MemObject
93{
94  protected:
95    /**
96     * Indexes to enumerate the MSHR queues.
97     */
98    enum MSHRQueueIndex {
99        MSHRQueue_MSHRs,
100        MSHRQueue_WriteBuffer
101    };
102
103  public:
104    /**
105     * Reasons for caches to be blocked.
106     */
107    enum BlockedCause {
108        Blocked_NoMSHRs = MSHRQueue_MSHRs,
109        Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
110        Blocked_NoTargets,
111        NUM_BLOCKED_CAUSES
112    };
113
114  protected:
115
116    /**
117     * A cache master port is used for the memory-side port of the
118     * cache, and in addition to the basic timing port that only sends
119     * response packets through a transmit list, it also offers the
120     * ability to schedule and send request packets (requests &
121     * writebacks). The send event is scheduled through schedSendEvent,
122     * and the sendDeferredPacket of the timing port is modified to
123     * consider both the transmit list and the requests from the MSHR.
124     */
125    class CacheMasterPort : public QueuedMasterPort
126    {
127
128      public:
129
130        /**
131         * Schedule a send of a request packet (from the MSHR). Note
132         * that we could already have a retry outstanding.
133         */
134        void schedSendEvent(Tick time)
135        {
136            DPRINTF(CachePort, "Scheduling send event at %llu\n", time);
137            reqQueue.schedSendEvent(time);
138        }
139
140      protected:
141
142        CacheMasterPort(const std::string &_name, BaseCache *_cache,
143                        ReqPacketQueue &_reqQueue,
144                        SnoopRespPacketQueue &_snoopRespQueue) :
145            QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue)
146        { }
147
148        /**
149         * Memory-side port always snoops.
150         *
151         * @return always true
152         */
153        virtual bool isSnooping() const { return true; }
154    };
155
156    /**
157     * Override the default behaviour of sendDeferredPacket to enable
158     * the memory-side cache port to also send requests based on the
159     * current MSHR status. This queue has a pointer to our specific
160     * cache implementation and is used by the MemSidePort.
161     */
162    class CacheReqPacketQueue : public ReqPacketQueue
163    {
164
165      protected:
166
167        BaseCache &cache;
168        SnoopRespPacketQueue &snoopRespQueue;
169
170      public:
171
172        CacheReqPacketQueue(BaseCache &cache, MasterPort &port,
173                            SnoopRespPacketQueue &snoop_resp_queue,
174                            const std::string &label) :
175            ReqPacketQueue(cache, port, label), cache(cache),
176            snoopRespQueue(snoop_resp_queue) { }
177
178        /**
179         * Override the normal sendDeferredPacket and do not only
180         * consider the transmit list (used for responses), but also
181         * requests.
182         */
183        virtual void sendDeferredPacket();
184
185        /**
186         * Check if there is a conflicting snoop response about to be
187         * send out, and if so simply stall any requests, and schedule
188         * a send event at the same time as the next snoop response is
189         * being sent out.
190         */
191        bool checkConflictingSnoop(Addr addr)
192        {
193            if (snoopRespQueue.hasAddr(addr)) {
194                DPRINTF(CachePort, "Waiting for snoop response to be "
195                        "sent\n");
196                Tick when = snoopRespQueue.deferredPacketReadyTime();
197                schedSendEvent(when);
198                return true;
199            }
200            return false;
201        }
202    };
203
204
205    /**
206     * The memory-side port extends the base cache master port with
207     * access functions for functional, atomic and timing snoops.
208     */
209    class MemSidePort : public CacheMasterPort
210    {
211      private:
212
213        /** The cache-specific queue. */
214        CacheReqPacketQueue _reqQueue;
215
216        SnoopRespPacketQueue _snoopRespQueue;
217
218        // a pointer to our specific cache implementation
219        BaseCache *cache;
220
221      protected:
222
223        virtual void recvTimingSnoopReq(PacketPtr pkt);
224
225        virtual bool recvTimingResp(PacketPtr pkt);
226
227        virtual Tick recvAtomicSnoop(PacketPtr pkt);
228
229        virtual void recvFunctionalSnoop(PacketPtr pkt);
230
231      public:
232
233        MemSidePort(const std::string &_name, BaseCache *_cache,
234                    const std::string &_label);
235    };
236
237    /**
238     * A cache slave port is used for the CPU-side port of the cache,
239     * and it is basically a simple timing port that uses a transmit
240     * list for responses to the CPU (or connected master). In
241     * addition, it has the functionality to block the port for
242     * incoming requests. If blocked, the port will issue a retry once
243     * unblocked.
244     */
245    class CacheSlavePort : public QueuedSlavePort
246    {
247
248      public:
249
250        /** Do not accept any new requests. */
251        void setBlocked();
252
253        /** Return to normal operation and accept new requests. */
254        void clearBlocked();
255
256        bool isBlocked() const { return blocked; }
257
258      protected:
259
260        CacheSlavePort(const std::string &_name, BaseCache *_cache,
261                       const std::string &_label);
262
263        /** A normal packet queue used to store responses. */
264        RespPacketQueue queue;
265
266        bool blocked;
267
268        bool mustSendRetry;
269
270      private:
271
272        void processSendRetry();
273
274        EventFunctionWrapper sendRetryEvent;
275
276    };
277
278    /**
279     * The CPU-side port extends the base cache slave port with access
280     * functions for functional, atomic and timing requests.
281     */
282    class CpuSidePort : public CacheSlavePort
283    {
284      private:
285
286        // a pointer to our specific cache implementation
287        BaseCache *cache;
288
289      protected:
290        virtual bool recvTimingSnoopResp(PacketPtr pkt) override;
291
292        virtual bool tryTiming(PacketPtr pkt) override;
293
294        virtual bool recvTimingReq(PacketPtr pkt) override;
295
296        virtual Tick recvAtomic(PacketPtr pkt) override;
297
298        virtual void recvFunctional(PacketPtr pkt) override;
299
300        virtual AddrRangeList getAddrRanges() const override;
301
302      public:
303
304        CpuSidePort(const std::string &_name, BaseCache *_cache,
305                    const std::string &_label);
306
307    };
308
309    CpuSidePort cpuSidePort;
310    MemSidePort memSidePort;
311
312  protected:
313
314    /** Miss status registers */
315    MSHRQueue mshrQueue;
316
317    /** Write/writeback buffer */
318    WriteQueue writeBuffer;
319
320    /** Tag and data Storage */
321    BaseTags *tags;
322
323    /** Prefetcher */
324    BasePrefetcher *prefetcher;
325
326    /**
327     * Notify the prefetcher on every access, not just misses.
328     */
329    const bool prefetchOnAccess;
330
331    /**
332     * Temporary cache block for occasional transitory use.  We use
333     * the tempBlock to fill when allocation fails (e.g., when there
334     * is an outstanding request that accesses the victim block) or
335     * when we want to avoid allocation (e.g., exclusive caches)
336     */
337    TempCacheBlk *tempBlock;
338
339    /**
340     * Upstream caches need this packet until true is returned, so
341     * hold it for deletion until a subsequent call
342     */
343    std::unique_ptr<Packet> pendingDelete;
344
345    /**
346     * Mark a request as in service (sent downstream in the memory
347     * system), effectively making this MSHR the ordering point.
348     */
349    void markInService(MSHR *mshr, bool pending_modified_resp)
350    {
351        bool wasFull = mshrQueue.isFull();
352        mshrQueue.markInService(mshr, pending_modified_resp);
353
354        if (wasFull && !mshrQueue.isFull()) {
355            clearBlocked(Blocked_NoMSHRs);
356        }
357    }
358
359    void markInService(WriteQueueEntry *entry)
360    {
361        bool wasFull = writeBuffer.isFull();
362        writeBuffer.markInService(entry);
363
364        if (wasFull && !writeBuffer.isFull()) {
365            clearBlocked(Blocked_NoWBBuffers);
366        }
367    }
368
369    /**
370     * Determine whether we should allocate on a fill or not. If this
371     * cache is mostly inclusive with regards to the upstream cache(s)
372     * we always allocate (for any non-forwarded and cacheable
373     * requests). In the case of a mostly exclusive cache, we allocate
374     * on fill if the packet did not come from a cache, thus if we:
375     * are dealing with a whole-line write (the latter behaves much
376     * like a writeback), the original target packet came from a
377     * non-caching source, or if we are performing a prefetch or LLSC.
378     *
379     * @param cmd Command of the incoming requesting packet
380     * @return Whether we should allocate on the fill
381     */
382    inline bool allocOnFill(MemCmd cmd) const
383    {
384        return clusivity == Enums::mostly_incl ||
385            cmd == MemCmd::WriteLineReq ||
386            cmd == MemCmd::ReadReq ||
387            cmd == MemCmd::WriteReq ||
388            cmd.isPrefetch() ||
389            cmd.isLLSC();
390    }
391
392    /**
393     * Regenerate block address using tags.
394     * Block address regeneration depends on whether we're using a temporary
395     * block or not.
396     *
397     * @param blk The block to regenerate address.
398     * @return The block's address.
399     */
400    Addr regenerateBlkAddr(CacheBlk* blk);
401
402    /**
403     * Does all the processing necessary to perform the provided request.
404     * @param pkt The memory request to perform.
405     * @param blk The cache block to be updated.
406     * @param lat The latency of the access.
407     * @param writebacks List for any writebacks that need to be performed.
408     * @return Boolean indicating whether the request was satisfied.
409     */
410    virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
411                        PacketList &writebacks);
412
413    /*
414     * Handle a timing request that hit in the cache
415     *
416     * @param ptk The request packet
417     * @param blk The referenced block
418     * @param request_time The tick at which the block lookup is compete
419     */
420    virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
421                                    Tick request_time);
422
423    /*
424     * Handle a timing request that missed in the cache
425     *
426     * Implementation specific handling for different cache
427     * implementations
428     *
429     * @param ptk The request packet
430     * @param blk The referenced block
431     * @param forward_time The tick at which we can process dependent requests
432     * @param request_time The tick at which the block lookup is compete
433     */
434    virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
435                                     Tick forward_time,
436                                     Tick request_time) = 0;
437
438    /*
439     * Handle a timing request that missed in the cache
440     *
441     * Common functionality across different cache implementations
442     *
443     * @param ptk The request packet
444     * @param blk The referenced block
445     * @param mshr Any existing mshr for the referenced cache block
446     * @param forward_time The tick at which we can process dependent requests
447     * @param request_time The tick at which the block lookup is compete
448     */
449    void handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk,
450                             Tick forward_time, Tick request_time);
451
452    /**
453     * Performs the access specified by the request.
454     * @param pkt The request to perform.
455     */
456    virtual void recvTimingReq(PacketPtr pkt);
457
458    /**
459     * Handling the special case of uncacheable write responses to
460     * make recvTimingResp less cluttered.
461     */
462    void handleUncacheableWriteResp(PacketPtr pkt);
463
464    /**
465     * Service non-deferred MSHR targets using the received response
466     *
467     * Iterates through the list of targets that can be serviced with
468     * the current response. Any writebacks that need to performed
469     * must be appended to the writebacks parameter.
470     *
471     * @param mshr The MSHR that corresponds to the reponse
472     * @param pkt The response packet
473     * @param blk The reference block
474     * @param writebacks List of writebacks that need to be performed
475     */
476    virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
477                                    CacheBlk *blk, PacketList& writebacks) = 0;
478
479    /**
480     * Handles a response (cache line fill/write ack) from the bus.
481     * @param pkt The response packet
482     */
483    virtual void recvTimingResp(PacketPtr pkt);
484
485    /**
486     * Snoops bus transactions to maintain coherence.
487     * @param pkt The current bus transaction.
488     */
489    virtual void recvTimingSnoopReq(PacketPtr pkt) = 0;
490
491    /**
492     * Handle a snoop response.
493     * @param pkt Snoop response packet
494     */
495    virtual void recvTimingSnoopResp(PacketPtr pkt) = 0;
496
497    /**
498     * Handle a request in atomic mode that missed in this cache
499     *
500     * Creates a downstream request, sends it to the memory below and
501     * handles the response. As we are in atomic mode all operations
502     * are performed immediately.
503     *
504     * @param pkt The packet with the requests
505     * @param blk The referenced block
506     * @param writebacks A list with packets for any performed writebacks
507     * @return Cycles for handling the request
508     */
509    virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
510                                       PacketList &writebacks) = 0;
511
512    /**
513     * Performs the access specified by the request.
514     * @param pkt The request to perform.
515     * @return The number of ticks required for the access.
516     */
517    virtual Tick recvAtomic(PacketPtr pkt);
518
519    /**
520     * Snoop for the provided request in the cache and return the estimated
521     * time taken.
522     * @param pkt The memory request to snoop
523     * @return The number of ticks required for the snoop.
524     */
525    virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0;
526
527    /**
528     * Performs the access specified by the request.
529     *
530     * @param pkt The request to perform.
531     * @param fromCpuSide from the CPU side port or the memory side port
532     */
533    virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side);
534
535    /**
536     * Handle doing the Compare and Swap function for SPARC.
537     */
538    void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
539
540    /**
541     * Return the next queue entry to service, either a pending miss
542     * from the MSHR queue, a buffered write from the write buffer, or
543     * something from the prefetcher. This function is responsible
544     * for prioritizing among those sources on the fly.
545     */
546    QueueEntry* getNextQueueEntry();
547
548    /**
549     * Insert writebacks into the write buffer
550     */
551    virtual void doWritebacks(PacketList& writebacks, Tick forward_time) = 0;
552
553    /**
554     * Send writebacks down the memory hierarchy in atomic mode
555     */
556    virtual void doWritebacksAtomic(PacketList& writebacks) = 0;
557
558    /**
559     * Create an appropriate downstream bus request packet.
560     *
561     * Creates a new packet with the request to be send to the memory
562     * below, or nullptr if the current request in cpu_pkt should just
563     * be forwarded on.
564     *
565     * @param cpu_pkt The miss packet that needs to be satisfied.
566     * @param blk The referenced block, can be nullptr.
567     * @param needs_writable Indicates that the block must be writable
568     * even if the request in cpu_pkt doesn't indicate that.
569     * @param is_whole_line_write True if there are writes for the
570     * whole line
571     * @return A packet send to the memory below
572     */
573    virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
574                                       bool needs_writable,
575                                       bool is_whole_line_write) const = 0;
576
577    /**
578     * Determine if clean lines should be written back or not. In
579     * cases where a downstream cache is mostly inclusive we likely
580     * want it to act as a victim cache also for lines that have not
581     * been modified. Hence, we cannot simply drop the line (or send a
582     * clean evict), but rather need to send the actual data.
583     */
584    const bool writebackClean;
585
586    /**
587     * Writebacks from the tempBlock, resulting on the response path
588     * in atomic mode, must happen after the call to recvAtomic has
589     * finished (for the right ordering of the packets). We therefore
590     * need to hold on to the packets, and have a method and an event
591     * to send them.
592     */
593    PacketPtr tempBlockWriteback;
594
595    /**
596     * Send the outstanding tempBlock writeback. To be called after
597     * recvAtomic finishes in cases where the block we filled is in
598     * fact the tempBlock, and now needs to be written back.
599     */
600    void writebackTempBlockAtomic() {
601        assert(tempBlockWriteback != nullptr);
602        PacketList writebacks{tempBlockWriteback};
603        doWritebacksAtomic(writebacks);
604        tempBlockWriteback = nullptr;
605    }
606
607    /**
608     * An event to writeback the tempBlock after recvAtomic
609     * finishes. To avoid other calls to recvAtomic getting in
610     * between, we create this event with a higher priority.
611     */
612    EventFunctionWrapper writebackTempBlockAtomicEvent;
613
614    /**
615     * Perform any necessary updates to the block and perform any data
616     * exchange between the packet and the block. The flags of the
617     * packet are also set accordingly.
618     *
619     * @param pkt Request packet from upstream that hit a block
620     * @param blk Cache block that the packet hit
621     * @param deferred_response Whether this request originally missed
622     * @param pending_downgrade Whether the writable flag is to be removed
623     */
624    virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
625                                bool deferred_response = false,
626                                bool pending_downgrade = false);
627
628    /**
629     * Maintain the clusivity of this cache by potentially
630     * invalidating a block. This method works in conjunction with
631     * satisfyRequest, but is separate to allow us to handle all MSHR
632     * targets before potentially dropping a block.
633     *
634     * @param from_cache Whether we have dealt with a packet from a cache
635     * @param blk The block that should potentially be dropped
636     */
637    void maintainClusivity(bool from_cache, CacheBlk *blk);
638
639    /**
640     * Handle a fill operation caused by a received packet.
641     *
642     * Populates a cache block and handles all outstanding requests for the
643     * satisfied fill request. This version takes two memory requests. One
644     * contains the fill data, the other is an optional target to satisfy.
645     * Note that the reason we return a list of writebacks rather than
646     * inserting them directly in the write buffer is that this function
647     * is called by both atomic and timing-mode accesses, and in atomic
648     * mode we don't mess with the write buffer (we just perform the
649     * writebacks atomically once the original request is complete).
650     *
651     * @param pkt The memory request with the fill data.
652     * @param blk The cache block if it already exists.
653     * @param writebacks List for any writebacks that need to be performed.
654     * @param allocate Whether to allocate a block or use the temp block
655     * @return Pointer to the new cache block.
656     */
657    CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
658                         PacketList &writebacks, bool allocate);
659
660    /**
661     * Allocate a new block and perform any necessary writebacks
662     *
663     * Find a victim block and if necessary prepare writebacks for any
664     * existing data. May return nullptr if there are no replaceable
665     * blocks. If a replaceable block is found, it inserts the new block in
666     * its place. The new block, however, is not set as valid yet.
667     *
668     * @param pkt Packet holding the address to update
669     * @param writebacks A list of writeback packets for the evicted blocks
670     * @return the allocated block
671     */
672    CacheBlk *allocateBlock(const PacketPtr pkt, PacketList &writebacks);
673    /**
674     * Evict a cache block.
675     *
676     * Performs a writeback if necesssary and invalidates the block
677     *
678     * @param blk Block to invalidate
679     * @return A packet with the writeback, can be nullptr
680     */
681    M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk) = 0;
682
683    /**
684     * Evict a cache block.
685     *
686     * Performs a writeback if necesssary and invalidates the block
687     *
688     * @param blk Block to invalidate
689     * @param writebacks Return a list of packets with writebacks
690     */
691    virtual void evictBlock(CacheBlk *blk, PacketList &writebacks) = 0;
692
693    /**
694     * Invalidate a cache block.
695     *
696     * @param blk Block to invalidate
697     */
698    void invalidateBlock(CacheBlk *blk);
699
700    /**
701     * Create a writeback request for the given block.
702     *
703     * @param blk The block to writeback.
704     * @return The writeback request for the block.
705     */
706    PacketPtr writebackBlk(CacheBlk *blk);
707
708    /**
709     * Create a writeclean request for the given block.
710     *
711     * Creates a request that writes the block to the cache below
712     * without evicting the block from the current cache.
713     *
714     * @param blk The block to write clean.
715     * @param dest The destination of the write clean operation.
716     * @param id Use the given packet id for the write clean operation.
717     * @return The generated write clean packet.
718     */
719    PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id);
720
721    /**
722     * Write back dirty blocks in the cache using functional accesses.
723     */
724    virtual void memWriteback() override;
725
726    /**
727     * Invalidates all blocks in the cache.
728     *
729     * @warn Dirty cache lines will not be written back to
730     * memory. Make sure to call functionalWriteback() first if you
731     * want the to write them to memory.
732     */
733    virtual void memInvalidate() override;
734
735    /**
736     * Determine if there are any dirty blocks in the cache.
737     *
738     * @return true if at least one block is dirty, false otherwise.
739     */
740    bool isDirty() const;
741
742    /**
743     * Determine if an address is in the ranges covered by this
744     * cache. This is useful to filter snoops.
745     *
746     * @param addr Address to check against
747     *
748     * @return If the address in question is in range
749     */
750    bool inRange(Addr addr) const;
751
752    /**
753     * Find next request ready time from among possible sources.
754     */
755    Tick nextQueueReadyTime() const;
756
757    /** Block size of this cache */
758    const unsigned blkSize;
759
760    /**
761     * The latency of tag lookup of a cache. It occurs when there is
762     * an access to the cache.
763     */
764    const Cycles lookupLatency;
765
766    /**
767     * The latency of data access of a cache. It occurs when there is
768     * an access to the cache.
769     */
770    const Cycles dataLatency;
771
772    /**
773     * This is the forward latency of the cache. It occurs when there
774     * is a cache miss and a request is forwarded downstream, in
775     * particular an outbound miss.
776     */
777    const Cycles forwardLatency;
778
779    /** The latency to fill a cache block */
780    const Cycles fillLatency;
781
782    /**
783     * The latency of sending reponse to its upper level cache/core on
784     * a linefill. The responseLatency parameter captures this
785     * latency.
786     */
787    const Cycles responseLatency;
788
789    /** The number of targets for each MSHR. */
790    const int numTarget;
791
792    /** Do we forward snoops from mem side port through to cpu side port? */
793    bool forwardSnoops;
794
795    /**
796     * Clusivity with respect to the upstream cache, determining if we
797     * fill into both this cache and the cache above on a miss. Note
798     * that we currently do not support strict clusivity policies.
799     */
800    const Enums::Clusivity clusivity;
801
802    /**
803     * Is this cache read only, for example the instruction cache, or
804     * table-walker cache. A cache that is read only should never see
805     * any writes, and should never get any dirty data (and hence
806     * never have to do any writebacks).
807     */
808    const bool isReadOnly;
809
810    /**
811     * Bit vector of the blocking reasons for the access path.
812     * @sa #BlockedCause
813     */
814    uint8_t blocked;
815
816    /** Increasing order number assigned to each incoming request. */
817    uint64_t order;
818
819    /** Stores time the cache blocked for statistics. */
820    Cycles blockedCycle;
821
822    /** Pointer to the MSHR that has no targets. */
823    MSHR *noTargetMSHR;
824
825    /** The number of misses to trigger an exit event. */
826    Counter missCount;
827
828    /**
829     * The address range to which the cache responds on the CPU side.
830     * Normally this is all possible memory addresses. */
831    const AddrRangeList addrRanges;
832
833  public:
834    /** System we are currently operating in. */
835    System *system;
836
837    // Statistics
838    /**
839     * @addtogroup CacheStatistics
840     * @{
841     */
842
843    /** Number of hits per thread for each type of command.
844        @sa Packet::Command */
845    Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
846    /** Number of hits for demand accesses. */
847    Stats::Formula demandHits;
848    /** Number of hit for all accesses. */
849    Stats::Formula overallHits;
850
851    /** Number of misses per thread for each type of command.
852        @sa Packet::Command */
853    Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
854    /** Number of misses for demand accesses. */
855    Stats::Formula demandMisses;
856    /** Number of misses for all accesses. */
857    Stats::Formula overallMisses;
858
859    /**
860     * Total number of cycles per thread/command spent waiting for a miss.
861     * Used to calculate the average miss latency.
862     */
863    Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
864    /** Total number of cycles spent waiting for demand misses. */
865    Stats::Formula demandMissLatency;
866    /** Total number of cycles spent waiting for all misses. */
867    Stats::Formula overallMissLatency;
868
869    /** The number of accesses per command and thread. */
870    Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
871    /** The number of demand accesses. */
872    Stats::Formula demandAccesses;
873    /** The number of overall accesses. */
874    Stats::Formula overallAccesses;
875
876    /** The miss rate per command and thread. */
877    Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
878    /** The miss rate of all demand accesses. */
879    Stats::Formula demandMissRate;
880    /** The miss rate for all accesses. */
881    Stats::Formula overallMissRate;
882
883    /** The average miss latency per command and thread. */
884    Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
885    /** The average miss latency for demand misses. */
886    Stats::Formula demandAvgMissLatency;
887    /** The average miss latency for all misses. */
888    Stats::Formula overallAvgMissLatency;
889
890    /** The total number of cycles blocked for each blocked cause. */
891    Stats::Vector blocked_cycles;
892    /** The number of times this cache blocked for each blocked cause. */
893    Stats::Vector blocked_causes;
894
895    /** The average number of cycles blocked for each blocked cause. */
896    Stats::Formula avg_blocked;
897
898    /** The number of times a HW-prefetched block is evicted w/o reference. */
899    Stats::Scalar unusedPrefetches;
900
901    /** Number of blocks written back per thread. */
902    Stats::Vector writebacks;
903
904    /** Number of misses that hit in the MSHRs per command and thread. */
905    Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
906    /** Demand misses that hit in the MSHRs. */
907    Stats::Formula demandMshrHits;
908    /** Total number of misses that hit in the MSHRs. */
909    Stats::Formula overallMshrHits;
910
911    /** Number of misses that miss in the MSHRs, per command and thread. */
912    Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
913    /** Demand misses that miss in the MSHRs. */
914    Stats::Formula demandMshrMisses;
915    /** Total number of misses that miss in the MSHRs. */
916    Stats::Formula overallMshrMisses;
917
918    /** Number of misses that miss in the MSHRs, per command and thread. */
919    Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
920    /** Total number of misses that miss in the MSHRs. */
921    Stats::Formula overallMshrUncacheable;
922
923    /** Total cycle latency of each MSHR miss, per command and thread. */
924    Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
925    /** Total cycle latency of demand MSHR misses. */
926    Stats::Formula demandMshrMissLatency;
927    /** Total cycle latency of overall MSHR misses. */
928    Stats::Formula overallMshrMissLatency;
929
930    /** Total cycle latency of each MSHR miss, per command and thread. */
931    Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
932    /** Total cycle latency of overall MSHR misses. */
933    Stats::Formula overallMshrUncacheableLatency;
934
935#if 0
936    /** The total number of MSHR accesses per command and thread. */
937    Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
938    /** The total number of demand MSHR accesses. */
939    Stats::Formula demandMshrAccesses;
940    /** The total number of MSHR accesses. */
941    Stats::Formula overallMshrAccesses;
942#endif
943
944    /** The miss rate in the MSHRs pre command and thread. */
945    Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
946    /** The demand miss rate in the MSHRs. */
947    Stats::Formula demandMshrMissRate;
948    /** The overall miss rate in the MSHRs. */
949    Stats::Formula overallMshrMissRate;
950
951    /** The average latency of an MSHR miss, per command and thread. */
952    Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
953    /** The average latency of a demand MSHR miss. */
954    Stats::Formula demandAvgMshrMissLatency;
955    /** The average overall latency of an MSHR miss. */
956    Stats::Formula overallAvgMshrMissLatency;
957
958    /** The average latency of an MSHR miss, per command and thread. */
959    Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
960    /** The average overall latency of an MSHR miss. */
961    Stats::Formula overallAvgMshrUncacheableLatency;
962
963    /** Number of replacements of valid blocks. */
964    Stats::Scalar replacements;
965
966    /**
967     * @}
968     */
969
970    /**
971     * Register stats for this object.
972     */
973    void regStats() override;
974
975  public:
976    BaseCache(const BaseCacheParams *p, unsigned blk_size);
977    ~BaseCache();
978
979    void init() override;
980
981    BaseMasterPort &getMasterPort(const std::string &if_name,
982                                  PortID idx = InvalidPortID) override;
983    BaseSlavePort &getSlavePort(const std::string &if_name,
984                                PortID idx = InvalidPortID) override;
985
986    /**
987     * Query block size of a cache.
988     * @return  The block size
989     */
990    unsigned
991    getBlockSize() const
992    {
993        return blkSize;
994    }
995
996    const AddrRangeList &getAddrRanges() const { return addrRanges; }
997
998    MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
999    {
1000        MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,
1001                                        pkt, time, order++,
1002                                        allocOnFill(pkt->cmd));
1003
1004        if (mshrQueue.isFull()) {
1005            setBlocked((BlockedCause)MSHRQueue_MSHRs);
1006        }
1007
1008        if (sched_send) {
1009            // schedule the send
1010            schedMemSideSendEvent(time);
1011        }
1012
1013        return mshr;
1014    }
1015
1016    void allocateWriteBuffer(PacketPtr pkt, Tick time)
1017    {
1018        // should only see writes or clean evicts here
1019        assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
1020
1021        Addr blk_addr = pkt->getBlockAddr(blkSize);
1022
1023        WriteQueueEntry *wq_entry =
1024            writeBuffer.findMatch(blk_addr, pkt->isSecure());
1025        if (wq_entry && !wq_entry->inService) {
1026            DPRINTF(Cache, "Potential to merge writeback %s", pkt->print());
1027        }
1028
1029        writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++);
1030
1031        if (writeBuffer.isFull()) {
1032            setBlocked((BlockedCause)MSHRQueue_WriteBuffer);
1033        }
1034
1035        // schedule the send
1036        schedMemSideSendEvent(time);
1037    }
1038
1039    /**
1040     * Returns true if the cache is blocked for accesses.
1041     */
1042    bool isBlocked() const
1043    {
1044        return blocked != 0;
1045    }
1046
1047    /**
1048     * Marks the access path of the cache as blocked for the given cause. This
1049     * also sets the blocked flag in the slave interface.
1050     * @param cause The reason for the cache blocking.
1051     */
1052    void setBlocked(BlockedCause cause)
1053    {
1054        uint8_t flag = 1 << cause;
1055        if (blocked == 0) {
1056            blocked_causes[cause]++;
1057            blockedCycle = curCycle();
1058            cpuSidePort.setBlocked();
1059        }
1060        blocked |= flag;
1061        DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
1062    }
1063
1064    /**
1065     * Marks the cache as unblocked for the given cause. This also clears the
1066     * blocked flags in the appropriate interfaces.
1067     * @param cause The newly unblocked cause.
1068     * @warning Calling this function can cause a blocked request on the bus to
1069     * access the cache. The cache must be in a state to handle that request.
1070     */
1071    void clearBlocked(BlockedCause cause)
1072    {
1073        uint8_t flag = 1 << cause;
1074        blocked &= ~flag;
1075        DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
1076        if (blocked == 0) {
1077            blocked_cycles[cause] += curCycle() - blockedCycle;
1078            cpuSidePort.clearBlocked();
1079        }
1080    }
1081
1082    /**
1083     * Schedule a send event for the memory-side port. If already
1084     * scheduled, this may reschedule the event at an earlier
1085     * time. When the specified time is reached, the port is free to
1086     * send either a response, a request, or a prefetch request.
1087     *
1088     * @param time The time when to attempt sending a packet.
1089     */
1090    void schedMemSideSendEvent(Tick time)
1091    {
1092        memSidePort.schedSendEvent(time);
1093    }
1094
1095    bool inCache(Addr addr, bool is_secure) const {
1096        return tags->findBlock(addr, is_secure);
1097    }
1098
1099    bool inMissQueue(Addr addr, bool is_secure) const {
1100        return mshrQueue.findMatch(addr, is_secure);
1101    }
1102
1103    void incMissCount(PacketPtr pkt)
1104    {
1105        assert(pkt->req->masterId() < system->maxMasters());
1106        misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
1107        pkt->req->incAccessDepth();
1108        if (missCount) {
1109            --missCount;
1110            if (missCount == 0)
1111                exitSimLoop("A cache reached the maximum miss count");
1112        }
1113    }
1114    void incHitCount(PacketPtr pkt)
1115    {
1116        assert(pkt->req->masterId() < system->maxMasters());
1117        hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
1118
1119    }
1120
1121    /**
1122     * Cache block visitor that writes back dirty cache blocks using
1123     * functional writes.
1124     */
1125    void writebackVisitor(CacheBlk &blk);
1126
1127    /**
1128     * Cache block visitor that invalidates all blocks in the cache.
1129     *
1130     * @warn Dirty cache lines will not be written back to memory.
1131     */
1132    void invalidateVisitor(CacheBlk &blk);
1133
1134    /**
1135     * Take an MSHR, turn it into a suitable downstream packet, and
1136     * send it out. This construct allows a queue entry to choose a suitable
1137     * approach based on its type.
1138     *
1139     * @param mshr The MSHR to turn into a packet and send
1140     * @return True if the port is waiting for a retry
1141     */
1142    virtual bool sendMSHRQueuePacket(MSHR* mshr);
1143
1144    /**
1145     * Similar to sendMSHR, but for a write-queue entry
1146     * instead. Create the packet, and send it, and if successful also
1147     * mark the entry in service.
1148     *
1149     * @param wq_entry The write-queue entry to turn into a packet and send
1150     * @return True if the port is waiting for a retry
1151     */
1152    bool sendWriteQueuePacket(WriteQueueEntry* wq_entry);
1153
1154    /**
1155     * Serialize the state of the caches
1156     *
1157     * We currently don't support checkpointing cache state, so this panics.
1158     */
1159    void serialize(CheckpointOut &cp) const override;
1160    void unserialize(CheckpointIn &cp) override;
1161
1162};
1163
1164#endif //__MEM_CACHE_BASE_HH__
1165