base.hh revision 12084:5a3769ff3d55
17090SN/A/* 27090SN/A * Copyright (c) 2012-2013, 2015-2016 ARM Limited 37090SN/A * All rights reserved. 47090SN/A * 57090SN/A * The license below extends only to copyright in the software and shall 67090SN/A * not be construed as granting a license to any other intellectual 77090SN/A * property including but not limited to intellectual property relating 87090SN/A * to a hardware implementation of the functionality of the software 97090SN/A * licensed hereunder. You may use the software subject to the license 107090SN/A * terms below provided that you ensure that this notice is replicated 117090SN/A * unmodified and in its entirety in all distributions of the software, 127090SN/A * modified or unmodified, in source code or in binary form. 134486SN/A * 144486SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 154486SN/A * All rights reserved. 164486SN/A * 174486SN/A * Redistribution and use in source and binary forms, with or without 184486SN/A * modification, are permitted provided that the following conditions are 194486SN/A * met: redistributions of source code must retain the above copyright 204486SN/A * notice, this list of conditions and the following disclaimer; 214486SN/A * redistributions in binary form must reproduce the above copyright 224486SN/A * notice, this list of conditions and the following disclaimer in the 234486SN/A * documentation and/or other materials provided with the distribution; 244486SN/A * neither the name of the copyright holders nor the names of its 254486SN/A * contributors may be used to endorse or promote products derived from 264486SN/A * this software without specific prior written permission. 274486SN/A * 284486SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294486SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304486SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314486SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324486SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334486SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344486SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354486SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364486SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374486SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384486SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397584SAli.Saidi@arm.com * 407584SAli.Saidi@arm.com * Authors: Erik Hallnor 417754SWilliam.Wang@arm.com * Steve Reinhardt 424486SN/A * Ron Dreslinski 433630SN/A */ 443630SN/A 457587SAli.Saidi@arm.com/** 468212SAli.Saidi@ARM.com * @file 475478SN/A * Declares a basic cache interface BaseCache. 485478SN/A */ 497584SAli.Saidi@arm.com 503630SN/A#ifndef __MEM_CACHE_BASE_HH__ 517584SAli.Saidi@arm.com#define __MEM_CACHE_BASE_HH__ 527584SAli.Saidi@arm.com 537584SAli.Saidi@arm.com#include <algorithm> 547584SAli.Saidi@arm.com#include <list> 553898SN/A#include <string> 567950SAli.Saidi@ARM.com#include <vector> 577950SAli.Saidi@ARM.com 587950SAli.Saidi@ARM.com#include "base/misc.hh" 597950SAli.Saidi@ARM.com#include "base/statistics.hh" 607950SAli.Saidi@ARM.com#include "base/trace.hh" 617950SAli.Saidi@ARM.com#include "base/types.hh" 627950SAli.Saidi@ARM.com#include "debug/Cache.hh" 637950SAli.Saidi@ARM.com#include "debug/CachePort.hh" 647587SAli.Saidi@arm.com#include "mem/cache/mshr_queue.hh" 657587SAli.Saidi@arm.com#include "mem/cache/write_queue.hh" 667587SAli.Saidi@arm.com#include "mem/mem_object.hh" 677753SWilliam.Wang@arm.com#include "mem/packet.hh" 687753SWilliam.Wang@arm.com#include "mem/qport.hh" 697753SWilliam.Wang@arm.com#include "mem/request.hh" 707753SWilliam.Wang@arm.com#include "params/BaseCache.hh" 717587SAli.Saidi@arm.com#include "sim/eventq.hh" 727587SAli.Saidi@arm.com#include "sim/full_system.hh" 738282SAli.Saidi@ARM.com#include "sim/sim_exit.hh" 748282SAli.Saidi@ARM.com#include "sim/system.hh" 758282SAli.Saidi@ARM.com 767584SAli.Saidi@arm.com/** 777584SAli.Saidi@arm.com * A basic cache interface. Implements some common functions for speed. 788299Schander.sudanthi@arm.com */ 798299Schander.sudanthi@arm.comclass BaseCache : public MemObject 807584SAli.Saidi@arm.com{ 817584SAli.Saidi@arm.com protected: 827584SAli.Saidi@arm.com /** 837584SAli.Saidi@arm.com * Indexes to enumerate the MSHR queues. 847584SAli.Saidi@arm.com */ 857584SAli.Saidi@arm.com enum MSHRQueueIndex { 868283SPrakash.Ramrakhyani@arm.com MSHRQueue_MSHRs, 878283SPrakash.Ramrakhyani@arm.com MSHRQueue_WriteBuffer 887584SAli.Saidi@arm.com }; 897584SAli.Saidi@arm.com 907584SAli.Saidi@arm.com public: 917584SAli.Saidi@arm.com /** 927584SAli.Saidi@arm.com * Reasons for caches to be blocked. 937584SAli.Saidi@arm.com */ 947584SAli.Saidi@arm.com enum BlockedCause { 957584SAli.Saidi@arm.com Blocked_NoMSHRs = MSHRQueue_MSHRs, 967584SAli.Saidi@arm.com Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 977584SAli.Saidi@arm.com Blocked_NoTargets, 987584SAli.Saidi@arm.com NUM_BLOCKED_CAUSES 997584SAli.Saidi@arm.com }; 1007584SAli.Saidi@arm.com 1017584SAli.Saidi@arm.com protected: 1027584SAli.Saidi@arm.com 1037584SAli.Saidi@arm.com /** 1047584SAli.Saidi@arm.com * A cache master port is used for the memory-side port of the 1057584SAli.Saidi@arm.com * cache, and in addition to the basic timing port that only sends 1067584SAli.Saidi@arm.com * response packets through a transmit list, it also offers the 1077584SAli.Saidi@arm.com * ability to schedule and send request packets (requests & 1087584SAli.Saidi@arm.com * writebacks). The send event is scheduled through schedSendEvent, 1097584SAli.Saidi@arm.com * and the sendDeferredPacket of the timing port is modified to 1107584SAli.Saidi@arm.com * consider both the transmit list and the requests from the MSHR. 1117950SAli.Saidi@ARM.com */ 1127754SWilliam.Wang@arm.com class CacheMasterPort : public QueuedMasterPort 1137950SAli.Saidi@ARM.com { 1147950SAli.Saidi@ARM.com 1157950SAli.Saidi@ARM.com public: 1167754SWilliam.Wang@arm.com 1177754SWilliam.Wang@arm.com /** 1187753SWilliam.Wang@arm.com * Schedule a send of a request packet (from the MSHR). Note 1197753SWilliam.Wang@arm.com * that we could already have a retry outstanding. 1207753SWilliam.Wang@arm.com */ 1217950SAli.Saidi@ARM.com void schedSendEvent(Tick time) 1227753SWilliam.Wang@arm.com { 1237753SWilliam.Wang@arm.com DPRINTF(CachePort, "Scheduling send event at %llu\n", time); 1247584SAli.Saidi@arm.com reqQueue.schedSendEvent(time); 1257584SAli.Saidi@arm.com } 1263630SN/A 1273630SN/A protected: 1287753SWilliam.Wang@arm.com 1297753SWilliam.Wang@arm.com CacheMasterPort(const std::string &_name, BaseCache *_cache, 1307753SWilliam.Wang@arm.com ReqPacketQueue &_reqQueue, 1317584SAli.Saidi@arm.com SnoopRespPacketQueue &_snoopRespQueue) : 1327584SAli.Saidi@arm.com QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue) 1337584SAli.Saidi@arm.com { } 1347584SAli.Saidi@arm.com 1357584SAli.Saidi@arm.com /** 1367584SAli.Saidi@arm.com * Memory-side port always snoops. 1377753SWilliam.Wang@arm.com * 1387754SWilliam.Wang@arm.com * @return always true 1397950SAli.Saidi@ARM.com */ 1408282SAli.Saidi@ARM.com virtual bool isSnooping() const { return true; } 1418212SAli.Saidi@ARM.com }; 1428212SAli.Saidi@ARM.com 1438212SAli.Saidi@ARM.com /** 1448212SAli.Saidi@ARM.com * A cache slave port is used for the CPU-side port of the cache, 1458212SAli.Saidi@ARM.com * and it is basically a simple timing port that uses a transmit 1468212SAli.Saidi@ARM.com * list for responses to the CPU (or connected master). In 1477584SAli.Saidi@arm.com * addition, it has the functionality to block the port for 1487731SAli.Saidi@ARM.com * incoming requests. If blocked, the port will issue a retry once 1498461SAli.Saidi@ARM.com * unblocked. 1508461SAli.Saidi@ARM.com */ 1517696SAli.Saidi@ARM.com class CacheSlavePort : public QueuedSlavePort 1527696SAli.Saidi@ARM.com { 1537696SAli.Saidi@ARM.com 1547696SAli.Saidi@ARM.com public: 1557696SAli.Saidi@ARM.com 1567696SAli.Saidi@ARM.com /** Do not accept any new requests. */ 1577696SAli.Saidi@ARM.com void setBlocked(); 1587696SAli.Saidi@ARM.com 1597696SAli.Saidi@ARM.com /** Return to normal operation and accept new requests. */ 1607696SAli.Saidi@ARM.com void clearBlocked(); 1617696SAli.Saidi@ARM.com 1627696SAli.Saidi@ARM.com bool isBlocked() const { return blocked; } 1637696SAli.Saidi@ARM.com 1647696SAli.Saidi@ARM.com protected: 1657696SAli.Saidi@ARM.com 1667696SAli.Saidi@ARM.com CacheSlavePort(const std::string &_name, BaseCache *_cache, 1677696SAli.Saidi@ARM.com const std::string &_label); 1687696SAli.Saidi@ARM.com 1697696SAli.Saidi@ARM.com /** A normal packet queue used to store responses. */ 1707696SAli.Saidi@ARM.com RespPacketQueue queue; 1717696SAli.Saidi@ARM.com 1728282SAli.Saidi@ARM.com bool blocked; 1737696SAli.Saidi@ARM.com 1747696SAli.Saidi@ARM.com bool mustSendRetry; 1757696SAli.Saidi@ARM.com 1767696SAli.Saidi@ARM.com private: 1777696SAli.Saidi@ARM.com 1787696SAli.Saidi@ARM.com void processSendRetry(); 1797696SAli.Saidi@ARM.com 1807696SAli.Saidi@ARM.com EventFunctionWrapper sendRetryEvent; 1817696SAli.Saidi@ARM.com 1827753SWilliam.Wang@arm.com }; 1837754SWilliam.Wang@arm.com 1847754SWilliam.Wang@arm.com CacheSlavePort *cpuSidePort; 1858212SAli.Saidi@ARM.com CacheMasterPort *memSidePort; 1867696SAli.Saidi@ARM.com 1877696SAli.Saidi@ARM.com protected: 1887696SAli.Saidi@ARM.com 1897696SAli.Saidi@ARM.com /** Miss status registers */ 1907696SAli.Saidi@ARM.com MSHRQueue mshrQueue; 1917696SAli.Saidi@ARM.com 1927696SAli.Saidi@ARM.com /** Write/writeback buffer */ 1937696SAli.Saidi@ARM.com WriteQueue writeBuffer; 1947696SAli.Saidi@ARM.com 1957696SAli.Saidi@ARM.com /** 1967696SAli.Saidi@ARM.com * Mark a request as in service (sent downstream in the memory 1977696SAli.Saidi@ARM.com * system), effectively making this MSHR the ordering point. 1987696SAli.Saidi@ARM.com */ 1997696SAli.Saidi@ARM.com void markInService(MSHR *mshr, bool pending_modified_resp) 2007696SAli.Saidi@ARM.com { 2017696SAli.Saidi@ARM.com bool wasFull = mshrQueue.isFull(); 2027696SAli.Saidi@ARM.com mshrQueue.markInService(mshr, pending_modified_resp); 2037754SWilliam.Wang@arm.com 2047754SWilliam.Wang@arm.com if (wasFull && !mshrQueue.isFull()) { 2057754SWilliam.Wang@arm.com clearBlocked(Blocked_NoMSHRs); 2067696SAli.Saidi@ARM.com } 2077696SAli.Saidi@ARM.com } 2087696SAli.Saidi@ARM.com 2097696SAli.Saidi@ARM.com void markInService(WriteQueueEntry *entry) 2107696SAli.Saidi@ARM.com { 2117696SAli.Saidi@ARM.com bool wasFull = writeBuffer.isFull(); 2127754SWilliam.Wang@arm.com writeBuffer.markInService(entry); 2137754SWilliam.Wang@arm.com 2147950SAli.Saidi@ARM.com if (wasFull && !writeBuffer.isFull()) { 2157696SAli.Saidi@ARM.com clearBlocked(Blocked_NoWBBuffers); 2167696SAli.Saidi@ARM.com } 2178461SAli.Saidi@ARM.com } 2188461SAli.Saidi@ARM.com 2197584SAli.Saidi@arm.com /** 2207584SAli.Saidi@arm.com * Determine if we should allocate on a fill or not. 2217584SAli.Saidi@arm.com * 2227584SAli.Saidi@arm.com * @param cmd Packet command being added as an MSHR target 2238299Schander.sudanthi@arm.com * 2247584SAli.Saidi@arm.com * @return Whether we should allocate on a fill or not 2257584SAli.Saidi@arm.com */ 2267584SAli.Saidi@arm.com virtual bool allocOnFill(MemCmd cmd) const = 0; 2277584SAli.Saidi@arm.com 2287584SAli.Saidi@arm.com /** 2297584SAli.Saidi@arm.com * Write back dirty blocks in the cache using functional accesses. 2307584SAli.Saidi@arm.com */ 2317584SAli.Saidi@arm.com virtual void memWriteback() = 0; 2327584SAli.Saidi@arm.com /** 2337584SAli.Saidi@arm.com * Invalidates all blocks in the cache. 2347584SAli.Saidi@arm.com * 2357584SAli.Saidi@arm.com * @warn Dirty cache lines will not be written back to 2367584SAli.Saidi@arm.com * memory. Make sure to call functionalWriteback() first if you 2377584SAli.Saidi@arm.com * want the to write them to memory. 2384104SN/A */ 2394104SN/A virtual void memInvalidate() = 0; 2407584SAli.Saidi@arm.com /** 2417584SAli.Saidi@arm.com * Determine if there are any dirty blocks in the cache. 2424104SN/A * 2433630SN/A * \return true if at least one block is dirty, false otherwise. 2443630SN/A */ 2453630SN/A virtual bool isDirty() const = 0; 2463630SN/A 2477584SAli.Saidi@arm.com /** 2487584SAli.Saidi@arm.com * Determine if an address is in the ranges covered by this 2497584SAli.Saidi@arm.com * cache. This is useful to filter snoops. 2507584SAli.Saidi@arm.com * 2517753SWilliam.Wang@arm.com * @param addr Address to check against 2527754SWilliam.Wang@arm.com * 2537754SWilliam.Wang@arm.com * @return If the address in question is in range 2547584SAli.Saidi@arm.com */ 2557584SAli.Saidi@arm.com bool inRange(Addr addr) const; 2567584SAli.Saidi@arm.com 2577584SAli.Saidi@arm.com /** Block size of this cache */ 2587584SAli.Saidi@arm.com const unsigned blkSize; 2597584SAli.Saidi@arm.com 2607584SAli.Saidi@arm.com /** 2617584SAli.Saidi@arm.com * The latency of tag lookup of a cache. It occurs when there is 2627584SAli.Saidi@arm.com * an access to the cache. 2637584SAli.Saidi@arm.com */ 2647584SAli.Saidi@arm.com const Cycles lookupLatency; 2657584SAli.Saidi@arm.com 2667584SAli.Saidi@arm.com /** 2677584SAli.Saidi@arm.com * The latency of data access of a cache. It occurs when there is 2687584SAli.Saidi@arm.com * an access to the cache. 2698299Schander.sudanthi@arm.com */ 2708299Schander.sudanthi@arm.com const Cycles dataLatency; 2717584SAli.Saidi@arm.com 272 /** 273 * This is the forward latency of the cache. It occurs when there 274 * is a cache miss and a request is forwarded downstream, in 275 * particular an outbound miss. 276 */ 277 const Cycles forwardLatency; 278 279 /** The latency to fill a cache block */ 280 const Cycles fillLatency; 281 282 /** 283 * The latency of sending reponse to its upper level cache/core on 284 * a linefill. The responseLatency parameter captures this 285 * latency. 286 */ 287 const Cycles responseLatency; 288 289 /** The number of targets for each MSHR. */ 290 const int numTarget; 291 292 /** Do we forward snoops from mem side port through to cpu side port? */ 293 bool forwardSnoops; 294 295 /** 296 * Is this cache read only, for example the instruction cache, or 297 * table-walker cache. A cache that is read only should never see 298 * any writes, and should never get any dirty data (and hence 299 * never have to do any writebacks). 300 */ 301 const bool isReadOnly; 302 303 /** 304 * Bit vector of the blocking reasons for the access path. 305 * @sa #BlockedCause 306 */ 307 uint8_t blocked; 308 309 /** Increasing order number assigned to each incoming request. */ 310 uint64_t order; 311 312 /** Stores time the cache blocked for statistics. */ 313 Cycles blockedCycle; 314 315 /** Pointer to the MSHR that has no targets. */ 316 MSHR *noTargetMSHR; 317 318 /** The number of misses to trigger an exit event. */ 319 Counter missCount; 320 321 /** 322 * The address range to which the cache responds on the CPU side. 323 * Normally this is all possible memory addresses. */ 324 const AddrRangeList addrRanges; 325 326 public: 327 /** System we are currently operating in. */ 328 System *system; 329 330 // Statistics 331 /** 332 * @addtogroup CacheStatistics 333 * @{ 334 */ 335 336 /** Number of hits per thread for each type of command. 337 @sa Packet::Command */ 338 Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 339 /** Number of hits for demand accesses. */ 340 Stats::Formula demandHits; 341 /** Number of hit for all accesses. */ 342 Stats::Formula overallHits; 343 344 /** Number of misses per thread for each type of command. 345 @sa Packet::Command */ 346 Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 347 /** Number of misses for demand accesses. */ 348 Stats::Formula demandMisses; 349 /** Number of misses for all accesses. */ 350 Stats::Formula overallMisses; 351 352 /** 353 * Total number of cycles per thread/command spent waiting for a miss. 354 * Used to calculate the average miss latency. 355 */ 356 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 357 /** Total number of cycles spent waiting for demand misses. */ 358 Stats::Formula demandMissLatency; 359 /** Total number of cycles spent waiting for all misses. */ 360 Stats::Formula overallMissLatency; 361 362 /** The number of accesses per command and thread. */ 363 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 364 /** The number of demand accesses. */ 365 Stats::Formula demandAccesses; 366 /** The number of overall accesses. */ 367 Stats::Formula overallAccesses; 368 369 /** The miss rate per command and thread. */ 370 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 371 /** The miss rate of all demand accesses. */ 372 Stats::Formula demandMissRate; 373 /** The miss rate for all accesses. */ 374 Stats::Formula overallMissRate; 375 376 /** The average miss latency per command and thread. */ 377 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 378 /** The average miss latency for demand misses. */ 379 Stats::Formula demandAvgMissLatency; 380 /** The average miss latency for all misses. */ 381 Stats::Formula overallAvgMissLatency; 382 383 /** The total number of cycles blocked for each blocked cause. */ 384 Stats::Vector blocked_cycles; 385 /** The number of times this cache blocked for each blocked cause. */ 386 Stats::Vector blocked_causes; 387 388 /** The average number of cycles blocked for each blocked cause. */ 389 Stats::Formula avg_blocked; 390 391 /** The number of times a HW-prefetched block is evicted w/o reference. */ 392 Stats::Scalar unusedPrefetches; 393 394 /** Number of blocks written back per thread. */ 395 Stats::Vector writebacks; 396 397 /** Number of misses that hit in the MSHRs per command and thread. */ 398 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 399 /** Demand misses that hit in the MSHRs. */ 400 Stats::Formula demandMshrHits; 401 /** Total number of misses that hit in the MSHRs. */ 402 Stats::Formula overallMshrHits; 403 404 /** Number of misses that miss in the MSHRs, per command and thread. */ 405 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 406 /** Demand misses that miss in the MSHRs. */ 407 Stats::Formula demandMshrMisses; 408 /** Total number of misses that miss in the MSHRs. */ 409 Stats::Formula overallMshrMisses; 410 411 /** Number of misses that miss in the MSHRs, per command and thread. */ 412 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 413 /** Total number of misses that miss in the MSHRs. */ 414 Stats::Formula overallMshrUncacheable; 415 416 /** Total cycle latency of each MSHR miss, per command and thread. */ 417 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 418 /** Total cycle latency of demand MSHR misses. */ 419 Stats::Formula demandMshrMissLatency; 420 /** Total cycle latency of overall MSHR misses. */ 421 Stats::Formula overallMshrMissLatency; 422 423 /** Total cycle latency of each MSHR miss, per command and thread. */ 424 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 425 /** Total cycle latency of overall MSHR misses. */ 426 Stats::Formula overallMshrUncacheableLatency; 427 428#if 0 429 /** The total number of MSHR accesses per command and thread. */ 430 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 431 /** The total number of demand MSHR accesses. */ 432 Stats::Formula demandMshrAccesses; 433 /** The total number of MSHR accesses. */ 434 Stats::Formula overallMshrAccesses; 435#endif 436 437 /** The miss rate in the MSHRs pre command and thread. */ 438 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 439 /** The demand miss rate in the MSHRs. */ 440 Stats::Formula demandMshrMissRate; 441 /** The overall miss rate in the MSHRs. */ 442 Stats::Formula overallMshrMissRate; 443 444 /** The average latency of an MSHR miss, per command and thread. */ 445 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 446 /** The average latency of a demand MSHR miss. */ 447 Stats::Formula demandAvgMshrMissLatency; 448 /** The average overall latency of an MSHR miss. */ 449 Stats::Formula overallAvgMshrMissLatency; 450 451 /** The average latency of an MSHR miss, per command and thread. */ 452 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 453 /** The average overall latency of an MSHR miss. */ 454 Stats::Formula overallAvgMshrUncacheableLatency; 455 456 /** 457 * @} 458 */ 459 460 /** 461 * Register stats for this object. 462 */ 463 virtual void regStats(); 464 465 public: 466 BaseCache(const BaseCacheParams *p, unsigned blk_size); 467 ~BaseCache() {} 468 469 virtual void init(); 470 471 virtual BaseMasterPort &getMasterPort(const std::string &if_name, 472 PortID idx = InvalidPortID); 473 virtual BaseSlavePort &getSlavePort(const std::string &if_name, 474 PortID idx = InvalidPortID); 475 476 /** 477 * Query block size of a cache. 478 * @return The block size 479 */ 480 unsigned 481 getBlockSize() const 482 { 483 return blkSize; 484 } 485 486 const AddrRangeList &getAddrRanges() const { return addrRanges; } 487 488 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true) 489 { 490 MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize, 491 pkt, time, order++, 492 allocOnFill(pkt->cmd)); 493 494 if (mshrQueue.isFull()) { 495 setBlocked((BlockedCause)MSHRQueue_MSHRs); 496 } 497 498 if (sched_send) { 499 // schedule the send 500 schedMemSideSendEvent(time); 501 } 502 503 return mshr; 504 } 505 506 void allocateWriteBuffer(PacketPtr pkt, Tick time) 507 { 508 // should only see writes or clean evicts here 509 assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict); 510 511 Addr blk_addr = pkt->getBlockAddr(blkSize); 512 513 WriteQueueEntry *wq_entry = 514 writeBuffer.findMatch(blk_addr, pkt->isSecure()); 515 if (wq_entry && !wq_entry->inService) { 516 DPRINTF(Cache, "Potential to merge writeback %s", pkt->print()); 517 } 518 519 writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++); 520 521 if (writeBuffer.isFull()) { 522 setBlocked((BlockedCause)MSHRQueue_WriteBuffer); 523 } 524 525 // schedule the send 526 schedMemSideSendEvent(time); 527 } 528 529 /** 530 * Returns true if the cache is blocked for accesses. 531 */ 532 bool isBlocked() const 533 { 534 return blocked != 0; 535 } 536 537 /** 538 * Marks the access path of the cache as blocked for the given cause. This 539 * also sets the blocked flag in the slave interface. 540 * @param cause The reason for the cache blocking. 541 */ 542 void setBlocked(BlockedCause cause) 543 { 544 uint8_t flag = 1 << cause; 545 if (blocked == 0) { 546 blocked_causes[cause]++; 547 blockedCycle = curCycle(); 548 cpuSidePort->setBlocked(); 549 } 550 blocked |= flag; 551 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 552 } 553 554 /** 555 * Marks the cache as unblocked for the given cause. This also clears the 556 * blocked flags in the appropriate interfaces. 557 * @param cause The newly unblocked cause. 558 * @warning Calling this function can cause a blocked request on the bus to 559 * access the cache. The cache must be in a state to handle that request. 560 */ 561 void clearBlocked(BlockedCause cause) 562 { 563 uint8_t flag = 1 << cause; 564 blocked &= ~flag; 565 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 566 if (blocked == 0) { 567 blocked_cycles[cause] += curCycle() - blockedCycle; 568 cpuSidePort->clearBlocked(); 569 } 570 } 571 572 /** 573 * Schedule a send event for the memory-side port. If already 574 * scheduled, this may reschedule the event at an earlier 575 * time. When the specified time is reached, the port is free to 576 * send either a response, a request, or a prefetch request. 577 * 578 * @param time The time when to attempt sending a packet. 579 */ 580 void schedMemSideSendEvent(Tick time) 581 { 582 memSidePort->schedSendEvent(time); 583 } 584 585 virtual bool inCache(Addr addr, bool is_secure) const = 0; 586 587 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0; 588 589 void incMissCount(PacketPtr pkt) 590 { 591 assert(pkt->req->masterId() < system->maxMasters()); 592 misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 593 pkt->req->incAccessDepth(); 594 if (missCount) { 595 --missCount; 596 if (missCount == 0) 597 exitSimLoop("A cache reached the maximum miss count"); 598 } 599 } 600 void incHitCount(PacketPtr pkt) 601 { 602 assert(pkt->req->masterId() < system->maxMasters()); 603 hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 604 605 } 606 607}; 608 609#endif //__MEM_CACHE_BASE_HH__ 610