base.hh revision 10693
1/* 2 * Copyright (c) 2012-2013, 2015 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Steve Reinhardt 42 * Ron Dreslinski 43 */ 44 45/** 46 * @file 47 * Declares a basic cache interface BaseCache. 48 */ 49 50#ifndef __BASE_CACHE_HH__ 51#define __BASE_CACHE_HH__ 52 53#include <algorithm> 54#include <list> 55#include <string> 56#include <vector> 57 58#include "base/misc.hh" 59#include "base/statistics.hh" 60#include "base/trace.hh" 61#include "base/types.hh" 62#include "debug/Cache.hh" 63#include "debug/CachePort.hh" 64#include "mem/cache/mshr_queue.hh" 65#include "mem/mem_object.hh" 66#include "mem/packet.hh" 67#include "mem/qport.hh" 68#include "mem/request.hh" 69#include "params/BaseCache.hh" 70#include "sim/eventq.hh" 71#include "sim/full_system.hh" 72#include "sim/sim_exit.hh" 73#include "sim/system.hh" 74 75class MSHR; 76/** 77 * A basic cache interface. Implements some common functions for speed. 78 */ 79class BaseCache : public MemObject 80{ 81 /** 82 * Indexes to enumerate the MSHR queues. 83 */ 84 enum MSHRQueueIndex { 85 MSHRQueue_MSHRs, 86 MSHRQueue_WriteBuffer 87 }; 88 89 public: 90 /** 91 * Reasons for caches to be blocked. 92 */ 93 enum BlockedCause { 94 Blocked_NoMSHRs = MSHRQueue_MSHRs, 95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 96 Blocked_NoTargets, 97 NUM_BLOCKED_CAUSES 98 }; 99 100 /** 101 * Reasons for cache to request a bus. 102 */ 103 enum RequestCause { 104 Request_MSHR = MSHRQueue_MSHRs, 105 Request_WB = MSHRQueue_WriteBuffer, 106 Request_PF, 107 NUM_REQUEST_CAUSES 108 }; 109 110 protected: 111 112 /** 113 * A cache master port is used for the memory-side port of the 114 * cache, and in addition to the basic timing port that only sends 115 * response packets through a transmit list, it also offers the 116 * ability to schedule and send request packets (requests & 117 * writebacks). The send event is scheduled through requestBus, 118 * and the sendDeferredPacket of the timing port is modified to 119 * consider both the transmit list and the requests from the MSHR. 120 */ 121 class CacheMasterPort : public QueuedMasterPort 122 { 123 124 public: 125 126 /** 127 * Schedule a send of a request packet (from the MSHR). Note 128 * that we could already have a retry or a transmit list of 129 * responses outstanding. 130 */ 131 void requestBus(RequestCause cause, Tick time) 132 { 133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 134 queue.schedSendEvent(time); 135 } 136 137 protected: 138 139 CacheMasterPort(const std::string &_name, BaseCache *_cache, 140 MasterPacketQueue &_queue) : 141 QueuedMasterPort(_name, _cache, _queue) 142 { } 143 144 /** 145 * Memory-side port always snoops. 146 * 147 * @return always true 148 */ 149 virtual bool isSnooping() const { return true; } 150 }; 151 152 /** 153 * A cache slave port is used for the CPU-side port of the cache, 154 * and it is basically a simple timing port that uses a transmit 155 * list for responses to the CPU (or connected master). In 156 * addition, it has the functionality to block the port for 157 * incoming requests. If blocked, the port will issue a retry once 158 * unblocked. 159 */ 160 class CacheSlavePort : public QueuedSlavePort 161 { 162 163 public: 164 165 /** Do not accept any new requests. */ 166 void setBlocked(); 167 168 /** Return to normal operation and accept new requests. */ 169 void clearBlocked(); 170 171 bool isBlocked() const { return blocked; } 172 173 protected: 174 175 CacheSlavePort(const std::string &_name, BaseCache *_cache, 176 const std::string &_label); 177 178 /** A normal packet queue used to store responses. */ 179 SlavePacketQueue queue; 180 181 bool blocked; 182 183 bool mustSendRetry; 184 185 private: 186 187 void processSendRetry(); 188 189 EventWrapper<CacheSlavePort, 190 &CacheSlavePort::processSendRetry> sendRetryEvent; 191 192 }; 193 194 CacheSlavePort *cpuSidePort; 195 CacheMasterPort *memSidePort; 196 197 protected: 198 199 /** Miss status registers */ 200 MSHRQueue mshrQueue; 201 202 /** Write/writeback buffer */ 203 MSHRQueue writeBuffer; 204 205 /** 206 * Allocate a buffer, passing the time indicating when schedule an 207 * event to the queued port to go and ask the MSHR and write queue 208 * if they have packets to send. 209 * 210 * allocateBufferInternal() function is called in: 211 * - MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer); 212 * - MSHR allocateMissBuffer (cacheable miss in MSHR queue); 213 * - MSHR allocateUncachedReadBuffer (unchached read allocated in MSHR 214 * queue) 215 */ 216 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 217 PacketPtr pkt, Tick time, bool requestBus) 218 { 219 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 220 221 if (mq->isFull()) { 222 setBlocked((BlockedCause)mq->index); 223 } 224 225 if (requestBus) { 226 requestMemSideBus((RequestCause)mq->index, time); 227 } 228 229 return mshr; 230 } 231 232 void markInServiceInternal(MSHR *mshr, bool pending_dirty_resp) 233 { 234 MSHRQueue *mq = mshr->queue; 235 bool wasFull = mq->isFull(); 236 mq->markInService(mshr, pending_dirty_resp); 237 if (wasFull && !mq->isFull()) { 238 clearBlocked((BlockedCause)mq->index); 239 } 240 } 241 242 /** 243 * Write back dirty blocks in the cache using functional accesses. 244 */ 245 virtual void memWriteback() = 0; 246 /** 247 * Invalidates all blocks in the cache. 248 * 249 * @warn Dirty cache lines will not be written back to 250 * memory. Make sure to call functionalWriteback() first if you 251 * want the to write them to memory. 252 */ 253 virtual void memInvalidate() = 0; 254 /** 255 * Determine if there are any dirty blocks in the cache. 256 * 257 * \return true if at least one block is dirty, false otherwise. 258 */ 259 virtual bool isDirty() const = 0; 260 261 /** Block size of this cache */ 262 const unsigned blkSize; 263 264 /** 265 * The latency of tag lookup of a cache. It occurs when there is 266 * an access to the cache. 267 */ 268 const Cycles lookupLatency; 269 270 /** 271 * This is the forward latency of the cache. It occurs when there 272 * is a cache miss and a request is forwarded downstream, in 273 * particular an outbound miss. 274 */ 275 const Cycles forwardLatency; 276 277 /** The latency to fill a cache block */ 278 const Cycles fillLatency; 279 280 /** 281 * The latency of sending reponse to its upper level cache/core on 282 * a linefill. The responseLatency parameter captures this 283 * latency. 284 */ 285 const Cycles responseLatency; 286 287 /** The number of targets for each MSHR. */ 288 const int numTarget; 289 290 /** Do we forward snoops from mem side port through to cpu side port? */ 291 const bool forwardSnoops; 292 293 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should 294 * never try to forward ownership and similar optimizations to the cpu 295 * side */ 296 const bool isTopLevel; 297 298 /** 299 * Bit vector of the blocking reasons for the access path. 300 * @sa #BlockedCause 301 */ 302 uint8_t blocked; 303 304 /** Increasing order number assigned to each incoming request. */ 305 uint64_t order; 306 307 /** Stores time the cache blocked for statistics. */ 308 Cycles blockedCycle; 309 310 /** Pointer to the MSHR that has no targets. */ 311 MSHR *noTargetMSHR; 312 313 /** The number of misses to trigger an exit event. */ 314 Counter missCount; 315 316 /** 317 * The address range to which the cache responds on the CPU side. 318 * Normally this is all possible memory addresses. */ 319 const AddrRangeList addrRanges; 320 321 public: 322 /** System we are currently operating in. */ 323 System *system; 324 325 // Statistics 326 /** 327 * @addtogroup CacheStatistics 328 * @{ 329 */ 330 331 /** Number of hits per thread for each type of command. @sa Packet::Command */ 332 Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 333 /** Number of hits for demand accesses. */ 334 Stats::Formula demandHits; 335 /** Number of hit for all accesses. */ 336 Stats::Formula overallHits; 337 338 /** Number of misses per thread for each type of command. @sa Packet::Command */ 339 Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 340 /** Number of misses for demand accesses. */ 341 Stats::Formula demandMisses; 342 /** Number of misses for all accesses. */ 343 Stats::Formula overallMisses; 344 345 /** 346 * Total number of cycles per thread/command spent waiting for a miss. 347 * Used to calculate the average miss latency. 348 */ 349 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 350 /** Total number of cycles spent waiting for demand misses. */ 351 Stats::Formula demandMissLatency; 352 /** Total number of cycles spent waiting for all misses. */ 353 Stats::Formula overallMissLatency; 354 355 /** The number of accesses per command and thread. */ 356 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 357 /** The number of demand accesses. */ 358 Stats::Formula demandAccesses; 359 /** The number of overall accesses. */ 360 Stats::Formula overallAccesses; 361 362 /** The miss rate per command and thread. */ 363 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 364 /** The miss rate of all demand accesses. */ 365 Stats::Formula demandMissRate; 366 /** The miss rate for all accesses. */ 367 Stats::Formula overallMissRate; 368 369 /** The average miss latency per command and thread. */ 370 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 371 /** The average miss latency for demand misses. */ 372 Stats::Formula demandAvgMissLatency; 373 /** The average miss latency for all misses. */ 374 Stats::Formula overallAvgMissLatency; 375 376 /** The total number of cycles blocked for each blocked cause. */ 377 Stats::Vector blocked_cycles; 378 /** The number of times this cache blocked for each blocked cause. */ 379 Stats::Vector blocked_causes; 380 381 /** The average number of cycles blocked for each blocked cause. */ 382 Stats::Formula avg_blocked; 383 384 /** The number of fast writes (WH64) performed. */ 385 Stats::Scalar fastWrites; 386 387 /** The number of cache copies performed. */ 388 Stats::Scalar cacheCopies; 389 390 /** Number of blocks written back per thread. */ 391 Stats::Vector writebacks; 392 393 /** Number of misses that hit in the MSHRs per command and thread. */ 394 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 395 /** Demand misses that hit in the MSHRs. */ 396 Stats::Formula demandMshrHits; 397 /** Total number of misses that hit in the MSHRs. */ 398 Stats::Formula overallMshrHits; 399 400 /** Number of misses that miss in the MSHRs, per command and thread. */ 401 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 402 /** Demand misses that miss in the MSHRs. */ 403 Stats::Formula demandMshrMisses; 404 /** Total number of misses that miss in the MSHRs. */ 405 Stats::Formula overallMshrMisses; 406 407 /** Number of misses that miss in the MSHRs, per command and thread. */ 408 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 409 /** Total number of misses that miss in the MSHRs. */ 410 Stats::Formula overallMshrUncacheable; 411 412 /** Total cycle latency of each MSHR miss, per command and thread. */ 413 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 414 /** Total cycle latency of demand MSHR misses. */ 415 Stats::Formula demandMshrMissLatency; 416 /** Total cycle latency of overall MSHR misses. */ 417 Stats::Formula overallMshrMissLatency; 418 419 /** Total cycle latency of each MSHR miss, per command and thread. */ 420 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 421 /** Total cycle latency of overall MSHR misses. */ 422 Stats::Formula overallMshrUncacheableLatency; 423 424#if 0 425 /** The total number of MSHR accesses per command and thread. */ 426 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 427 /** The total number of demand MSHR accesses. */ 428 Stats::Formula demandMshrAccesses; 429 /** The total number of MSHR accesses. */ 430 Stats::Formula overallMshrAccesses; 431#endif 432 433 /** The miss rate in the MSHRs pre command and thread. */ 434 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 435 /** The demand miss rate in the MSHRs. */ 436 Stats::Formula demandMshrMissRate; 437 /** The overall miss rate in the MSHRs. */ 438 Stats::Formula overallMshrMissRate; 439 440 /** The average latency of an MSHR miss, per command and thread. */ 441 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 442 /** The average latency of a demand MSHR miss. */ 443 Stats::Formula demandAvgMshrMissLatency; 444 /** The average overall latency of an MSHR miss. */ 445 Stats::Formula overallAvgMshrMissLatency; 446 447 /** The average latency of an MSHR miss, per command and thread. */ 448 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 449 /** The average overall latency of an MSHR miss. */ 450 Stats::Formula overallAvgMshrUncacheableLatency; 451 452 /** The number of times a thread hit its MSHR cap. */ 453 Stats::Vector mshr_cap_events; 454 /** The number of times software prefetches caused the MSHR to block. */ 455 Stats::Vector soft_prefetch_mshr_full; 456 457 Stats::Scalar mshr_no_allocate_misses; 458 459 /** 460 * @} 461 */ 462 463 /** 464 * Register stats for this object. 465 */ 466 virtual void regStats(); 467 468 public: 469 typedef BaseCacheParams Params; 470 BaseCache(const Params *p); 471 ~BaseCache() {} 472 473 virtual void init(); 474 475 virtual BaseMasterPort &getMasterPort(const std::string &if_name, 476 PortID idx = InvalidPortID); 477 virtual BaseSlavePort &getSlavePort(const std::string &if_name, 478 PortID idx = InvalidPortID); 479 480 /** 481 * Query block size of a cache. 482 * @return The block size 483 */ 484 unsigned 485 getBlockSize() const 486 { 487 return blkSize; 488 } 489 490 491 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 492 493 494 const AddrRangeList &getAddrRanges() const { return addrRanges; } 495 496 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 497 { 498 assert(!pkt->req->isUncacheable()); 499 return allocateBufferInternal(&mshrQueue, 500 blockAlign(pkt->getAddr()), blkSize, 501 pkt, time, requestBus); 502 } 503 504 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 505 { 506 assert(pkt->isWrite() && !pkt->isRead()); 507 return allocateBufferInternal(&writeBuffer, 508 pkt->getAddr(), pkt->getSize(), 509 pkt, time, requestBus); 510 } 511 512 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus) 513 { 514 assert(pkt->req->isUncacheable()); 515 assert(pkt->isRead()); 516 return allocateBufferInternal(&mshrQueue, 517 pkt->getAddr(), pkt->getSize(), 518 pkt, time, requestBus); 519 } 520 521 /** 522 * Returns true if the cache is blocked for accesses. 523 */ 524 bool isBlocked() const 525 { 526 return blocked != 0; 527 } 528 529 /** 530 * Marks the access path of the cache as blocked for the given cause. This 531 * also sets the blocked flag in the slave interface. 532 * @param cause The reason for the cache blocking. 533 */ 534 void setBlocked(BlockedCause cause) 535 { 536 uint8_t flag = 1 << cause; 537 if (blocked == 0) { 538 blocked_causes[cause]++; 539 blockedCycle = curCycle(); 540 cpuSidePort->setBlocked(); 541 } 542 blocked |= flag; 543 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 544 } 545 546 /** 547 * Marks the cache as unblocked for the given cause. This also clears the 548 * blocked flags in the appropriate interfaces. 549 * @param cause The newly unblocked cause. 550 * @warning Calling this function can cause a blocked request on the bus to 551 * access the cache. The cache must be in a state to handle that request. 552 */ 553 void clearBlocked(BlockedCause cause) 554 { 555 uint8_t flag = 1 << cause; 556 blocked &= ~flag; 557 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 558 if (blocked == 0) { 559 blocked_cycles[cause] += curCycle() - blockedCycle; 560 cpuSidePort->clearBlocked(); 561 } 562 } 563 564 /** 565 * Request the master bus for the given cause and time. 566 * @param cause The reason for the request. 567 * @param time The time to make the request. 568 */ 569 void requestMemSideBus(RequestCause cause, Tick time) 570 { 571 memSidePort->requestBus(cause, time); 572 } 573 574 /** 575 * Clear the master bus request for the given cause. 576 * @param cause The request reason to clear. 577 */ 578 void deassertMemSideBusRequest(RequestCause cause) 579 { 580 // Obsolete... we no longer signal bus requests explicitly so 581 // we can't deassert them. Leaving this in as a no-op since 582 // the prefetcher calls it to indicate that it no longer wants 583 // to request a prefetch, and someday that might be 584 // interesting again. 585 } 586 587 virtual unsigned int drain(DrainManager *dm); 588 589 virtual bool inCache(Addr addr, bool is_secure) const = 0; 590 591 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0; 592 593 void incMissCount(PacketPtr pkt) 594 { 595 assert(pkt->req->masterId() < system->maxMasters()); 596 misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 597 pkt->req->incAccessDepth(); 598 if (missCount) { 599 --missCount; 600 if (missCount == 0) 601 exitSimLoop("A cache reached the maximum miss count"); 602 } 603 } 604 void incHitCount(PacketPtr pkt) 605 { 606 assert(pkt->req->masterId() < system->maxMasters()); 607 hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 608 609 } 610 611}; 612 613#endif //__BASE_CACHE_HH__ 614