base.hh revision 9446
12SN/A/* 21762SN/A * Copyright (c) 2012 ARM Limited 32SN/A * All rights reserved. 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312665Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363506Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373506Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392973Sgblack@eecs.umich.edu * 403584Ssaidi@eecs.umich.edu * Authors: Erik Hallnor 4156SN/A * Steve Reinhardt 423614Sgblack@eecs.umich.edu * Ron Dreslinski 431717SN/A */ 442518SN/A 4556SN/A/** 462518SN/A * @file 472518SN/A * Declares a basic cache interface BaseCache. 482SN/A */ 493614Sgblack@eecs.umich.edu 503614Sgblack@eecs.umich.edu#ifndef __BASE_CACHE_HH__ 513614Sgblack@eecs.umich.edu#define __BASE_CACHE_HH__ 523614Sgblack@eecs.umich.edu 533065Sgblack@eecs.umich.edu#include <algorithm> 543065Sgblack@eecs.umich.edu#include <list> 553506Ssaidi@eecs.umich.edu#include <string> 563065Sgblack@eecs.umich.edu#include <vector> 572SN/A 582973Sgblack@eecs.umich.edu#include "base/misc.hh" 592SN/A#include "base/statistics.hh" 603840Shsul@eecs.umich.edu#include "base/trace.hh" 613825Ssaidi@eecs.umich.edu#include "base/types.hh" 623840Shsul@eecs.umich.edu#include "debug/Cache.hh" 633825Ssaidi@eecs.umich.edu#include "debug/CachePort.hh" 643506Ssaidi@eecs.umich.edu#include "mem/cache/mshr_queue.hh" 653506Ssaidi@eecs.umich.edu#include "mem/mem_object.hh" 663506Ssaidi@eecs.umich.edu#include "mem/packet.hh" 673506Ssaidi@eecs.umich.edu#include "mem/qport.hh" 682SN/A#include "mem/request.hh" 692SN/A#include "params/BaseCache.hh" 702SN/A#include "sim/eventq.hh" 712SN/A#include "sim/full_system.hh" 722SN/A#include "sim/sim_exit.hh" 733748Sgblack@eecs.umich.edu#include "sim/system.hh" 743748Sgblack@eecs.umich.edu 753748Sgblack@eecs.umich.educlass MSHR; 763748Sgblack@eecs.umich.edu/** 773748Sgblack@eecs.umich.edu * A basic cache interface. Implements some common functions for speed. 783748Sgblack@eecs.umich.edu */ 793748Sgblack@eecs.umich.educlass BaseCache : public MemObject 803748Sgblack@eecs.umich.edu{ 813748Sgblack@eecs.umich.edu /** 823748Sgblack@eecs.umich.edu * Indexes to enumerate the MSHR queues. 833748Sgblack@eecs.umich.edu */ 843748Sgblack@eecs.umich.edu enum MSHRQueueIndex { 853748Sgblack@eecs.umich.edu MSHRQueue_MSHRs, 863748Sgblack@eecs.umich.edu MSHRQueue_WriteBuffer 873748Sgblack@eecs.umich.edu }; 883748Sgblack@eecs.umich.edu 893748Sgblack@eecs.umich.edu public: 903748Sgblack@eecs.umich.edu /** 913748Sgblack@eecs.umich.edu * Reasons for caches to be blocked. 923748Sgblack@eecs.umich.edu */ 933748Sgblack@eecs.umich.edu enum BlockedCause { 943748Sgblack@eecs.umich.edu Blocked_NoMSHRs = MSHRQueue_MSHRs, 953748Sgblack@eecs.umich.edu Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 963748Sgblack@eecs.umich.edu Blocked_NoTargets, 973748Sgblack@eecs.umich.edu NUM_BLOCKED_CAUSES 983748Sgblack@eecs.umich.edu }; 993748Sgblack@eecs.umich.edu 1003748Sgblack@eecs.umich.edu /** 1013748Sgblack@eecs.umich.edu * Reasons for cache to request a bus. 1023748Sgblack@eecs.umich.edu */ 1033748Sgblack@eecs.umich.edu enum RequestCause { 1043748Sgblack@eecs.umich.edu Request_MSHR = MSHRQueue_MSHRs, 1053748Sgblack@eecs.umich.edu Request_WB = MSHRQueue_WriteBuffer, 1063748Sgblack@eecs.umich.edu Request_PF, 1073748Sgblack@eecs.umich.edu NUM_REQUEST_CAUSES 1083748Sgblack@eecs.umich.edu }; 1093748Sgblack@eecs.umich.edu 1103748Sgblack@eecs.umich.edu protected: 1113748Sgblack@eecs.umich.edu 1123748Sgblack@eecs.umich.edu /** 1133748Sgblack@eecs.umich.edu * A cache master port is used for the memory-side port of the 1143748Sgblack@eecs.umich.edu * cache, and in addition to the basic timing port that only sends 1153748Sgblack@eecs.umich.edu * response packets through a transmit list, it also offers the 1163748Sgblack@eecs.umich.edu * ability to schedule and send request packets (requests & 1173748Sgblack@eecs.umich.edu * writebacks). The send event is scheduled through requestBus, 1183748Sgblack@eecs.umich.edu * and the sendDeferredPacket of the timing port is modified to 1193748Sgblack@eecs.umich.edu * consider both the transmit list and the requests from the MSHR. 1203748Sgblack@eecs.umich.edu */ 1213748Sgblack@eecs.umich.edu class CacheMasterPort : public QueuedMasterPort 1223748Sgblack@eecs.umich.edu { 1232SN/A 1242SN/A public: 1252SN/A 1262SN/A /** 1272973Sgblack@eecs.umich.edu * Schedule a send of a request packet (from the MSHR). Note 1282973Sgblack@eecs.umich.edu * that we could already have a retry or a transmit list of 1293065Sgblack@eecs.umich.edu * responses outstanding. 1303380Sgblack@eecs.umich.edu */ 1313380Sgblack@eecs.umich.edu void requestBus(RequestCause cause, Tick time) 1323380Sgblack@eecs.umich.edu { 1333380Sgblack@eecs.umich.edu DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 1343380Sgblack@eecs.umich.edu queue.schedSendEvent(time); 1353380Sgblack@eecs.umich.edu } 1363380Sgblack@eecs.umich.edu 1373380Sgblack@eecs.umich.edu protected: 1383380Sgblack@eecs.umich.edu 1393380Sgblack@eecs.umich.edu CacheMasterPort(const std::string &_name, BaseCache *_cache, 1403380Sgblack@eecs.umich.edu MasterPacketQueue &_queue) : 1413380Sgblack@eecs.umich.edu QueuedMasterPort(_name, _cache, _queue) 1423380Sgblack@eecs.umich.edu { } 1433380Sgblack@eecs.umich.edu 1443065Sgblack@eecs.umich.edu /** 1453588Sgblack@eecs.umich.edu * Memory-side port always snoops. 1463588Sgblack@eecs.umich.edu * 1473588Sgblack@eecs.umich.edu * @return always true 1483380Sgblack@eecs.umich.edu */ 1493380Sgblack@eecs.umich.edu virtual bool isSnooping() const { return true; } 1503059Sgblack@eecs.umich.edu }; 1513588Sgblack@eecs.umich.edu 1523380Sgblack@eecs.umich.edu /** 1533380Sgblack@eecs.umich.edu * A cache slave port is used for the CPU-side port of the cache, 1543380Sgblack@eecs.umich.edu * and it is basically a simple timing port that uses a transmit 1553380Sgblack@eecs.umich.edu * list for responses to the CPU (or connected master). In 1563380Sgblack@eecs.umich.edu * addition, it has the functionality to block the port for 1573588Sgblack@eecs.umich.edu * incoming requests. If blocked, the port will issue a retry once 1583380Sgblack@eecs.umich.edu * unblocked. 1593380Sgblack@eecs.umich.edu */ 1603380Sgblack@eecs.umich.edu class CacheSlavePort : public QueuedSlavePort 1613380Sgblack@eecs.umich.edu { 1623380Sgblack@eecs.umich.edu 1633059Sgblack@eecs.umich.edu public: 1643380Sgblack@eecs.umich.edu 1653380Sgblack@eecs.umich.edu /** Do not accept any new requests. */ 1663380Sgblack@eecs.umich.edu void setBlocked(); 1673380Sgblack@eecs.umich.edu 1683588Sgblack@eecs.umich.edu /** Return to normal operation and accept new requests. */ 1693380Sgblack@eecs.umich.edu void clearBlocked(); 1703380Sgblack@eecs.umich.edu 1713059Sgblack@eecs.umich.edu protected: 1723059Sgblack@eecs.umich.edu 1733380Sgblack@eecs.umich.edu CacheSlavePort(const std::string &_name, BaseCache *_cache, 1743380Sgblack@eecs.umich.edu const std::string &_label); 1753380Sgblack@eecs.umich.edu 1763380Sgblack@eecs.umich.edu /** A normal packet queue used to store responses. */ 1773380Sgblack@eecs.umich.edu SlavePacketQueue queue; 1783588Sgblack@eecs.umich.edu 1793380Sgblack@eecs.umich.edu bool blocked; 1803380Sgblack@eecs.umich.edu 1813380Sgblack@eecs.umich.edu bool mustSendRetry; 1823588Sgblack@eecs.umich.edu 1833059Sgblack@eecs.umich.edu private: 1843065Sgblack@eecs.umich.edu 1852973Sgblack@eecs.umich.edu EventWrapper<SlavePort, &SlavePort::sendRetry> sendRetryEvent; 1862973Sgblack@eecs.umich.edu 1871968SN/A }; 1883064Sgblack@eecs.umich.edu 1891968SN/A CacheSlavePort *cpuSidePort; 1901968SN/A CacheMasterPort *memSidePort; 1911968SN/A 1921968SN/A protected: 1931967SN/A 1941967SN/A /** Miss status registers */ 1951967SN/A MSHRQueue mshrQueue; 1961967SN/A 1971967SN/A /** Write/writeback buffer */ 1981967SN/A MSHRQueue writeBuffer; 1991967SN/A 2001967SN/A MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 2011967SN/A PacketPtr pkt, Tick time, bool requestBus) 2021967SN/A { 2031904SN/A MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 2041904SN/A 2051904SN/A if (mq->isFull()) { 2061904SN/A setBlocked((BlockedCause)mq->index); 207452SN/A } 2083064Sgblack@eecs.umich.edu 2092SN/A if (requestBus) { 2101904SN/A requestMemSideBus((RequestCause)mq->index, time); 2111904SN/A } 2122SN/A 2131904SN/A return mshr; 2143064Sgblack@eecs.umich.edu } 2152SN/A 2162SN/A void markInServiceInternal(MSHR *mshr, PacketPtr pkt) 2171904SN/A { 2181904SN/A MSHRQueue *mq = mshr->queue; 2191904SN/A bool wasFull = mq->isFull(); 2202299SN/A mq->markInService(mshr, pkt); 2212299SN/A if (wasFull && !mq->isFull()) { 2221904SN/A clearBlocked((BlockedCause)mq->index); 2231904SN/A } 2241904SN/A } 2251904SN/A 2261904SN/A /** 2271904SN/A * Write back dirty blocks in the cache using functional accesses. 2281904SN/A */ 229452SN/A virtual void memWriteback() = 0; 2301904SN/A /** 2311904SN/A * Invalidates all blocks in the cache. 2321904SN/A * 2332SN/A * @warn Dirty cache lines will not be written back to 2342SN/A * memory. Make sure to call functionalWriteback() first if you 2351904SN/A * want the to write them to memory. 2361904SN/A */ 2371904SN/A virtual void memInvalidate() = 0; 2381904SN/A /** 2391904SN/A * Determine if there are any dirty blocks in the cache. 2401904SN/A * 2412SN/A * \return true if at least one block is dirty, false otherwise. 2421904SN/A */ 2432SN/A virtual bool isDirty() const = 0; 2442SN/A 2451904SN/A /** Block size of this cache */ 2462SN/A const unsigned blkSize; 2471904SN/A 2481904SN/A /** 2491904SN/A * The latency of a hit in this device. 2501904SN/A */ 2511904SN/A const Cycles hitLatency; 2521904SN/A 2531904SN/A /** 2541904SN/A * The latency of sending reponse to its upper level cache/core on a 2551904SN/A * linefill. In most contemporary processors, the return path on a cache 2561904SN/A * miss is much quicker that the hit latency. The responseLatency parameter 2571904SN/A * tries to capture this latency. 2581904SN/A */ 2591904SN/A const Cycles responseLatency; 2601904SN/A 2611904SN/A /** The number of targets for each MSHR. */ 2621904SN/A const int numTarget; 2631904SN/A 2641904SN/A /** Do we forward snoops from mem side port through to cpu side port? */ 2651904SN/A bool forwardSnoops; 2661904SN/A 2672525SN/A /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should 2681904SN/A * never try to forward ownership and similar optimizations to the cpu 2692525SN/A * side */ 2702525SN/A bool isTopLevel; 2712525SN/A 2721904SN/A /** 2731904SN/A * Bit vector of the blocking reasons for the access path. 2741904SN/A * @sa #BlockedCause 2751904SN/A */ 2761904SN/A uint8_t blocked; 2771904SN/A 2781904SN/A /** Increasing order number assigned to each incoming request. */ 2791904SN/A uint64_t order; 2801967SN/A 2811967SN/A /** Stores time the cache blocked for statistics. */ 2821967SN/A Cycles blockedCycle; 2831967SN/A 2841967SN/A /** Pointer to the MSHR that has no targets. */ 2852SN/A MSHR *noTargetMSHR; 2863817Ssaidi@eecs.umich.edu 2873506Ssaidi@eecs.umich.edu /** The number of misses to trigger an exit event. */ 2883506Ssaidi@eecs.umich.edu Counter missCount; 2893506Ssaidi@eecs.umich.edu 2903506Ssaidi@eecs.umich.edu /** The drain event. */ 2913506Ssaidi@eecs.umich.edu DrainManager *drainManager; 2923814Ssaidi@eecs.umich.edu 2933506Ssaidi@eecs.umich.edu /** 2943506Ssaidi@eecs.umich.edu * The address range to which the cache responds on the CPU side. 2953748Sgblack@eecs.umich.edu * Normally this is all possible memory addresses. */ 2963748Sgblack@eecs.umich.edu AddrRangeList addrRanges; 2973748Sgblack@eecs.umich.edu 2983748Sgblack@eecs.umich.edu public: 2993748Sgblack@eecs.umich.edu /** System we are currently operating in. */ 3003748Sgblack@eecs.umich.edu System *system; 3013748Sgblack@eecs.umich.edu 3023748Sgblack@eecs.umich.edu // Statistics 3033748Sgblack@eecs.umich.edu /** 3043748Sgblack@eecs.umich.edu * @addtogroup CacheStatistics 3053748Sgblack@eecs.umich.edu * @{ 3063748Sgblack@eecs.umich.edu */ 3073748Sgblack@eecs.umich.edu 3083748Sgblack@eecs.umich.edu /** Number of hits per thread for each type of command. @sa Packet::Command */ 3093748Sgblack@eecs.umich.edu Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 3103748Sgblack@eecs.umich.edu /** Number of hits for demand accesses. */ 3113748Sgblack@eecs.umich.edu Stats::Formula demandHits; 3123748Sgblack@eecs.umich.edu /** Number of hit for all accesses. */ 3133748Sgblack@eecs.umich.edu Stats::Formula overallHits; 3143748Sgblack@eecs.umich.edu 3153603Ssaidi@eecs.umich.edu /** Number of misses per thread for each type of command. @sa Packet::Command */ 3163603Ssaidi@eecs.umich.edu Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 3173506Ssaidi@eecs.umich.edu /** Number of misses for demand accesses. */ 3183584Ssaidi@eecs.umich.edu Stats::Formula demandMisses; 3193584Ssaidi@eecs.umich.edu /** Number of misses for all accesses. */ 3203584Ssaidi@eecs.umich.edu Stats::Formula overallMisses; 3213748Sgblack@eecs.umich.edu 3223748Sgblack@eecs.umich.edu /** 3233603Ssaidi@eecs.umich.edu * Total number of cycles per thread/command spent waiting for a miss. 3243584Ssaidi@eecs.umich.edu * Used to calculate the average miss latency. 3253814Ssaidi@eecs.umich.edu */ 3263814Ssaidi@eecs.umich.edu Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 3273814Ssaidi@eecs.umich.edu /** Total number of cycles spent waiting for demand misses. */ 3283814Ssaidi@eecs.umich.edu Stats::Formula demandMissLatency; 3293814Ssaidi@eecs.umich.edu /** Total number of cycles spent waiting for all misses. */ 3303743Sgblack@eecs.umich.edu Stats::Formula overallMissLatency; 3313743Sgblack@eecs.umich.edu 3323584Ssaidi@eecs.umich.edu /** The number of accesses per command and thread. */ 3333743Sgblack@eecs.umich.edu Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 3343754Sgblack@eecs.umich.edu /** The number of demand accesses. */ 3353603Ssaidi@eecs.umich.edu Stats::Formula demandAccesses; 3363584Ssaidi@eecs.umich.edu /** The number of overall accesses. */ 3373603Ssaidi@eecs.umich.edu Stats::Formula overallAccesses; 3383584Ssaidi@eecs.umich.edu 3393748Sgblack@eecs.umich.edu /** The miss rate per command and thread. */ 3403748Sgblack@eecs.umich.edu Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 3413748Sgblack@eecs.umich.edu /** The miss rate of all demand accesses. */ 3423748Sgblack@eecs.umich.edu Stats::Formula demandMissRate; 3433748Sgblack@eecs.umich.edu /** The miss rate for all accesses. */ 3443748Sgblack@eecs.umich.edu Stats::Formula overallMissRate; 3453815Ssaidi@eecs.umich.edu 3463748Sgblack@eecs.umich.edu /** The average miss latency per command and thread. */ 3473748Sgblack@eecs.umich.edu Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 3483815Ssaidi@eecs.umich.edu /** The average miss latency for demand misses. */ 3493748Sgblack@eecs.umich.edu Stats::Formula demandAvgMissLatency; 3503748Sgblack@eecs.umich.edu /** The average miss latency for all misses. */ 3513815Ssaidi@eecs.umich.edu Stats::Formula overallAvgMissLatency; 3523748Sgblack@eecs.umich.edu 3533748Sgblack@eecs.umich.edu /** The total number of cycles blocked for each blocked cause. */ 3543815Ssaidi@eecs.umich.edu Stats::Vector blocked_cycles; 3553748Sgblack@eecs.umich.edu /** The number of times this cache blocked for each blocked cause. */ 3563748Sgblack@eecs.umich.edu Stats::Vector blocked_causes; 3573815Ssaidi@eecs.umich.edu 3583748Sgblack@eecs.umich.edu /** The average number of cycles blocked for each blocked cause. */ 3593748Sgblack@eecs.umich.edu Stats::Formula avg_blocked; 3603748Sgblack@eecs.umich.edu 3613584Ssaidi@eecs.umich.edu /** The number of fast writes (WH64) performed. */ 3623748Sgblack@eecs.umich.edu Stats::Scalar fastWrites; 3633748Sgblack@eecs.umich.edu 3643748Sgblack@eecs.umich.edu /** The number of cache copies performed. */ 3653748Sgblack@eecs.umich.edu Stats::Scalar cacheCopies; 3663748Sgblack@eecs.umich.edu 3673748Sgblack@eecs.umich.edu /** Number of blocks written back per thread. */ 3683748Sgblack@eecs.umich.edu Stats::Vector writebacks; 3693748Sgblack@eecs.umich.edu 3703748Sgblack@eecs.umich.edu /** Number of misses that hit in the MSHRs per command and thread. */ 3713748Sgblack@eecs.umich.edu Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 3723748Sgblack@eecs.umich.edu /** Demand misses that hit in the MSHRs. */ 3733748Sgblack@eecs.umich.edu Stats::Formula demandMshrHits; 3743748Sgblack@eecs.umich.edu /** Total number of misses that hit in the MSHRs. */ 3753748Sgblack@eecs.umich.edu Stats::Formula overallMshrHits; 3763748Sgblack@eecs.umich.edu 3773748Sgblack@eecs.umich.edu /** Number of misses that miss in the MSHRs, per command and thread. */ 3783748Sgblack@eecs.umich.edu Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 3793748Sgblack@eecs.umich.edu /** Demand misses that miss in the MSHRs. */ 3803748Sgblack@eecs.umich.edu Stats::Formula demandMshrMisses; 3813748Sgblack@eecs.umich.edu /** Total number of misses that miss in the MSHRs. */ 3823748Sgblack@eecs.umich.edu Stats::Formula overallMshrMisses; 3833748Sgblack@eecs.umich.edu 3843748Sgblack@eecs.umich.edu /** Number of misses that miss in the MSHRs, per command and thread. */ 3853748Sgblack@eecs.umich.edu Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 3863748Sgblack@eecs.umich.edu /** Total number of misses that miss in the MSHRs. */ 3873748Sgblack@eecs.umich.edu Stats::Formula overallMshrUncacheable; 3883748Sgblack@eecs.umich.edu 3893748Sgblack@eecs.umich.edu /** Total cycle latency of each MSHR miss, per command and thread. */ 3903748Sgblack@eecs.umich.edu Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 3913748Sgblack@eecs.umich.edu /** Total cycle latency of demand MSHR misses. */ 3923748Sgblack@eecs.umich.edu Stats::Formula demandMshrMissLatency; 3933748Sgblack@eecs.umich.edu /** Total cycle latency of overall MSHR misses. */ 3943748Sgblack@eecs.umich.edu Stats::Formula overallMshrMissLatency; 3953748Sgblack@eecs.umich.edu 3963748Sgblack@eecs.umich.edu /** Total cycle latency of each MSHR miss, per command and thread. */ 3973748Sgblack@eecs.umich.edu Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 3983826Ssaidi@eecs.umich.edu /** Total cycle latency of overall MSHR misses. */ 3993814Ssaidi@eecs.umich.edu Stats::Formula overallMshrUncacheableLatency; 4003748Sgblack@eecs.umich.edu 4013748Sgblack@eecs.umich.edu#if 0 4023748Sgblack@eecs.umich.edu /** The total number of MSHR accesses per command and thread. */ 4033826Ssaidi@eecs.umich.edu Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 4043832Ssaidi@eecs.umich.edu /** The total number of demand MSHR accesses. */ 4053584Ssaidi@eecs.umich.edu Stats::Formula demandMshrAccesses; 4063584Ssaidi@eecs.umich.edu /** The total number of MSHR accesses. */ 4073584Ssaidi@eecs.umich.edu Stats::Formula overallMshrAccesses; 4083814Ssaidi@eecs.umich.edu#endif 4093814Ssaidi@eecs.umich.edu 4103584Ssaidi@eecs.umich.edu /** The miss rate in the MSHRs pre command and thread. */ 4113584Ssaidi@eecs.umich.edu Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 4123584Ssaidi@eecs.umich.edu /** The demand miss rate in the MSHRs. */ 4133584Ssaidi@eecs.umich.edu Stats::Formula demandMshrMissRate; 4143748Sgblack@eecs.umich.edu /** The overall miss rate in the MSHRs. */ 4153748Sgblack@eecs.umich.edu Stats::Formula overallMshrMissRate; 4163748Sgblack@eecs.umich.edu 4173748Sgblack@eecs.umich.edu /** The average latency of an MSHR miss, per command and thread. */ 4183748Sgblack@eecs.umich.edu Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 4193748Sgblack@eecs.umich.edu /** The average latency of a demand MSHR miss. */ 4203748Sgblack@eecs.umich.edu Stats::Formula demandAvgMshrMissLatency; 4213748Sgblack@eecs.umich.edu /** The average overall latency of an MSHR miss. */ 4223748Sgblack@eecs.umich.edu Stats::Formula overallAvgMshrMissLatency; 4233748Sgblack@eecs.umich.edu 4243748Sgblack@eecs.umich.edu /** The average latency of an MSHR miss, per command and thread. */ 4253748Sgblack@eecs.umich.edu Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 4263748Sgblack@eecs.umich.edu /** The average overall latency of an MSHR miss. */ 4273748Sgblack@eecs.umich.edu Stats::Formula overallAvgMshrUncacheableLatency; 4283748Sgblack@eecs.umich.edu 4293748Sgblack@eecs.umich.edu /** The number of times a thread hit its MSHR cap. */ 4303748Sgblack@eecs.umich.edu Stats::Vector mshr_cap_events; 4313748Sgblack@eecs.umich.edu /** The number of times software prefetches caused the MSHR to block. */ 4323748Sgblack@eecs.umich.edu Stats::Vector soft_prefetch_mshr_full; 4333748Sgblack@eecs.umich.edu 4343748Sgblack@eecs.umich.edu Stats::Scalar mshr_no_allocate_misses; 4353748Sgblack@eecs.umich.edu 4363748Sgblack@eecs.umich.edu /** 4373748Sgblack@eecs.umich.edu * @} 4383748Sgblack@eecs.umich.edu */ 4393748Sgblack@eecs.umich.edu 4403748Sgblack@eecs.umich.edu /** 4413748Sgblack@eecs.umich.edu * Register stats for this object. 4423748Sgblack@eecs.umich.edu */ 4433748Sgblack@eecs.umich.edu virtual void regStats(); 4443748Sgblack@eecs.umich.edu 4453748Sgblack@eecs.umich.edu public: 4463748Sgblack@eecs.umich.edu typedef BaseCacheParams Params; 4473748Sgblack@eecs.umich.edu BaseCache(const Params *p); 4483748Sgblack@eecs.umich.edu ~BaseCache() {} 4493748Sgblack@eecs.umich.edu 4503748Sgblack@eecs.umich.edu virtual void init(); 4513748Sgblack@eecs.umich.edu 4523603Ssaidi@eecs.umich.edu virtual BaseMasterPort &getMasterPort(const std::string &if_name, 4533584Ssaidi@eecs.umich.edu PortID idx = InvalidPortID); 4543603Ssaidi@eecs.umich.edu virtual BaseSlavePort &getSlavePort(const std::string &if_name, 4553584Ssaidi@eecs.umich.edu PortID idx = InvalidPortID); 4563603Ssaidi@eecs.umich.edu 4573584Ssaidi@eecs.umich.edu /** 4583584Ssaidi@eecs.umich.edu * Query block size of a cache. 4593603Ssaidi@eecs.umich.edu * @return The block size 4603584Ssaidi@eecs.umich.edu */ 4613814Ssaidi@eecs.umich.edu unsigned 4623814Ssaidi@eecs.umich.edu getBlockSize() const 4633814Ssaidi@eecs.umich.edu { 4643814Ssaidi@eecs.umich.edu return blkSize; 4653814Ssaidi@eecs.umich.edu } 4663814Ssaidi@eecs.umich.edu 4673814Ssaidi@eecs.umich.edu 4683584Ssaidi@eecs.umich.edu Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 4693584Ssaidi@eecs.umich.edu 4703584Ssaidi@eecs.umich.edu 4713603Ssaidi@eecs.umich.edu const AddrRangeList &getAddrRanges() const { return addrRanges; } 4723584Ssaidi@eecs.umich.edu 4733584Ssaidi@eecs.umich.edu MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 4743748Sgblack@eecs.umich.edu { 4753748Sgblack@eecs.umich.edu assert(!pkt->req->isUncacheable()); 4763748Sgblack@eecs.umich.edu return allocateBufferInternal(&mshrQueue, 4773584Ssaidi@eecs.umich.edu blockAlign(pkt->getAddr()), blkSize, 4783584Ssaidi@eecs.umich.edu pkt, time, requestBus); 4793584Ssaidi@eecs.umich.edu } 4803584Ssaidi@eecs.umich.edu 4813603Ssaidi@eecs.umich.edu MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 4823748Sgblack@eecs.umich.edu { 4833584Ssaidi@eecs.umich.edu assert(pkt->isWrite() && !pkt->isRead()); 4843748Sgblack@eecs.umich.edu return allocateBufferInternal(&writeBuffer, 4853748Sgblack@eecs.umich.edu pkt->getAddr(), pkt->getSize(), 4863748Sgblack@eecs.umich.edu pkt, time, requestBus); 4873748Sgblack@eecs.umich.edu } 4883748Sgblack@eecs.umich.edu 4893748Sgblack@eecs.umich.edu MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus) 4903748Sgblack@eecs.umich.edu { 4913748Sgblack@eecs.umich.edu assert(pkt->req->isUncacheable()); 4923748Sgblack@eecs.umich.edu assert(pkt->isRead()); 4933748Sgblack@eecs.umich.edu return allocateBufferInternal(&mshrQueue, 4943748Sgblack@eecs.umich.edu pkt->getAddr(), pkt->getSize(), 4953748Sgblack@eecs.umich.edu pkt, time, requestBus); 4963748Sgblack@eecs.umich.edu } 4973748Sgblack@eecs.umich.edu 4983748Sgblack@eecs.umich.edu /** 4993748Sgblack@eecs.umich.edu * Returns true if the cache is blocked for accesses. 5003748Sgblack@eecs.umich.edu */ 5013748Sgblack@eecs.umich.edu bool isBlocked() 5023748Sgblack@eecs.umich.edu { 5033748Sgblack@eecs.umich.edu return blocked != 0; 5043748Sgblack@eecs.umich.edu } 5053748Sgblack@eecs.umich.edu 5063748Sgblack@eecs.umich.edu /** 5073748Sgblack@eecs.umich.edu * Marks the access path of the cache as blocked for the given cause. This 5083748Sgblack@eecs.umich.edu * also sets the blocked flag in the slave interface. 5093748Sgblack@eecs.umich.edu * @param cause The reason for the cache blocking. 5103748Sgblack@eecs.umich.edu */ 5113748Sgblack@eecs.umich.edu void setBlocked(BlockedCause cause) 5123748Sgblack@eecs.umich.edu { 5133748Sgblack@eecs.umich.edu uint8_t flag = 1 << cause; 5143748Sgblack@eecs.umich.edu if (blocked == 0) { 5153748Sgblack@eecs.umich.edu blocked_causes[cause]++; 5163748Sgblack@eecs.umich.edu blockedCycle = curCycle(); 5173748Sgblack@eecs.umich.edu cpuSidePort->setBlocked(); 5183748Sgblack@eecs.umich.edu } 5193748Sgblack@eecs.umich.edu blocked |= flag; 5203748Sgblack@eecs.umich.edu DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 5213748Sgblack@eecs.umich.edu } 5223748Sgblack@eecs.umich.edu 5233748Sgblack@eecs.umich.edu /** 5243748Sgblack@eecs.umich.edu * Marks the cache as unblocked for the given cause. This also clears the 5253748Sgblack@eecs.umich.edu * blocked flags in the appropriate interfaces. 5263748Sgblack@eecs.umich.edu * @param cause The newly unblocked cause. 5273748Sgblack@eecs.umich.edu * @warning Calling this function can cause a blocked request on the bus to 5283748Sgblack@eecs.umich.edu * access the cache. The cache must be in a state to handle that request. 5293748Sgblack@eecs.umich.edu */ 5303748Sgblack@eecs.umich.edu void clearBlocked(BlockedCause cause) 5313748Sgblack@eecs.umich.edu { 5323748Sgblack@eecs.umich.edu uint8_t flag = 1 << cause; 5333748Sgblack@eecs.umich.edu blocked &= ~flag; 5343748Sgblack@eecs.umich.edu DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 5353815Ssaidi@eecs.umich.edu if (blocked == 0) { 5363748Sgblack@eecs.umich.edu blocked_cycles[cause] += curCycle() - blockedCycle; 5373748Sgblack@eecs.umich.edu cpuSidePort->clearBlocked(); 5383815Ssaidi@eecs.umich.edu } 5393748Sgblack@eecs.umich.edu } 5403748Sgblack@eecs.umich.edu 5413815Ssaidi@eecs.umich.edu /** 5423748Sgblack@eecs.umich.edu * Request the master bus for the given cause and time. 5433748Sgblack@eecs.umich.edu * @param cause The reason for the request. 5443815Ssaidi@eecs.umich.edu * @param time The time to make the request. 5453748Sgblack@eecs.umich.edu */ 5463748Sgblack@eecs.umich.edu void requestMemSideBus(RequestCause cause, Tick time) 5473815Ssaidi@eecs.umich.edu { 5483748Sgblack@eecs.umich.edu memSidePort->requestBus(cause, time); 5493748Sgblack@eecs.umich.edu } 5503584Ssaidi@eecs.umich.edu 5513584Ssaidi@eecs.umich.edu /** 5523748Sgblack@eecs.umich.edu * Clear the master bus request for the given cause. 5533584Ssaidi@eecs.umich.edu * @param cause The request reason to clear. 5543584Ssaidi@eecs.umich.edu */ 5553584Ssaidi@eecs.umich.edu void deassertMemSideBusRequest(RequestCause cause) 5563584Ssaidi@eecs.umich.edu { 5573584Ssaidi@eecs.umich.edu // Obsolete... we no longer signal bus requests explicitly so 5583748Sgblack@eecs.umich.edu // we can't deassert them. Leaving this in as a no-op since 5593748Sgblack@eecs.umich.edu // the prefetcher calls it to indicate that it no longer wants 5603748Sgblack@eecs.umich.edu // to request a prefetch, and someday that might be 5613748Sgblack@eecs.umich.edu // interesting again. 5623748Sgblack@eecs.umich.edu } 5633748Sgblack@eecs.umich.edu 5643748Sgblack@eecs.umich.edu virtual unsigned int drain(DrainManager *dm); 5653748Sgblack@eecs.umich.edu 5663748Sgblack@eecs.umich.edu virtual bool inCache(Addr addr) = 0; 5673748Sgblack@eecs.umich.edu 5683584Ssaidi@eecs.umich.edu virtual bool inMissQueue(Addr addr) = 0; 5693584Ssaidi@eecs.umich.edu 5703584Ssaidi@eecs.umich.edu void incMissCount(PacketPtr pkt) 5713748Sgblack@eecs.umich.edu { 5723748Sgblack@eecs.umich.edu assert(pkt->req->masterId() < system->maxMasters()); 5733748Sgblack@eecs.umich.edu misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 5743584Ssaidi@eecs.umich.edu 5753584Ssaidi@eecs.umich.edu if (missCount) { 5763826Ssaidi@eecs.umich.edu --missCount; 5773826Ssaidi@eecs.umich.edu if (missCount == 0) 5783826Ssaidi@eecs.umich.edu exitSimLoop("A cache reached the maximum miss count"); 5793825Ssaidi@eecs.umich.edu } 5803832Ssaidi@eecs.umich.edu } 5813825Ssaidi@eecs.umich.edu void incHitCount(PacketPtr pkt) 5823584Ssaidi@eecs.umich.edu { 5833584Ssaidi@eecs.umich.edu assert(pkt->req->masterId() < system->maxMasters()); 5843584Ssaidi@eecs.umich.edu hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 5853584Ssaidi@eecs.umich.edu 5863506Ssaidi@eecs.umich.edu } 5873584Ssaidi@eecs.umich.edu 5883584Ssaidi@eecs.umich.edu}; 5893506Ssaidi@eecs.umich.edu 5903584Ssaidi@eecs.umich.edu#endif //__BASE_CACHE_HH__ 5912SN/A