base.hh revision 8975
12810SN/A/* 28856Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 414458SN/A * Steve Reinhardt 424458SN/A * Ron Dreslinski 432810SN/A */ 442810SN/A 452810SN/A/** 462810SN/A * @file 472810SN/A * Declares a basic cache interface BaseCache. 482810SN/A */ 492810SN/A 502810SN/A#ifndef __BASE_CACHE_HH__ 512810SN/A#define __BASE_CACHE_HH__ 522810SN/A 537676Snate@binkert.org#include <algorithm> 547676Snate@binkert.org#include <list> 557676Snate@binkert.org#include <string> 562810SN/A#include <vector> 572810SN/A 582825SN/A#include "base/misc.hh" 592810SN/A#include "base/statistics.hh" 602810SN/A#include "base/trace.hh" 616215Snate@binkert.org#include "base/types.hh" 628232Snate@binkert.org#include "debug/Cache.hh" 638232Snate@binkert.org#include "debug/CachePort.hh" 645338Sstever@gmail.com#include "mem/cache/mshr_queue.hh" 652810SN/A#include "mem/mem_object.hh" 662810SN/A#include "mem/packet.hh" 678914Sandreas.hansson@arm.com#include "mem/qport.hh" 688229Snate@binkert.org#include "mem/request.hh" 695034SN/A#include "params/BaseCache.hh" 702811SN/A#include "sim/eventq.hh" 718786Sgblack@eecs.umich.edu#include "sim/full_system.hh" 724626SN/A#include "sim/sim_exit.hh" 738833Sdam.sunwoo@arm.com#include "sim/system.hh" 742810SN/A 753194SN/Aclass MSHR; 762810SN/A/** 772810SN/A * A basic cache interface. Implements some common functions for speed. 782810SN/A */ 792810SN/Aclass BaseCache : public MemObject 802810SN/A{ 814628SN/A /** 824628SN/A * Indexes to enumerate the MSHR queues. 834628SN/A */ 844628SN/A enum MSHRQueueIndex { 854628SN/A MSHRQueue_MSHRs, 864628SN/A MSHRQueue_WriteBuffer 874628SN/A }; 884628SN/A 898737Skoansin.tan@gmail.com public: 904628SN/A /** 914628SN/A * Reasons for caches to be blocked. 924628SN/A */ 934628SN/A enum BlockedCause { 944628SN/A Blocked_NoMSHRs = MSHRQueue_MSHRs, 954628SN/A Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 964628SN/A Blocked_NoTargets, 974628SN/A NUM_BLOCKED_CAUSES 984628SN/A }; 994628SN/A 1004628SN/A /** 1014628SN/A * Reasons for cache to request a bus. 1024628SN/A */ 1034628SN/A enum RequestCause { 1044628SN/A Request_MSHR = MSHRQueue_MSHRs, 1054628SN/A Request_WB = MSHRQueue_WriteBuffer, 1064628SN/A Request_PF, 1074628SN/A NUM_REQUEST_CAUSES 1084628SN/A }; 1094628SN/A 1108737Skoansin.tan@gmail.com protected: 1114628SN/A 1128856Sandreas.hansson@arm.com /** 1138856Sandreas.hansson@arm.com * A cache master port is used for the memory-side port of the 1148856Sandreas.hansson@arm.com * cache, and in addition to the basic timing port that only sends 1158856Sandreas.hansson@arm.com * response packets through a transmit list, it also offers the 1168856Sandreas.hansson@arm.com * ability to schedule and send request packets (requests & 1178856Sandreas.hansson@arm.com * writebacks). The send event is scheduled through requestBus, 1188856Sandreas.hansson@arm.com * and the sendDeferredPacket of the timing port is modified to 1198856Sandreas.hansson@arm.com * consider both the transmit list and the requests from the MSHR. 1208856Sandreas.hansson@arm.com */ 1218922Swilliam.wang@arm.com class CacheMasterPort : public QueuedMasterPort 1222810SN/A { 1238856Sandreas.hansson@arm.com 1242844SN/A public: 1258856Sandreas.hansson@arm.com 1268856Sandreas.hansson@arm.com /** 1278856Sandreas.hansson@arm.com * Schedule a send of a request packet (from the MSHR). Note 1288856Sandreas.hansson@arm.com * that we could already have a retry or a transmit list of 1298856Sandreas.hansson@arm.com * responses outstanding. 1308856Sandreas.hansson@arm.com */ 1318856Sandreas.hansson@arm.com void requestBus(RequestCause cause, Tick time) 1328856Sandreas.hansson@arm.com { 1338856Sandreas.hansson@arm.com DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 1348914Sandreas.hansson@arm.com queue.schedSendEvent(time); 1358856Sandreas.hansson@arm.com } 1368856Sandreas.hansson@arm.com 1378914Sandreas.hansson@arm.com /** 1388914Sandreas.hansson@arm.com * Schedule the transmissions of a response packet at a given 1398914Sandreas.hansson@arm.com * point in time. 1408914Sandreas.hansson@arm.com * 1418914Sandreas.hansson@arm.com * @param pkt response packet 1428914Sandreas.hansson@arm.com * @param when time to send the response 1438914Sandreas.hansson@arm.com */ 1448856Sandreas.hansson@arm.com void respond(PacketPtr pkt, Tick time) { 1458948Sandreas.hansson@arm.com queue.schedSendTiming(pkt, time, true); 1468856Sandreas.hansson@arm.com } 1472810SN/A 1483738SN/A protected: 1494458SN/A 1508856Sandreas.hansson@arm.com CacheMasterPort(const std::string &_name, BaseCache *_cache, 1518975Sandreas.hansson@arm.com MasterPacketQueue &_queue) : 1528922Swilliam.wang@arm.com QueuedMasterPort(_name, _cache, _queue) 1538914Sandreas.hansson@arm.com { } 1542810SN/A 1558856Sandreas.hansson@arm.com /** 1568856Sandreas.hansson@arm.com * Memory-side port always snoops. 1578856Sandreas.hansson@arm.com * 1588914Sandreas.hansson@arm.com * @return always true 1598856Sandreas.hansson@arm.com */ 1608922Swilliam.wang@arm.com virtual bool isSnooping() const { return true; } 1618856Sandreas.hansson@arm.com }; 1623013SN/A 1638856Sandreas.hansson@arm.com /** 1648856Sandreas.hansson@arm.com * A cache slave port is used for the CPU-side port of the cache, 1658856Sandreas.hansson@arm.com * and it is basically a simple timing port that uses a transmit 1668856Sandreas.hansson@arm.com * list for responses to the CPU (or connected master). In 1678856Sandreas.hansson@arm.com * addition, it has the functionality to block the port for 1688856Sandreas.hansson@arm.com * incoming requests. If blocked, the port will issue a retry once 1698856Sandreas.hansson@arm.com * unblocked. 1708856Sandreas.hansson@arm.com */ 1718922Swilliam.wang@arm.com class CacheSlavePort : public QueuedSlavePort 1728856Sandreas.hansson@arm.com { 1735314SN/A 1742811SN/A public: 1758856Sandreas.hansson@arm.com 1768856Sandreas.hansson@arm.com /** Do not accept any new requests. */ 1772810SN/A void setBlocked(); 1782810SN/A 1798856Sandreas.hansson@arm.com /** Return to normal operation and accept new requests. */ 1802810SN/A void clearBlocked(); 1812810SN/A 1828914Sandreas.hansson@arm.com /** 1838914Sandreas.hansson@arm.com * Schedule the transmissions of a response packet at a given 1848914Sandreas.hansson@arm.com * point in time. 1858914Sandreas.hansson@arm.com * 1868914Sandreas.hansson@arm.com * @param pkt response packet 1878914Sandreas.hansson@arm.com * @param when time to send the response 1888914Sandreas.hansson@arm.com */ 1898856Sandreas.hansson@arm.com void respond(PacketPtr pkt, Tick time) { 1908914Sandreas.hansson@arm.com queue.schedSendTiming(pkt, time); 1918856Sandreas.hansson@arm.com } 1928856Sandreas.hansson@arm.com 1938856Sandreas.hansson@arm.com protected: 1948856Sandreas.hansson@arm.com 1958856Sandreas.hansson@arm.com CacheSlavePort(const std::string &_name, BaseCache *_cache, 1968856Sandreas.hansson@arm.com const std::string &_label); 1973606SN/A 1988914Sandreas.hansson@arm.com /** A normal packet queue used to store responses. */ 1998975Sandreas.hansson@arm.com SlavePacketQueue queue; 2008914Sandreas.hansson@arm.com 2012810SN/A bool blocked; 2022810SN/A 2032897SN/A bool mustSendRetry; 2042897SN/A 2058856Sandreas.hansson@arm.com private: 2064458SN/A 2078856Sandreas.hansson@arm.com EventWrapper<Port, &Port::sendRetry> sendRetryEvent; 2088856Sandreas.hansson@arm.com 2092811SN/A }; 2102810SN/A 2118856Sandreas.hansson@arm.com CacheSlavePort *cpuSidePort; 2128856Sandreas.hansson@arm.com CacheMasterPort *memSidePort; 2133338SN/A 2144626SN/A protected: 2154626SN/A 2164626SN/A /** Miss status registers */ 2174626SN/A MSHRQueue mshrQueue; 2184626SN/A 2194626SN/A /** Write/writeback buffer */ 2204626SN/A MSHRQueue writeBuffer; 2214626SN/A 2224628SN/A MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 2234628SN/A PacketPtr pkt, Tick time, bool requestBus) 2244628SN/A { 2254666SN/A MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 2264628SN/A 2274628SN/A if (mq->isFull()) { 2284628SN/A setBlocked((BlockedCause)mq->index); 2294628SN/A } 2304628SN/A 2314628SN/A if (requestBus) { 2324628SN/A requestMemSideBus((RequestCause)mq->index, time); 2334628SN/A } 2344628SN/A 2354628SN/A return mshr; 2364628SN/A } 2374628SN/A 2387667Ssteve.reinhardt@amd.com void markInServiceInternal(MSHR *mshr, PacketPtr pkt) 2394628SN/A { 2404628SN/A MSHRQueue *mq = mshr->queue; 2414628SN/A bool wasFull = mq->isFull(); 2427667Ssteve.reinhardt@amd.com mq->markInService(mshr, pkt); 2434628SN/A if (wasFull && !mq->isFull()) { 2444628SN/A clearBlocked((BlockedCause)mq->index); 2454628SN/A } 2464628SN/A } 2474628SN/A 2484626SN/A /** Block size of this cache */ 2496227Snate@binkert.org const unsigned blkSize; 2504626SN/A 2514630SN/A /** 2524630SN/A * The latency of a hit in this device. 2534630SN/A */ 2544630SN/A int hitLatency; 2554630SN/A 2564626SN/A /** The number of targets for each MSHR. */ 2574626SN/A const int numTarget; 2584626SN/A 2596122SSteve.Reinhardt@amd.com /** Do we forward snoops from mem side port through to cpu side port? */ 2606122SSteve.Reinhardt@amd.com bool forwardSnoops; 2614626SN/A 2628134SAli.Saidi@ARM.com /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should 2638134SAli.Saidi@ARM.com * never try to forward ownership and similar optimizations to the cpu 2648134SAli.Saidi@ARM.com * side */ 2658134SAli.Saidi@ARM.com bool isTopLevel; 2668134SAli.Saidi@ARM.com 2672810SN/A /** 2682810SN/A * Bit vector of the blocking reasons for the access path. 2692810SN/A * @sa #BlockedCause 2702810SN/A */ 2712810SN/A uint8_t blocked; 2722810SN/A 2736122SSteve.Reinhardt@amd.com /** Increasing order number assigned to each incoming request. */ 2746122SSteve.Reinhardt@amd.com uint64_t order; 2756122SSteve.Reinhardt@amd.com 2762810SN/A /** Stores time the cache blocked for statistics. */ 2772810SN/A Tick blockedCycle; 2782810SN/A 2794626SN/A /** Pointer to the MSHR that has no targets. */ 2804626SN/A MSHR *noTargetMSHR; 2812810SN/A 2822810SN/A /** The number of misses to trigger an exit event. */ 2832810SN/A Counter missCount; 2842810SN/A 2853503SN/A /** The drain event. */ 2863503SN/A Event *drainEvent; 2873503SN/A 2886122SSteve.Reinhardt@amd.com /** 2896122SSteve.Reinhardt@amd.com * The address range to which the cache responds on the CPU side. 2906122SSteve.Reinhardt@amd.com * Normally this is all possible memory addresses. */ 2918883SAli.Saidi@ARM.com AddrRangeList addrRanges; 2926122SSteve.Reinhardt@amd.com 2938833Sdam.sunwoo@arm.com public: 2948833Sdam.sunwoo@arm.com /** System we are currently operating in. */ 2958833Sdam.sunwoo@arm.com System *system; 2966978SLisa.Hsu@amd.com 2972810SN/A // Statistics 2982810SN/A /** 2992810SN/A * @addtogroup CacheStatistics 3002810SN/A * @{ 3012810SN/A */ 3022810SN/A 3032810SN/A /** Number of hits per thread for each type of command. @sa Packet::Command */ 3045999Snate@binkert.org Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 3052810SN/A /** Number of hits for demand accesses. */ 3062810SN/A Stats::Formula demandHits; 3072810SN/A /** Number of hit for all accesses. */ 3082810SN/A Stats::Formula overallHits; 3092810SN/A 3102810SN/A /** Number of misses per thread for each type of command. @sa Packet::Command */ 3115999Snate@binkert.org Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 3122810SN/A /** Number of misses for demand accesses. */ 3132810SN/A Stats::Formula demandMisses; 3142810SN/A /** Number of misses for all accesses. */ 3152810SN/A Stats::Formula overallMisses; 3162810SN/A 3172810SN/A /** 3182810SN/A * Total number of cycles per thread/command spent waiting for a miss. 3192810SN/A * Used to calculate the average miss latency. 3202810SN/A */ 3215999Snate@binkert.org Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 3222810SN/A /** Total number of cycles spent waiting for demand misses. */ 3232810SN/A Stats::Formula demandMissLatency; 3242810SN/A /** Total number of cycles spent waiting for all misses. */ 3252810SN/A Stats::Formula overallMissLatency; 3262810SN/A 3272810SN/A /** The number of accesses per command and thread. */ 3284022SN/A Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 3292810SN/A /** The number of demand accesses. */ 3302810SN/A Stats::Formula demandAccesses; 3312810SN/A /** The number of overall accesses. */ 3322810SN/A Stats::Formula overallAccesses; 3332810SN/A 3342810SN/A /** The miss rate per command and thread. */ 3354022SN/A Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 3362810SN/A /** The miss rate of all demand accesses. */ 3372810SN/A Stats::Formula demandMissRate; 3382810SN/A /** The miss rate for all accesses. */ 3392810SN/A Stats::Formula overallMissRate; 3402810SN/A 3412810SN/A /** The average miss latency per command and thread. */ 3424022SN/A Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 3432810SN/A /** The average miss latency for demand misses. */ 3442810SN/A Stats::Formula demandAvgMissLatency; 3452810SN/A /** The average miss latency for all misses. */ 3462810SN/A Stats::Formula overallAvgMissLatency; 3472810SN/A 3482810SN/A /** The total number of cycles blocked for each blocked cause. */ 3495999Snate@binkert.org Stats::Vector blocked_cycles; 3502810SN/A /** The number of times this cache blocked for each blocked cause. */ 3515999Snate@binkert.org Stats::Vector blocked_causes; 3522810SN/A 3532810SN/A /** The average number of cycles blocked for each blocked cause. */ 3542810SN/A Stats::Formula avg_blocked; 3552810SN/A 3562810SN/A /** The number of fast writes (WH64) performed. */ 3575999Snate@binkert.org Stats::Scalar fastWrites; 3582810SN/A 3592810SN/A /** The number of cache copies performed. */ 3605999Snate@binkert.org Stats::Scalar cacheCopies; 3612810SN/A 3624626SN/A /** Number of blocks written back per thread. */ 3635999Snate@binkert.org Stats::Vector writebacks; 3644626SN/A 3654626SN/A /** Number of misses that hit in the MSHRs per command and thread. */ 3665999Snate@binkert.org Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 3674626SN/A /** Demand misses that hit in the MSHRs. */ 3684626SN/A Stats::Formula demandMshrHits; 3694626SN/A /** Total number of misses that hit in the MSHRs. */ 3704626SN/A Stats::Formula overallMshrHits; 3714626SN/A 3724626SN/A /** Number of misses that miss in the MSHRs, per command and thread. */ 3735999Snate@binkert.org Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 3744626SN/A /** Demand misses that miss in the MSHRs. */ 3754626SN/A Stats::Formula demandMshrMisses; 3764626SN/A /** Total number of misses that miss in the MSHRs. */ 3774626SN/A Stats::Formula overallMshrMisses; 3784626SN/A 3794626SN/A /** Number of misses that miss in the MSHRs, per command and thread. */ 3805999Snate@binkert.org Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 3814626SN/A /** Total number of misses that miss in the MSHRs. */ 3824626SN/A Stats::Formula overallMshrUncacheable; 3834626SN/A 3844626SN/A /** Total cycle latency of each MSHR miss, per command and thread. */ 3855999Snate@binkert.org Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 3864626SN/A /** Total cycle latency of demand MSHR misses. */ 3874626SN/A Stats::Formula demandMshrMissLatency; 3884626SN/A /** Total cycle latency of overall MSHR misses. */ 3894626SN/A Stats::Formula overallMshrMissLatency; 3904626SN/A 3914626SN/A /** Total cycle latency of each MSHR miss, per command and thread. */ 3925999Snate@binkert.org Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 3934626SN/A /** Total cycle latency of overall MSHR misses. */ 3944626SN/A Stats::Formula overallMshrUncacheableLatency; 3954626SN/A 3967461Snate@binkert.org#if 0 3974626SN/A /** The total number of MSHR accesses per command and thread. */ 3984626SN/A Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 3994626SN/A /** The total number of demand MSHR accesses. */ 4004626SN/A Stats::Formula demandMshrAccesses; 4014626SN/A /** The total number of MSHR accesses. */ 4024626SN/A Stats::Formula overallMshrAccesses; 4037461Snate@binkert.org#endif 4044626SN/A 4054626SN/A /** The miss rate in the MSHRs pre command and thread. */ 4064626SN/A Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 4074626SN/A /** The demand miss rate in the MSHRs. */ 4084626SN/A Stats::Formula demandMshrMissRate; 4094626SN/A /** The overall miss rate in the MSHRs. */ 4104626SN/A Stats::Formula overallMshrMissRate; 4114626SN/A 4124626SN/A /** The average latency of an MSHR miss, per command and thread. */ 4134626SN/A Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 4144626SN/A /** The average latency of a demand MSHR miss. */ 4154626SN/A Stats::Formula demandAvgMshrMissLatency; 4164626SN/A /** The average overall latency of an MSHR miss. */ 4174626SN/A Stats::Formula overallAvgMshrMissLatency; 4184626SN/A 4194626SN/A /** The average latency of an MSHR miss, per command and thread. */ 4204626SN/A Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 4214626SN/A /** The average overall latency of an MSHR miss. */ 4224626SN/A Stats::Formula overallAvgMshrUncacheableLatency; 4234626SN/A 4244626SN/A /** The number of times a thread hit its MSHR cap. */ 4255999Snate@binkert.org Stats::Vector mshr_cap_events; 4264626SN/A /** The number of times software prefetches caused the MSHR to block. */ 4275999Snate@binkert.org Stats::Vector soft_prefetch_mshr_full; 4284626SN/A 4295999Snate@binkert.org Stats::Scalar mshr_no_allocate_misses; 4304626SN/A 4312810SN/A /** 4322810SN/A * @} 4332810SN/A */ 4342810SN/A 4352810SN/A /** 4362810SN/A * Register stats for this object. 4372810SN/A */ 4382810SN/A virtual void regStats(); 4392810SN/A 4402810SN/A public: 4415034SN/A typedef BaseCacheParams Params; 4425034SN/A BaseCache(const Params *p); 4435034SN/A ~BaseCache() {} 4443606SN/A 4452858SN/A virtual void init(); 4462858SN/A 4478922Swilliam.wang@arm.com virtual MasterPort &getMasterPort(const std::string &if_name, int idx = -1); 4488922Swilliam.wang@arm.com virtual SlavePort &getSlavePort(const std::string &if_name, int idx = -1); 4498922Swilliam.wang@arm.com 4502810SN/A /** 4512810SN/A * Query block size of a cache. 4522810SN/A * @return The block size 4532810SN/A */ 4546227Snate@binkert.org unsigned 4556227Snate@binkert.org getBlockSize() const 4562810SN/A { 4572810SN/A return blkSize; 4582810SN/A } 4592810SN/A 4604626SN/A 4616666Ssteve.reinhardt@amd.com Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 4624626SN/A 4634626SN/A 4648883SAli.Saidi@ARM.com const AddrRangeList &getAddrRanges() const { return addrRanges; } 4656122SSteve.Reinhardt@amd.com 4664628SN/A MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 4674628SN/A { 4684902SN/A assert(!pkt->req->isUncacheable()); 4694628SN/A return allocateBufferInternal(&mshrQueue, 4704628SN/A blockAlign(pkt->getAddr()), blkSize, 4714628SN/A pkt, time, requestBus); 4724628SN/A } 4734628SN/A 4744902SN/A MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 4754628SN/A { 4764902SN/A assert(pkt->isWrite() && !pkt->isRead()); 4774902SN/A return allocateBufferInternal(&writeBuffer, 4784902SN/A pkt->getAddr(), pkt->getSize(), 4794628SN/A pkt, time, requestBus); 4804628SN/A } 4814628SN/A 4824902SN/A MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus) 4834902SN/A { 4844902SN/A assert(pkt->req->isUncacheable()); 4854902SN/A assert(pkt->isRead()); 4864902SN/A return allocateBufferInternal(&mshrQueue, 4874902SN/A pkt->getAddr(), pkt->getSize(), 4884902SN/A pkt, time, requestBus); 4894902SN/A } 4904628SN/A 4912810SN/A /** 4922810SN/A * Returns true if the cache is blocked for accesses. 4932810SN/A */ 4942810SN/A bool isBlocked() 4952810SN/A { 4962810SN/A return blocked != 0; 4972810SN/A } 4982810SN/A 4992810SN/A /** 5002810SN/A * Marks the access path of the cache as blocked for the given cause. This 5012810SN/A * also sets the blocked flag in the slave interface. 5022810SN/A * @param cause The reason for the cache blocking. 5032810SN/A */ 5042810SN/A void setBlocked(BlockedCause cause) 5052810SN/A { 5062810SN/A uint8_t flag = 1 << cause; 5072810SN/A if (blocked == 0) { 5082810SN/A blocked_causes[cause]++; 5097823Ssteve.reinhardt@amd.com blockedCycle = curTick(); 5104630SN/A cpuSidePort->setBlocked(); 5112810SN/A } 5124630SN/A blocked |= flag; 5134630SN/A DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 5142810SN/A } 5152810SN/A 5162810SN/A /** 5172810SN/A * Marks the cache as unblocked for the given cause. This also clears the 5182810SN/A * blocked flags in the appropriate interfaces. 5192810SN/A * @param cause The newly unblocked cause. 5202810SN/A * @warning Calling this function can cause a blocked request on the bus to 5212810SN/A * access the cache. The cache must be in a state to handle that request. 5222810SN/A */ 5232810SN/A void clearBlocked(BlockedCause cause) 5242810SN/A { 5252810SN/A uint8_t flag = 1 << cause; 5264630SN/A blocked &= ~flag; 5274630SN/A DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 5284630SN/A if (blocked == 0) { 5297823Ssteve.reinhardt@amd.com blocked_cycles[cause] += curTick() - blockedCycle; 5304630SN/A cpuSidePort->clearBlocked(); 5312810SN/A } 5322810SN/A } 5332810SN/A 5342810SN/A /** 5352810SN/A * Request the master bus for the given cause and time. 5362810SN/A * @param cause The reason for the request. 5372810SN/A * @param time The time to make the request. 5382810SN/A */ 5394458SN/A void requestMemSideBus(RequestCause cause, Tick time) 5402810SN/A { 5414458SN/A memSidePort->requestBus(cause, time); 5422810SN/A } 5432810SN/A 5442810SN/A /** 5452810SN/A * Clear the master bus request for the given cause. 5462810SN/A * @param cause The request reason to clear. 5472810SN/A */ 5484458SN/A void deassertMemSideBusRequest(RequestCause cause) 5492810SN/A { 5505875Ssteve.reinhardt@amd.com // Obsolete... we no longer signal bus requests explicitly so 5515875Ssteve.reinhardt@amd.com // we can't deassert them. Leaving this in as a no-op since 5525875Ssteve.reinhardt@amd.com // the prefetcher calls it to indicate that it no longer wants 5535875Ssteve.reinhardt@amd.com // to request a prefetch, and someday that might be 5545875Ssteve.reinhardt@amd.com // interesting again. 5552811SN/A } 5563503SN/A 5573503SN/A virtual unsigned int drain(Event *de); 5583503SN/A 5594626SN/A virtual bool inCache(Addr addr) = 0; 5604626SN/A 5614626SN/A virtual bool inMissQueue(Addr addr) = 0; 5624626SN/A 5638833Sdam.sunwoo@arm.com void incMissCount(PacketPtr pkt) 5643503SN/A { 5658833Sdam.sunwoo@arm.com assert(pkt->req->masterId() < system->maxMasters()); 5668833Sdam.sunwoo@arm.com misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 5674626SN/A 5684626SN/A if (missCount) { 5694626SN/A --missCount; 5704626SN/A if (missCount == 0) 5714626SN/A exitSimLoop("A cache reached the maximum miss count"); 5723503SN/A } 5733503SN/A } 5748833Sdam.sunwoo@arm.com void incHitCount(PacketPtr pkt) 5756978SLisa.Hsu@amd.com { 5768833Sdam.sunwoo@arm.com assert(pkt->req->masterId() < system->maxMasters()); 5778833Sdam.sunwoo@arm.com hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 5786978SLisa.Hsu@amd.com 5796978SLisa.Hsu@amd.com } 5803503SN/A 5812810SN/A}; 5822810SN/A 5832810SN/A#endif //__BASE_CACHE_HH__ 584