base.hh revision 5529
12810SN/A/* 22810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use in source and binary forms, with or without 62810SN/A * modification, are permitted provided that the following conditions are 72810SN/A * met: redistributions of source code must retain the above copyright 82810SN/A * notice, this list of conditions and the following disclaimer; 92810SN/A * redistributions in binary form must reproduce the above copyright 102810SN/A * notice, this list of conditions and the following disclaimer in the 112810SN/A * documentation and/or other materials provided with the distribution; 122810SN/A * neither the name of the copyright holders nor the names of its 132810SN/A * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Erik Hallnor 294458SN/A * Steve Reinhardt 304458SN/A * Ron Dreslinski 312810SN/A */ 322810SN/A 332810SN/A/** 342810SN/A * @file 352810SN/A * Declares a basic cache interface BaseCache. 362810SN/A */ 372810SN/A 382810SN/A#ifndef __BASE_CACHE_HH__ 392810SN/A#define __BASE_CACHE_HH__ 402810SN/A 412810SN/A#include <vector> 422810SN/A#include <string> 432810SN/A#include <list> 444666SN/A#include <algorithm> 452810SN/A#include <inttypes.h> 462810SN/A 472825SN/A#include "base/misc.hh" 482810SN/A#include "base/statistics.hh" 492810SN/A#include "base/trace.hh" 505338Sstever@gmail.com#include "mem/cache/mshr_queue.hh" 512810SN/A#include "mem/mem_object.hh" 522810SN/A#include "mem/packet.hh" 534626SN/A#include "mem/tport.hh" 542810SN/A#include "mem/request.hh" 555034SN/A#include "params/BaseCache.hh" 562811SN/A#include "sim/eventq.hh" 574626SN/A#include "sim/sim_exit.hh" 582810SN/A 593194SN/Aclass MSHR; 602810SN/A/** 612810SN/A * A basic cache interface. Implements some common functions for speed. 622810SN/A */ 632810SN/Aclass BaseCache : public MemObject 642810SN/A{ 654628SN/A /** 664628SN/A * Indexes to enumerate the MSHR queues. 674628SN/A */ 684628SN/A enum MSHRQueueIndex { 694628SN/A MSHRQueue_MSHRs, 704628SN/A MSHRQueue_WriteBuffer 714628SN/A }; 724628SN/A 734628SN/A /** 744628SN/A * Reasons for caches to be blocked. 754628SN/A */ 764628SN/A enum BlockedCause { 774628SN/A Blocked_NoMSHRs = MSHRQueue_MSHRs, 784628SN/A Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 794628SN/A Blocked_NoTargets, 804628SN/A NUM_BLOCKED_CAUSES 814628SN/A }; 824628SN/A 834628SN/A public: 844628SN/A /** 854628SN/A * Reasons for cache to request a bus. 864628SN/A */ 874628SN/A enum RequestCause { 884628SN/A Request_MSHR = MSHRQueue_MSHRs, 894628SN/A Request_WB = MSHRQueue_WriteBuffer, 904628SN/A Request_PF, 914628SN/A NUM_REQUEST_CAUSES 924628SN/A }; 934628SN/A 944628SN/A private: 954628SN/A 964626SN/A class CachePort : public SimpleTimingPort 972810SN/A { 982844SN/A public: 992810SN/A BaseCache *cache; 1002810SN/A 1013738SN/A protected: 1024965SN/A CachePort(const std::string &_name, BaseCache *_cache, 1035314SN/A const std::string &_label, 1045314SN/A std::vector<Range<Addr> > filter_ranges); 1054458SN/A 1062810SN/A virtual void recvStatusChange(Status status); 1072810SN/A 1082810SN/A virtual int deviceBlockSize(); 1092810SN/A 1104458SN/A bool recvRetryCommon(); 1113013SN/A 1124666SN/A typedef EventWrapper<Port, &Port::sendRetry> 1134666SN/A SendRetryEvent; 1144666SN/A 1155314SN/A const std::string label; 1165314SN/A 1172811SN/A public: 1184458SN/A void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; } 1194458SN/A 1202810SN/A void setBlocked(); 1212810SN/A 1222810SN/A void clearBlocked(); 1232810SN/A 1245314SN/A bool checkFunctional(PacketPtr pkt); 1253606SN/A 1264458SN/A CachePort *otherPort; 1274458SN/A 1282810SN/A bool blocked; 1292810SN/A 1302897SN/A bool mustSendRetry; 1312897SN/A 1324965SN/A /** filter ranges */ 1334965SN/A std::vector<Range<Addr> > filterRanges; 1344965SN/A 1354458SN/A void requestBus(RequestCause cause, Tick time) 1364458SN/A { 1374888SN/A DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 1384666SN/A if (!waitingOnRetry) { 1394666SN/A schedSendEvent(time); 1404458SN/A } 1414458SN/A } 1424458SN/A 1434626SN/A void respond(PacketPtr pkt, Tick time) { 1444626SN/A schedSendTiming(pkt, time); 1454626SN/A } 1462811SN/A }; 1472810SN/A 1483338SN/A public: //Made public so coherence can get at it. 1493338SN/A CachePort *cpuSidePort; 1503738SN/A CachePort *memSidePort; 1513338SN/A 1524626SN/A protected: 1534626SN/A 1544626SN/A /** Miss status registers */ 1554626SN/A MSHRQueue mshrQueue; 1564626SN/A 1574626SN/A /** Write/writeback buffer */ 1584626SN/A MSHRQueue writeBuffer; 1594626SN/A 1604628SN/A MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 1614628SN/A PacketPtr pkt, Tick time, bool requestBus) 1624628SN/A { 1634666SN/A MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 1644628SN/A 1654628SN/A if (mq->isFull()) { 1664628SN/A setBlocked((BlockedCause)mq->index); 1674628SN/A } 1684628SN/A 1694628SN/A if (requestBus) { 1704628SN/A requestMemSideBus((RequestCause)mq->index, time); 1714628SN/A } 1724628SN/A 1734628SN/A return mshr; 1744628SN/A } 1754628SN/A 1764628SN/A void markInServiceInternal(MSHR *mshr) 1774628SN/A { 1784628SN/A MSHRQueue *mq = mshr->queue; 1794628SN/A bool wasFull = mq->isFull(); 1804628SN/A mq->markInService(mshr); 1814628SN/A if (wasFull && !mq->isFull()) { 1824628SN/A clearBlocked((BlockedCause)mq->index); 1834628SN/A } 1844628SN/A } 1854628SN/A 1864626SN/A /** Block size of this cache */ 1874626SN/A const int blkSize; 1884626SN/A 1894630SN/A /** 1904630SN/A * The latency of a hit in this device. 1914630SN/A */ 1924630SN/A int hitLatency; 1934630SN/A 1944626SN/A /** The number of targets for each MSHR. */ 1954626SN/A const int numTarget; 1964626SN/A 1974626SN/A /** Increasing order number assigned to each incoming request. */ 1984626SN/A uint64_t order; 1994626SN/A 2002810SN/A /** 2012810SN/A * Bit vector of the blocking reasons for the access path. 2022810SN/A * @sa #BlockedCause 2032810SN/A */ 2042810SN/A uint8_t blocked; 2052810SN/A 2062810SN/A /** Stores time the cache blocked for statistics. */ 2072810SN/A Tick blockedCycle; 2082810SN/A 2094626SN/A /** Pointer to the MSHR that has no targets. */ 2104626SN/A MSHR *noTargetMSHR; 2112810SN/A 2122810SN/A /** The number of misses to trigger an exit event. */ 2132810SN/A Counter missCount; 2142810SN/A 2153503SN/A /** The drain event. */ 2163503SN/A Event *drainEvent; 2173503SN/A 2182810SN/A public: 2192810SN/A // Statistics 2202810SN/A /** 2212810SN/A * @addtogroup CacheStatistics 2222810SN/A * @{ 2232810SN/A */ 2242810SN/A 2252810SN/A /** Number of hits per thread for each type of command. @sa Packet::Command */ 2264022SN/A Stats::Vector<> hits[MemCmd::NUM_MEM_CMDS]; 2272810SN/A /** Number of hits for demand accesses. */ 2282810SN/A Stats::Formula demandHits; 2292810SN/A /** Number of hit for all accesses. */ 2302810SN/A Stats::Formula overallHits; 2312810SN/A 2322810SN/A /** Number of misses per thread for each type of command. @sa Packet::Command */ 2334022SN/A Stats::Vector<> misses[MemCmd::NUM_MEM_CMDS]; 2342810SN/A /** Number of misses for demand accesses. */ 2352810SN/A Stats::Formula demandMisses; 2362810SN/A /** Number of misses for all accesses. */ 2372810SN/A Stats::Formula overallMisses; 2382810SN/A 2392810SN/A /** 2402810SN/A * Total number of cycles per thread/command spent waiting for a miss. 2412810SN/A * Used to calculate the average miss latency. 2422810SN/A */ 2434022SN/A Stats::Vector<> missLatency[MemCmd::NUM_MEM_CMDS]; 2442810SN/A /** Total number of cycles spent waiting for demand misses. */ 2452810SN/A Stats::Formula demandMissLatency; 2462810SN/A /** Total number of cycles spent waiting for all misses. */ 2472810SN/A Stats::Formula overallMissLatency; 2482810SN/A 2492810SN/A /** The number of accesses per command and thread. */ 2504022SN/A Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 2512810SN/A /** The number of demand accesses. */ 2522810SN/A Stats::Formula demandAccesses; 2532810SN/A /** The number of overall accesses. */ 2542810SN/A Stats::Formula overallAccesses; 2552810SN/A 2562810SN/A /** The miss rate per command and thread. */ 2574022SN/A Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 2582810SN/A /** The miss rate of all demand accesses. */ 2592810SN/A Stats::Formula demandMissRate; 2602810SN/A /** The miss rate for all accesses. */ 2612810SN/A Stats::Formula overallMissRate; 2622810SN/A 2632810SN/A /** The average miss latency per command and thread. */ 2644022SN/A Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 2652810SN/A /** The average miss latency for demand misses. */ 2662810SN/A Stats::Formula demandAvgMissLatency; 2672810SN/A /** The average miss latency for all misses. */ 2682810SN/A Stats::Formula overallAvgMissLatency; 2692810SN/A 2702810SN/A /** The total number of cycles blocked for each blocked cause. */ 2712810SN/A Stats::Vector<> blocked_cycles; 2722810SN/A /** The number of times this cache blocked for each blocked cause. */ 2732810SN/A Stats::Vector<> blocked_causes; 2742810SN/A 2752810SN/A /** The average number of cycles blocked for each blocked cause. */ 2762810SN/A Stats::Formula avg_blocked; 2772810SN/A 2782810SN/A /** The number of fast writes (WH64) performed. */ 2792810SN/A Stats::Scalar<> fastWrites; 2802810SN/A 2812810SN/A /** The number of cache copies performed. */ 2822810SN/A Stats::Scalar<> cacheCopies; 2832810SN/A 2844626SN/A /** Number of blocks written back per thread. */ 2854626SN/A Stats::Vector<> writebacks; 2864626SN/A 2874626SN/A /** Number of misses that hit in the MSHRs per command and thread. */ 2884626SN/A Stats::Vector<> mshr_hits[MemCmd::NUM_MEM_CMDS]; 2894626SN/A /** Demand misses that hit in the MSHRs. */ 2904626SN/A Stats::Formula demandMshrHits; 2914626SN/A /** Total number of misses that hit in the MSHRs. */ 2924626SN/A Stats::Formula overallMshrHits; 2934626SN/A 2944626SN/A /** Number of misses that miss in the MSHRs, per command and thread. */ 2954626SN/A Stats::Vector<> mshr_misses[MemCmd::NUM_MEM_CMDS]; 2964626SN/A /** Demand misses that miss in the MSHRs. */ 2974626SN/A Stats::Formula demandMshrMisses; 2984626SN/A /** Total number of misses that miss in the MSHRs. */ 2994626SN/A Stats::Formula overallMshrMisses; 3004626SN/A 3014626SN/A /** Number of misses that miss in the MSHRs, per command and thread. */ 3024626SN/A Stats::Vector<> mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 3034626SN/A /** Total number of misses that miss in the MSHRs. */ 3044626SN/A Stats::Formula overallMshrUncacheable; 3054626SN/A 3064626SN/A /** Total cycle latency of each MSHR miss, per command and thread. */ 3074626SN/A Stats::Vector<> mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 3084626SN/A /** Total cycle latency of demand MSHR misses. */ 3094626SN/A Stats::Formula demandMshrMissLatency; 3104626SN/A /** Total cycle latency of overall MSHR misses. */ 3114626SN/A Stats::Formula overallMshrMissLatency; 3124626SN/A 3134626SN/A /** Total cycle latency of each MSHR miss, per command and thread. */ 3144626SN/A Stats::Vector<> mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 3154626SN/A /** Total cycle latency of overall MSHR misses. */ 3164626SN/A Stats::Formula overallMshrUncacheableLatency; 3174626SN/A 3184626SN/A /** The total number of MSHR accesses per command and thread. */ 3194626SN/A Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 3204626SN/A /** The total number of demand MSHR accesses. */ 3214626SN/A Stats::Formula demandMshrAccesses; 3224626SN/A /** The total number of MSHR accesses. */ 3234626SN/A Stats::Formula overallMshrAccesses; 3244626SN/A 3254626SN/A /** The miss rate in the MSHRs pre command and thread. */ 3264626SN/A Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 3274626SN/A /** The demand miss rate in the MSHRs. */ 3284626SN/A Stats::Formula demandMshrMissRate; 3294626SN/A /** The overall miss rate in the MSHRs. */ 3304626SN/A Stats::Formula overallMshrMissRate; 3314626SN/A 3324626SN/A /** The average latency of an MSHR miss, per command and thread. */ 3334626SN/A Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 3344626SN/A /** The average latency of a demand MSHR miss. */ 3354626SN/A Stats::Formula demandAvgMshrMissLatency; 3364626SN/A /** The average overall latency of an MSHR miss. */ 3374626SN/A Stats::Formula overallAvgMshrMissLatency; 3384626SN/A 3394626SN/A /** The average latency of an MSHR miss, per command and thread. */ 3404626SN/A Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 3414626SN/A /** The average overall latency of an MSHR miss. */ 3424626SN/A Stats::Formula overallAvgMshrUncacheableLatency; 3434626SN/A 3444626SN/A /** The number of times a thread hit its MSHR cap. */ 3454626SN/A Stats::Vector<> mshr_cap_events; 3464626SN/A /** The number of times software prefetches caused the MSHR to block. */ 3474626SN/A Stats::Vector<> soft_prefetch_mshr_full; 3484626SN/A 3494626SN/A Stats::Scalar<> mshr_no_allocate_misses; 3504626SN/A 3512810SN/A /** 3522810SN/A * @} 3532810SN/A */ 3542810SN/A 3552810SN/A /** 3562810SN/A * Register stats for this object. 3572810SN/A */ 3582810SN/A virtual void regStats(); 3592810SN/A 3602810SN/A public: 3615034SN/A typedef BaseCacheParams Params; 3625034SN/A BaseCache(const Params *p); 3635034SN/A ~BaseCache() {} 3643606SN/A 3652858SN/A virtual void init(); 3662858SN/A 3672810SN/A /** 3682810SN/A * Query block size of a cache. 3692810SN/A * @return The block size 3702810SN/A */ 3712810SN/A int getBlockSize() const 3722810SN/A { 3732810SN/A return blkSize; 3742810SN/A } 3752810SN/A 3764626SN/A 3774626SN/A Addr blockAlign(Addr addr) const { return (addr & ~(blkSize - 1)); } 3784626SN/A 3794626SN/A 3804628SN/A MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 3814628SN/A { 3824902SN/A assert(!pkt->req->isUncacheable()); 3834628SN/A return allocateBufferInternal(&mshrQueue, 3844628SN/A blockAlign(pkt->getAddr()), blkSize, 3854628SN/A pkt, time, requestBus); 3864628SN/A } 3874628SN/A 3884902SN/A MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 3894628SN/A { 3904902SN/A assert(pkt->isWrite() && !pkt->isRead()); 3914902SN/A return allocateBufferInternal(&writeBuffer, 3924902SN/A pkt->getAddr(), pkt->getSize(), 3934628SN/A pkt, time, requestBus); 3944628SN/A } 3954628SN/A 3964902SN/A MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus) 3974902SN/A { 3984902SN/A assert(pkt->req->isUncacheable()); 3994902SN/A assert(pkt->isRead()); 4004902SN/A return allocateBufferInternal(&mshrQueue, 4014902SN/A pkt->getAddr(), pkt->getSize(), 4024902SN/A pkt, time, requestBus); 4034902SN/A } 4044628SN/A 4052810SN/A /** 4062810SN/A * Returns true if the cache is blocked for accesses. 4072810SN/A */ 4082810SN/A bool isBlocked() 4092810SN/A { 4102810SN/A return blocked != 0; 4112810SN/A } 4122810SN/A 4132810SN/A /** 4142810SN/A * Marks the access path of the cache as blocked for the given cause. This 4152810SN/A * also sets the blocked flag in the slave interface. 4162810SN/A * @param cause The reason for the cache blocking. 4172810SN/A */ 4182810SN/A void setBlocked(BlockedCause cause) 4192810SN/A { 4202810SN/A uint8_t flag = 1 << cause; 4212810SN/A if (blocked == 0) { 4222810SN/A blocked_causes[cause]++; 4232810SN/A blockedCycle = curTick; 4244630SN/A cpuSidePort->setBlocked(); 4252810SN/A } 4264630SN/A blocked |= flag; 4274630SN/A DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 4282810SN/A } 4292810SN/A 4302810SN/A /** 4312810SN/A * Marks the cache as unblocked for the given cause. This also clears the 4322810SN/A * blocked flags in the appropriate interfaces. 4332810SN/A * @param cause The newly unblocked cause. 4342810SN/A * @warning Calling this function can cause a blocked request on the bus to 4352810SN/A * access the cache. The cache must be in a state to handle that request. 4362810SN/A */ 4372810SN/A void clearBlocked(BlockedCause cause) 4382810SN/A { 4392810SN/A uint8_t flag = 1 << cause; 4404630SN/A blocked &= ~flag; 4414630SN/A DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 4424630SN/A if (blocked == 0) { 4434630SN/A blocked_cycles[cause] += curTick - blockedCycle; 4444630SN/A cpuSidePort->clearBlocked(); 4452810SN/A } 4462810SN/A } 4472810SN/A 4484871SN/A Tick nextMSHRReadyTime() 4492810SN/A { 4504871SN/A return std::min(mshrQueue.nextMSHRReadyTime(), 4514871SN/A writeBuffer.nextMSHRReadyTime()); 4522810SN/A } 4532810SN/A 4542810SN/A /** 4552810SN/A * Request the master bus for the given cause and time. 4562810SN/A * @param cause The reason for the request. 4572810SN/A * @param time The time to make the request. 4582810SN/A */ 4594458SN/A void requestMemSideBus(RequestCause cause, Tick time) 4602810SN/A { 4614458SN/A memSidePort->requestBus(cause, time); 4622810SN/A } 4632810SN/A 4642810SN/A /** 4652810SN/A * Clear the master bus request for the given cause. 4662810SN/A * @param cause The request reason to clear. 4672810SN/A */ 4684458SN/A void deassertMemSideBusRequest(RequestCause cause) 4692810SN/A { 4704666SN/A // obsolete!! 4714666SN/A assert(false); 4724666SN/A // memSidePort->deassertBusRequest(cause); 4734626SN/A // checkDrain(); 4742811SN/A } 4753503SN/A 4763503SN/A virtual unsigned int drain(Event *de); 4773503SN/A 4784626SN/A virtual bool inCache(Addr addr) = 0; 4794626SN/A 4804626SN/A virtual bool inMissQueue(Addr addr) = 0; 4814626SN/A 4824626SN/A void incMissCount(PacketPtr pkt) 4833503SN/A { 4844626SN/A misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; 4854626SN/A 4864626SN/A if (missCount) { 4874626SN/A --missCount; 4884626SN/A if (missCount == 0) 4894626SN/A exitSimLoop("A cache reached the maximum miss count"); 4903503SN/A } 4913503SN/A } 4923503SN/A 4932810SN/A}; 4942810SN/A 4952810SN/A#endif //__BASE_CACHE_HH__ 496