base.hh revision 12773
12810SN/A/* 212724Snikos.nikoleris@arm.com * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 414458SN/A * Steve Reinhardt 424458SN/A * Ron Dreslinski 4312724Snikos.nikoleris@arm.com * Andreas Hansson 4412724Snikos.nikoleris@arm.com * Nikos Nikoleris 452810SN/A */ 462810SN/A 472810SN/A/** 482810SN/A * @file 492810SN/A * Declares a basic cache interface BaseCache. 502810SN/A */ 512810SN/A 5211051Sandreas.hansson@arm.com#ifndef __MEM_CACHE_BASE_HH__ 5311051Sandreas.hansson@arm.com#define __MEM_CACHE_BASE_HH__ 542810SN/A 5512724Snikos.nikoleris@arm.com#include <cassert> 5612724Snikos.nikoleris@arm.com#include <cstdint> 577676Snate@binkert.org#include <string> 582810SN/A 5912724Snikos.nikoleris@arm.com#include "base/addr_range.hh" 602810SN/A#include "base/statistics.hh" 612810SN/A#include "base/trace.hh" 626215Snate@binkert.org#include "base/types.hh" 638232Snate@binkert.org#include "debug/Cache.hh" 648232Snate@binkert.org#include "debug/CachePort.hh" 6512724Snikos.nikoleris@arm.com#include "enums/Clusivity.hh" 6612724Snikos.nikoleris@arm.com#include "mem/cache/blk.hh" 675338Sstever@gmail.com#include "mem/cache/mshr_queue.hh" 6812724Snikos.nikoleris@arm.com#include "mem/cache/tags/base.hh" 6911375Sandreas.hansson@arm.com#include "mem/cache/write_queue.hh" 7012724Snikos.nikoleris@arm.com#include "mem/cache/write_queue_entry.hh" 712810SN/A#include "mem/mem_object.hh" 722810SN/A#include "mem/packet.hh" 7312724Snikos.nikoleris@arm.com#include "mem/packet_queue.hh" 748914Sandreas.hansson@arm.com#include "mem/qport.hh" 758229Snate@binkert.org#include "mem/request.hh" 762811SN/A#include "sim/eventq.hh" 7712724Snikos.nikoleris@arm.com#include "sim/serialize.hh" 784626SN/A#include "sim/sim_exit.hh" 798833Sdam.sunwoo@arm.com#include "sim/system.hh" 802810SN/A 8112724Snikos.nikoleris@arm.comclass BaseMasterPort; 8212724Snikos.nikoleris@arm.comclass BasePrefetcher; 8312724Snikos.nikoleris@arm.comclass BaseSlavePort; 8412724Snikos.nikoleris@arm.comclass MSHR; 8512724Snikos.nikoleris@arm.comclass MasterPort; 8612724Snikos.nikoleris@arm.comclass QueueEntry; 8712724Snikos.nikoleris@arm.comstruct BaseCacheParams; 8812724Snikos.nikoleris@arm.com 892810SN/A/** 902810SN/A * A basic cache interface. Implements some common functions for speed. 912810SN/A */ 922810SN/Aclass BaseCache : public MemObject 932810SN/A{ 9411375Sandreas.hansson@arm.com protected: 954628SN/A /** 964628SN/A * Indexes to enumerate the MSHR queues. 974628SN/A */ 984628SN/A enum MSHRQueueIndex { 994628SN/A MSHRQueue_MSHRs, 1004628SN/A MSHRQueue_WriteBuffer 1014628SN/A }; 1024628SN/A 1038737Skoansin.tan@gmail.com public: 1044628SN/A /** 1054628SN/A * Reasons for caches to be blocked. 1064628SN/A */ 1074628SN/A enum BlockedCause { 1084628SN/A Blocked_NoMSHRs = MSHRQueue_MSHRs, 1094628SN/A Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 1104628SN/A Blocked_NoTargets, 1114628SN/A NUM_BLOCKED_CAUSES 1124628SN/A }; 1134628SN/A 1148737Skoansin.tan@gmail.com protected: 1154628SN/A 1168856Sandreas.hansson@arm.com /** 1178856Sandreas.hansson@arm.com * A cache master port is used for the memory-side port of the 1188856Sandreas.hansson@arm.com * cache, and in addition to the basic timing port that only sends 1198856Sandreas.hansson@arm.com * response packets through a transmit list, it also offers the 1208856Sandreas.hansson@arm.com * ability to schedule and send request packets (requests & 12110942Sandreas.hansson@arm.com * writebacks). The send event is scheduled through schedSendEvent, 1228856Sandreas.hansson@arm.com * and the sendDeferredPacket of the timing port is modified to 1238856Sandreas.hansson@arm.com * consider both the transmit list and the requests from the MSHR. 1248856Sandreas.hansson@arm.com */ 1258922Swilliam.wang@arm.com class CacheMasterPort : public QueuedMasterPort 1262810SN/A { 1278856Sandreas.hansson@arm.com 1282844SN/A public: 1298856Sandreas.hansson@arm.com 1308856Sandreas.hansson@arm.com /** 1318856Sandreas.hansson@arm.com * Schedule a send of a request packet (from the MSHR). Note 13210713Sandreas.hansson@arm.com * that we could already have a retry outstanding. 1338856Sandreas.hansson@arm.com */ 13410942Sandreas.hansson@arm.com void schedSendEvent(Tick time) 1358856Sandreas.hansson@arm.com { 13610942Sandreas.hansson@arm.com DPRINTF(CachePort, "Scheduling send event at %llu\n", time); 13710713Sandreas.hansson@arm.com reqQueue.schedSendEvent(time); 1388856Sandreas.hansson@arm.com } 1398856Sandreas.hansson@arm.com 1403738SN/A protected: 1414458SN/A 1428856Sandreas.hansson@arm.com CacheMasterPort(const std::string &_name, BaseCache *_cache, 14310713Sandreas.hansson@arm.com ReqPacketQueue &_reqQueue, 14410713Sandreas.hansson@arm.com SnoopRespPacketQueue &_snoopRespQueue) : 14510713Sandreas.hansson@arm.com QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue) 1468914Sandreas.hansson@arm.com { } 1472810SN/A 1488856Sandreas.hansson@arm.com /** 1498856Sandreas.hansson@arm.com * Memory-side port always snoops. 1508856Sandreas.hansson@arm.com * 1518914Sandreas.hansson@arm.com * @return always true 1528856Sandreas.hansson@arm.com */ 1538922Swilliam.wang@arm.com virtual bool isSnooping() const { return true; } 1548856Sandreas.hansson@arm.com }; 1553013SN/A 1568856Sandreas.hansson@arm.com /** 15712724Snikos.nikoleris@arm.com * Override the default behaviour of sendDeferredPacket to enable 15812724Snikos.nikoleris@arm.com * the memory-side cache port to also send requests based on the 15912724Snikos.nikoleris@arm.com * current MSHR status. This queue has a pointer to our specific 16012724Snikos.nikoleris@arm.com * cache implementation and is used by the MemSidePort. 16112724Snikos.nikoleris@arm.com */ 16212724Snikos.nikoleris@arm.com class CacheReqPacketQueue : public ReqPacketQueue 16312724Snikos.nikoleris@arm.com { 16412724Snikos.nikoleris@arm.com 16512724Snikos.nikoleris@arm.com protected: 16612724Snikos.nikoleris@arm.com 16712724Snikos.nikoleris@arm.com BaseCache &cache; 16812724Snikos.nikoleris@arm.com SnoopRespPacketQueue &snoopRespQueue; 16912724Snikos.nikoleris@arm.com 17012724Snikos.nikoleris@arm.com public: 17112724Snikos.nikoleris@arm.com 17212724Snikos.nikoleris@arm.com CacheReqPacketQueue(BaseCache &cache, MasterPort &port, 17312724Snikos.nikoleris@arm.com SnoopRespPacketQueue &snoop_resp_queue, 17412724Snikos.nikoleris@arm.com const std::string &label) : 17512724Snikos.nikoleris@arm.com ReqPacketQueue(cache, port, label), cache(cache), 17612724Snikos.nikoleris@arm.com snoopRespQueue(snoop_resp_queue) { } 17712724Snikos.nikoleris@arm.com 17812724Snikos.nikoleris@arm.com /** 17912724Snikos.nikoleris@arm.com * Override the normal sendDeferredPacket and do not only 18012724Snikos.nikoleris@arm.com * consider the transmit list (used for responses), but also 18112724Snikos.nikoleris@arm.com * requests. 18212724Snikos.nikoleris@arm.com */ 18312724Snikos.nikoleris@arm.com virtual void sendDeferredPacket(); 18412724Snikos.nikoleris@arm.com 18512724Snikos.nikoleris@arm.com /** 18612724Snikos.nikoleris@arm.com * Check if there is a conflicting snoop response about to be 18712724Snikos.nikoleris@arm.com * send out, and if so simply stall any requests, and schedule 18812724Snikos.nikoleris@arm.com * a send event at the same time as the next snoop response is 18912724Snikos.nikoleris@arm.com * being sent out. 19012724Snikos.nikoleris@arm.com */ 19112724Snikos.nikoleris@arm.com bool checkConflictingSnoop(Addr addr) 19212724Snikos.nikoleris@arm.com { 19312724Snikos.nikoleris@arm.com if (snoopRespQueue.hasAddr(addr)) { 19412724Snikos.nikoleris@arm.com DPRINTF(CachePort, "Waiting for snoop response to be " 19512724Snikos.nikoleris@arm.com "sent\n"); 19612724Snikos.nikoleris@arm.com Tick when = snoopRespQueue.deferredPacketReadyTime(); 19712724Snikos.nikoleris@arm.com schedSendEvent(when); 19812724Snikos.nikoleris@arm.com return true; 19912724Snikos.nikoleris@arm.com } 20012724Snikos.nikoleris@arm.com return false; 20112724Snikos.nikoleris@arm.com } 20212724Snikos.nikoleris@arm.com }; 20312724Snikos.nikoleris@arm.com 20412724Snikos.nikoleris@arm.com 20512724Snikos.nikoleris@arm.com /** 20612724Snikos.nikoleris@arm.com * The memory-side port extends the base cache master port with 20712724Snikos.nikoleris@arm.com * access functions for functional, atomic and timing snoops. 20812724Snikos.nikoleris@arm.com */ 20912724Snikos.nikoleris@arm.com class MemSidePort : public CacheMasterPort 21012724Snikos.nikoleris@arm.com { 21112724Snikos.nikoleris@arm.com private: 21212724Snikos.nikoleris@arm.com 21312724Snikos.nikoleris@arm.com /** The cache-specific queue. */ 21412724Snikos.nikoleris@arm.com CacheReqPacketQueue _reqQueue; 21512724Snikos.nikoleris@arm.com 21612724Snikos.nikoleris@arm.com SnoopRespPacketQueue _snoopRespQueue; 21712724Snikos.nikoleris@arm.com 21812724Snikos.nikoleris@arm.com // a pointer to our specific cache implementation 21912724Snikos.nikoleris@arm.com BaseCache *cache; 22012724Snikos.nikoleris@arm.com 22112724Snikos.nikoleris@arm.com protected: 22212724Snikos.nikoleris@arm.com 22312724Snikos.nikoleris@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt); 22412724Snikos.nikoleris@arm.com 22512724Snikos.nikoleris@arm.com virtual bool recvTimingResp(PacketPtr pkt); 22612724Snikos.nikoleris@arm.com 22712724Snikos.nikoleris@arm.com virtual Tick recvAtomicSnoop(PacketPtr pkt); 22812724Snikos.nikoleris@arm.com 22912724Snikos.nikoleris@arm.com virtual void recvFunctionalSnoop(PacketPtr pkt); 23012724Snikos.nikoleris@arm.com 23112724Snikos.nikoleris@arm.com public: 23212724Snikos.nikoleris@arm.com 23312724Snikos.nikoleris@arm.com MemSidePort(const std::string &_name, BaseCache *_cache, 23412724Snikos.nikoleris@arm.com const std::string &_label); 23512724Snikos.nikoleris@arm.com }; 23612724Snikos.nikoleris@arm.com 23712724Snikos.nikoleris@arm.com /** 2388856Sandreas.hansson@arm.com * A cache slave port is used for the CPU-side port of the cache, 2398856Sandreas.hansson@arm.com * and it is basically a simple timing port that uses a transmit 2408856Sandreas.hansson@arm.com * list for responses to the CPU (or connected master). In 2418856Sandreas.hansson@arm.com * addition, it has the functionality to block the port for 2428856Sandreas.hansson@arm.com * incoming requests. If blocked, the port will issue a retry once 2438856Sandreas.hansson@arm.com * unblocked. 2448856Sandreas.hansson@arm.com */ 2458922Swilliam.wang@arm.com class CacheSlavePort : public QueuedSlavePort 2468856Sandreas.hansson@arm.com { 2475314SN/A 2482811SN/A public: 2498856Sandreas.hansson@arm.com 2508856Sandreas.hansson@arm.com /** Do not accept any new requests. */ 2512810SN/A void setBlocked(); 2522810SN/A 2538856Sandreas.hansson@arm.com /** Return to normal operation and accept new requests. */ 2542810SN/A void clearBlocked(); 2552810SN/A 25610345SCurtis.Dunham@arm.com bool isBlocked() const { return blocked; } 25710345SCurtis.Dunham@arm.com 2588856Sandreas.hansson@arm.com protected: 2598856Sandreas.hansson@arm.com 2608856Sandreas.hansson@arm.com CacheSlavePort(const std::string &_name, BaseCache *_cache, 2618856Sandreas.hansson@arm.com const std::string &_label); 2623606SN/A 2638914Sandreas.hansson@arm.com /** A normal packet queue used to store responses. */ 26410713Sandreas.hansson@arm.com RespPacketQueue queue; 2658914Sandreas.hansson@arm.com 2662810SN/A bool blocked; 2672810SN/A 2682897SN/A bool mustSendRetry; 2692897SN/A 2708856Sandreas.hansson@arm.com private: 2714458SN/A 27210344Sandreas.hansson@arm.com void processSendRetry(); 27310344Sandreas.hansson@arm.com 27412084Sspwilson2@wisc.edu EventFunctionWrapper sendRetryEvent; 2758856Sandreas.hansson@arm.com 2762811SN/A }; 2772810SN/A 27812724Snikos.nikoleris@arm.com /** 27912724Snikos.nikoleris@arm.com * The CPU-side port extends the base cache slave port with access 28012724Snikos.nikoleris@arm.com * functions for functional, atomic and timing requests. 28112724Snikos.nikoleris@arm.com */ 28212724Snikos.nikoleris@arm.com class CpuSidePort : public CacheSlavePort 28312724Snikos.nikoleris@arm.com { 28412724Snikos.nikoleris@arm.com private: 28512724Snikos.nikoleris@arm.com 28612724Snikos.nikoleris@arm.com // a pointer to our specific cache implementation 28712724Snikos.nikoleris@arm.com BaseCache *cache; 28812724Snikos.nikoleris@arm.com 28912724Snikos.nikoleris@arm.com protected: 29012724Snikos.nikoleris@arm.com virtual bool recvTimingSnoopResp(PacketPtr pkt) override; 29112724Snikos.nikoleris@arm.com 29212724Snikos.nikoleris@arm.com virtual bool tryTiming(PacketPtr pkt) override; 29312724Snikos.nikoleris@arm.com 29412724Snikos.nikoleris@arm.com virtual bool recvTimingReq(PacketPtr pkt) override; 29512724Snikos.nikoleris@arm.com 29612724Snikos.nikoleris@arm.com virtual Tick recvAtomic(PacketPtr pkt) override; 29712724Snikos.nikoleris@arm.com 29812724Snikos.nikoleris@arm.com virtual void recvFunctional(PacketPtr pkt) override; 29912724Snikos.nikoleris@arm.com 30012724Snikos.nikoleris@arm.com virtual AddrRangeList getAddrRanges() const override; 30112724Snikos.nikoleris@arm.com 30212724Snikos.nikoleris@arm.com public: 30312724Snikos.nikoleris@arm.com 30412724Snikos.nikoleris@arm.com CpuSidePort(const std::string &_name, BaseCache *_cache, 30512724Snikos.nikoleris@arm.com const std::string &_label); 30612724Snikos.nikoleris@arm.com 30712724Snikos.nikoleris@arm.com }; 30812724Snikos.nikoleris@arm.com 30912724Snikos.nikoleris@arm.com CpuSidePort cpuSidePort; 31012724Snikos.nikoleris@arm.com MemSidePort memSidePort; 3113338SN/A 3124626SN/A protected: 3134626SN/A 3144626SN/A /** Miss status registers */ 3154626SN/A MSHRQueue mshrQueue; 3164626SN/A 3174626SN/A /** Write/writeback buffer */ 31811375Sandreas.hansson@arm.com WriteQueue writeBuffer; 3194626SN/A 32012724Snikos.nikoleris@arm.com /** Tag and data Storage */ 32112724Snikos.nikoleris@arm.com BaseTags *tags; 32212724Snikos.nikoleris@arm.com 32312724Snikos.nikoleris@arm.com /** Prefetcher */ 32412724Snikos.nikoleris@arm.com BasePrefetcher *prefetcher; 32512724Snikos.nikoleris@arm.com 32612724Snikos.nikoleris@arm.com /** 32712724Snikos.nikoleris@arm.com * Notify the prefetcher on every access, not just misses. 32812724Snikos.nikoleris@arm.com */ 32912724Snikos.nikoleris@arm.com const bool prefetchOnAccess; 33012724Snikos.nikoleris@arm.com 33112724Snikos.nikoleris@arm.com /** 33212724Snikos.nikoleris@arm.com * Temporary cache block for occasional transitory use. We use 33312724Snikos.nikoleris@arm.com * the tempBlock to fill when allocation fails (e.g., when there 33412724Snikos.nikoleris@arm.com * is an outstanding request that accesses the victim block) or 33512724Snikos.nikoleris@arm.com * when we want to avoid allocation (e.g., exclusive caches) 33612724Snikos.nikoleris@arm.com */ 33712730Sodanrc@yahoo.com.br TempCacheBlk *tempBlock; 33812724Snikos.nikoleris@arm.com 33912724Snikos.nikoleris@arm.com /** 34012724Snikos.nikoleris@arm.com * Upstream caches need this packet until true is returned, so 34112724Snikos.nikoleris@arm.com * hold it for deletion until a subsequent call 34212724Snikos.nikoleris@arm.com */ 34312724Snikos.nikoleris@arm.com std::unique_ptr<Packet> pendingDelete; 34412724Snikos.nikoleris@arm.com 34510693SMarco.Balboni@ARM.com /** 34611375Sandreas.hansson@arm.com * Mark a request as in service (sent downstream in the memory 34711375Sandreas.hansson@arm.com * system), effectively making this MSHR the ordering point. 34810693SMarco.Balboni@ARM.com */ 34911375Sandreas.hansson@arm.com void markInService(MSHR *mshr, bool pending_modified_resp) 3504628SN/A { 35111375Sandreas.hansson@arm.com bool wasFull = mshrQueue.isFull(); 35211375Sandreas.hansson@arm.com mshrQueue.markInService(mshr, pending_modified_resp); 35310764Sandreas.hansson@arm.com 35411375Sandreas.hansson@arm.com if (wasFull && !mshrQueue.isFull()) { 35511375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 3564628SN/A } 3574628SN/A } 3584628SN/A 35911375Sandreas.hansson@arm.com void markInService(WriteQueueEntry *entry) 3604628SN/A { 36111375Sandreas.hansson@arm.com bool wasFull = writeBuffer.isFull(); 36211375Sandreas.hansson@arm.com writeBuffer.markInService(entry); 36311375Sandreas.hansson@arm.com 36411375Sandreas.hansson@arm.com if (wasFull && !writeBuffer.isFull()) { 36511375Sandreas.hansson@arm.com clearBlocked(Blocked_NoWBBuffers); 3664628SN/A } 3674628SN/A } 3684628SN/A 3699347SAndreas.Sandberg@arm.com /** 37012724Snikos.nikoleris@arm.com * Determine whether we should allocate on a fill or not. If this 37112724Snikos.nikoleris@arm.com * cache is mostly inclusive with regards to the upstream cache(s) 37212724Snikos.nikoleris@arm.com * we always allocate (for any non-forwarded and cacheable 37312724Snikos.nikoleris@arm.com * requests). In the case of a mostly exclusive cache, we allocate 37412724Snikos.nikoleris@arm.com * on fill if the packet did not come from a cache, thus if we: 37512724Snikos.nikoleris@arm.com * are dealing with a whole-line write (the latter behaves much 37612724Snikos.nikoleris@arm.com * like a writeback), the original target packet came from a 37712724Snikos.nikoleris@arm.com * non-caching source, or if we are performing a prefetch or LLSC. 37811197Sandreas.hansson@arm.com * 37912724Snikos.nikoleris@arm.com * @param cmd Command of the incoming requesting packet 38012724Snikos.nikoleris@arm.com * @return Whether we should allocate on the fill 38112724Snikos.nikoleris@arm.com */ 38212724Snikos.nikoleris@arm.com inline bool allocOnFill(MemCmd cmd) const 38312724Snikos.nikoleris@arm.com { 38412724Snikos.nikoleris@arm.com return clusivity == Enums::mostly_incl || 38512724Snikos.nikoleris@arm.com cmd == MemCmd::WriteLineReq || 38612724Snikos.nikoleris@arm.com cmd == MemCmd::ReadReq || 38712724Snikos.nikoleris@arm.com cmd == MemCmd::WriteReq || 38812724Snikos.nikoleris@arm.com cmd.isPrefetch() || 38912724Snikos.nikoleris@arm.com cmd.isLLSC(); 39012724Snikos.nikoleris@arm.com } 39112724Snikos.nikoleris@arm.com 39212724Snikos.nikoleris@arm.com /** 39312730Sodanrc@yahoo.com.br * Regenerate block address using tags. 39412730Sodanrc@yahoo.com.br * Block address regeneration depends on whether we're using a temporary 39512730Sodanrc@yahoo.com.br * block or not. 39612730Sodanrc@yahoo.com.br * 39712730Sodanrc@yahoo.com.br * @param blk The block to regenerate address. 39812730Sodanrc@yahoo.com.br * @return The block's address. 39912730Sodanrc@yahoo.com.br */ 40012730Sodanrc@yahoo.com.br Addr regenerateBlkAddr(CacheBlk* blk); 40112730Sodanrc@yahoo.com.br 40212730Sodanrc@yahoo.com.br /** 40312724Snikos.nikoleris@arm.com * Does all the processing necessary to perform the provided request. 40412724Snikos.nikoleris@arm.com * @param pkt The memory request to perform. 40512724Snikos.nikoleris@arm.com * @param blk The cache block to be updated. 40612724Snikos.nikoleris@arm.com * @param lat The latency of the access. 40712724Snikos.nikoleris@arm.com * @param writebacks List for any writebacks that need to be performed. 40812724Snikos.nikoleris@arm.com * @return Boolean indicating whether the request was satisfied. 40912724Snikos.nikoleris@arm.com */ 41012724Snikos.nikoleris@arm.com virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 41112724Snikos.nikoleris@arm.com PacketList &writebacks); 41212724Snikos.nikoleris@arm.com 41312724Snikos.nikoleris@arm.com /* 41412724Snikos.nikoleris@arm.com * Handle a timing request that hit in the cache 41511197Sandreas.hansson@arm.com * 41612724Snikos.nikoleris@arm.com * @param ptk The request packet 41712724Snikos.nikoleris@arm.com * @param blk The referenced block 41812724Snikos.nikoleris@arm.com * @param request_time The tick at which the block lookup is compete 41911197Sandreas.hansson@arm.com */ 42012724Snikos.nikoleris@arm.com virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, 42112724Snikos.nikoleris@arm.com Tick request_time); 42212724Snikos.nikoleris@arm.com 42312724Snikos.nikoleris@arm.com /* 42412724Snikos.nikoleris@arm.com * Handle a timing request that missed in the cache 42512724Snikos.nikoleris@arm.com * 42612724Snikos.nikoleris@arm.com * Implementation specific handling for different cache 42712724Snikos.nikoleris@arm.com * implementations 42812724Snikos.nikoleris@arm.com * 42912724Snikos.nikoleris@arm.com * @param ptk The request packet 43012724Snikos.nikoleris@arm.com * @param blk The referenced block 43112724Snikos.nikoleris@arm.com * @param forward_time The tick at which we can process dependent requests 43212724Snikos.nikoleris@arm.com * @param request_time The tick at which the block lookup is compete 43312724Snikos.nikoleris@arm.com */ 43412724Snikos.nikoleris@arm.com virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, 43512724Snikos.nikoleris@arm.com Tick forward_time, 43612724Snikos.nikoleris@arm.com Tick request_time) = 0; 43712724Snikos.nikoleris@arm.com 43812724Snikos.nikoleris@arm.com /* 43912724Snikos.nikoleris@arm.com * Handle a timing request that missed in the cache 44012724Snikos.nikoleris@arm.com * 44112724Snikos.nikoleris@arm.com * Common functionality across different cache implementations 44212724Snikos.nikoleris@arm.com * 44312724Snikos.nikoleris@arm.com * @param ptk The request packet 44412724Snikos.nikoleris@arm.com * @param blk The referenced block 44512724Snikos.nikoleris@arm.com * @param mshr Any existing mshr for the referenced cache block 44612724Snikos.nikoleris@arm.com * @param forward_time The tick at which we can process dependent requests 44712724Snikos.nikoleris@arm.com * @param request_time The tick at which the block lookup is compete 44812724Snikos.nikoleris@arm.com */ 44912724Snikos.nikoleris@arm.com void handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk, 45012724Snikos.nikoleris@arm.com Tick forward_time, Tick request_time); 45112724Snikos.nikoleris@arm.com 45212724Snikos.nikoleris@arm.com /** 45312724Snikos.nikoleris@arm.com * Performs the access specified by the request. 45412724Snikos.nikoleris@arm.com * @param pkt The request to perform. 45512724Snikos.nikoleris@arm.com */ 45612724Snikos.nikoleris@arm.com virtual void recvTimingReq(PacketPtr pkt); 45712724Snikos.nikoleris@arm.com 45812724Snikos.nikoleris@arm.com /** 45912724Snikos.nikoleris@arm.com * Handling the special case of uncacheable write responses to 46012724Snikos.nikoleris@arm.com * make recvTimingResp less cluttered. 46112724Snikos.nikoleris@arm.com */ 46212724Snikos.nikoleris@arm.com void handleUncacheableWriteResp(PacketPtr pkt); 46312724Snikos.nikoleris@arm.com 46412724Snikos.nikoleris@arm.com /** 46512724Snikos.nikoleris@arm.com * Service non-deferred MSHR targets using the received response 46612724Snikos.nikoleris@arm.com * 46712724Snikos.nikoleris@arm.com * Iterates through the list of targets that can be serviced with 46812724Snikos.nikoleris@arm.com * the current response. Any writebacks that need to performed 46912724Snikos.nikoleris@arm.com * must be appended to the writebacks parameter. 47012724Snikos.nikoleris@arm.com * 47112724Snikos.nikoleris@arm.com * @param mshr The MSHR that corresponds to the reponse 47212724Snikos.nikoleris@arm.com * @param pkt The response packet 47312724Snikos.nikoleris@arm.com * @param blk The reference block 47412724Snikos.nikoleris@arm.com * @param writebacks List of writebacks that need to be performed 47512724Snikos.nikoleris@arm.com */ 47612724Snikos.nikoleris@arm.com virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, 47712724Snikos.nikoleris@arm.com CacheBlk *blk, PacketList& writebacks) = 0; 47812724Snikos.nikoleris@arm.com 47912724Snikos.nikoleris@arm.com /** 48012724Snikos.nikoleris@arm.com * Handles a response (cache line fill/write ack) from the bus. 48112724Snikos.nikoleris@arm.com * @param pkt The response packet 48212724Snikos.nikoleris@arm.com */ 48312724Snikos.nikoleris@arm.com virtual void recvTimingResp(PacketPtr pkt); 48412724Snikos.nikoleris@arm.com 48512724Snikos.nikoleris@arm.com /** 48612724Snikos.nikoleris@arm.com * Snoops bus transactions to maintain coherence. 48712724Snikos.nikoleris@arm.com * @param pkt The current bus transaction. 48812724Snikos.nikoleris@arm.com */ 48912724Snikos.nikoleris@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt) = 0; 49012724Snikos.nikoleris@arm.com 49112724Snikos.nikoleris@arm.com /** 49212724Snikos.nikoleris@arm.com * Handle a snoop response. 49312724Snikos.nikoleris@arm.com * @param pkt Snoop response packet 49412724Snikos.nikoleris@arm.com */ 49512724Snikos.nikoleris@arm.com virtual void recvTimingSnoopResp(PacketPtr pkt) = 0; 49612724Snikos.nikoleris@arm.com 49712724Snikos.nikoleris@arm.com /** 49812724Snikos.nikoleris@arm.com * Handle a request in atomic mode that missed in this cache 49912724Snikos.nikoleris@arm.com * 50012724Snikos.nikoleris@arm.com * Creates a downstream request, sends it to the memory below and 50112724Snikos.nikoleris@arm.com * handles the response. As we are in atomic mode all operations 50212724Snikos.nikoleris@arm.com * are performed immediately. 50312724Snikos.nikoleris@arm.com * 50412724Snikos.nikoleris@arm.com * @param pkt The packet with the requests 50512724Snikos.nikoleris@arm.com * @param blk The referenced block 50612724Snikos.nikoleris@arm.com * @param writebacks A list with packets for any performed writebacks 50712724Snikos.nikoleris@arm.com * @return Cycles for handling the request 50812724Snikos.nikoleris@arm.com */ 50912724Snikos.nikoleris@arm.com virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk, 51012724Snikos.nikoleris@arm.com PacketList &writebacks) = 0; 51112724Snikos.nikoleris@arm.com 51212724Snikos.nikoleris@arm.com /** 51312724Snikos.nikoleris@arm.com * Performs the access specified by the request. 51412724Snikos.nikoleris@arm.com * @param pkt The request to perform. 51512724Snikos.nikoleris@arm.com * @return The number of ticks required for the access. 51612724Snikos.nikoleris@arm.com */ 51712724Snikos.nikoleris@arm.com virtual Tick recvAtomic(PacketPtr pkt); 51812724Snikos.nikoleris@arm.com 51912724Snikos.nikoleris@arm.com /** 52012724Snikos.nikoleris@arm.com * Snoop for the provided request in the cache and return the estimated 52112724Snikos.nikoleris@arm.com * time taken. 52212724Snikos.nikoleris@arm.com * @param pkt The memory request to snoop 52312724Snikos.nikoleris@arm.com * @return The number of ticks required for the snoop. 52412724Snikos.nikoleris@arm.com */ 52512724Snikos.nikoleris@arm.com virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0; 52612724Snikos.nikoleris@arm.com 52712724Snikos.nikoleris@arm.com /** 52812724Snikos.nikoleris@arm.com * Performs the access specified by the request. 52912724Snikos.nikoleris@arm.com * 53012724Snikos.nikoleris@arm.com * @param pkt The request to perform. 53112724Snikos.nikoleris@arm.com * @param fromCpuSide from the CPU side port or the memory side port 53212724Snikos.nikoleris@arm.com */ 53312724Snikos.nikoleris@arm.com virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side); 53412724Snikos.nikoleris@arm.com 53512724Snikos.nikoleris@arm.com /** 53612724Snikos.nikoleris@arm.com * Handle doing the Compare and Swap function for SPARC. 53712724Snikos.nikoleris@arm.com */ 53812724Snikos.nikoleris@arm.com void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); 53912724Snikos.nikoleris@arm.com 54012724Snikos.nikoleris@arm.com /** 54112724Snikos.nikoleris@arm.com * Return the next queue entry to service, either a pending miss 54212724Snikos.nikoleris@arm.com * from the MSHR queue, a buffered write from the write buffer, or 54312724Snikos.nikoleris@arm.com * something from the prefetcher. This function is responsible 54412724Snikos.nikoleris@arm.com * for prioritizing among those sources on the fly. 54512724Snikos.nikoleris@arm.com */ 54612724Snikos.nikoleris@arm.com QueueEntry* getNextQueueEntry(); 54712724Snikos.nikoleris@arm.com 54812724Snikos.nikoleris@arm.com /** 54912724Snikos.nikoleris@arm.com * Insert writebacks into the write buffer 55012724Snikos.nikoleris@arm.com */ 55112724Snikos.nikoleris@arm.com virtual void doWritebacks(PacketList& writebacks, Tick forward_time) = 0; 55212724Snikos.nikoleris@arm.com 55312724Snikos.nikoleris@arm.com /** 55412724Snikos.nikoleris@arm.com * Send writebacks down the memory hierarchy in atomic mode 55512724Snikos.nikoleris@arm.com */ 55612724Snikos.nikoleris@arm.com virtual void doWritebacksAtomic(PacketList& writebacks) = 0; 55712724Snikos.nikoleris@arm.com 55812724Snikos.nikoleris@arm.com /** 55912724Snikos.nikoleris@arm.com * Create an appropriate downstream bus request packet. 56012724Snikos.nikoleris@arm.com * 56112724Snikos.nikoleris@arm.com * Creates a new packet with the request to be send to the memory 56212724Snikos.nikoleris@arm.com * below, or nullptr if the current request in cpu_pkt should just 56312724Snikos.nikoleris@arm.com * be forwarded on. 56412724Snikos.nikoleris@arm.com * 56512724Snikos.nikoleris@arm.com * @param cpu_pkt The miss packet that needs to be satisfied. 56612724Snikos.nikoleris@arm.com * @param blk The referenced block, can be nullptr. 56712724Snikos.nikoleris@arm.com * @param needs_writable Indicates that the block must be writable 56812724Snikos.nikoleris@arm.com * even if the request in cpu_pkt doesn't indicate that. 56912724Snikos.nikoleris@arm.com * @return A packet send to the memory below 57012724Snikos.nikoleris@arm.com */ 57112724Snikos.nikoleris@arm.com virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 57212724Snikos.nikoleris@arm.com bool needs_writable) const = 0; 57312724Snikos.nikoleris@arm.com 57412724Snikos.nikoleris@arm.com /** 57512724Snikos.nikoleris@arm.com * Determine if clean lines should be written back or not. In 57612724Snikos.nikoleris@arm.com * cases where a downstream cache is mostly inclusive we likely 57712724Snikos.nikoleris@arm.com * want it to act as a victim cache also for lines that have not 57812724Snikos.nikoleris@arm.com * been modified. Hence, we cannot simply drop the line (or send a 57912724Snikos.nikoleris@arm.com * clean evict), but rather need to send the actual data. 58012724Snikos.nikoleris@arm.com */ 58112724Snikos.nikoleris@arm.com const bool writebackClean; 58212724Snikos.nikoleris@arm.com 58312724Snikos.nikoleris@arm.com /** 58412724Snikos.nikoleris@arm.com * Writebacks from the tempBlock, resulting on the response path 58512724Snikos.nikoleris@arm.com * in atomic mode, must happen after the call to recvAtomic has 58612724Snikos.nikoleris@arm.com * finished (for the right ordering of the packets). We therefore 58712724Snikos.nikoleris@arm.com * need to hold on to the packets, and have a method and an event 58812724Snikos.nikoleris@arm.com * to send them. 58912724Snikos.nikoleris@arm.com */ 59012724Snikos.nikoleris@arm.com PacketPtr tempBlockWriteback; 59112724Snikos.nikoleris@arm.com 59212724Snikos.nikoleris@arm.com /** 59312724Snikos.nikoleris@arm.com * Send the outstanding tempBlock writeback. To be called after 59412724Snikos.nikoleris@arm.com * recvAtomic finishes in cases where the block we filled is in 59512724Snikos.nikoleris@arm.com * fact the tempBlock, and now needs to be written back. 59612724Snikos.nikoleris@arm.com */ 59712724Snikos.nikoleris@arm.com void writebackTempBlockAtomic() { 59812724Snikos.nikoleris@arm.com assert(tempBlockWriteback != nullptr); 59912724Snikos.nikoleris@arm.com PacketList writebacks{tempBlockWriteback}; 60012724Snikos.nikoleris@arm.com doWritebacksAtomic(writebacks); 60112724Snikos.nikoleris@arm.com tempBlockWriteback = nullptr; 60212724Snikos.nikoleris@arm.com } 60312724Snikos.nikoleris@arm.com 60412724Snikos.nikoleris@arm.com /** 60512724Snikos.nikoleris@arm.com * An event to writeback the tempBlock after recvAtomic 60612724Snikos.nikoleris@arm.com * finishes. To avoid other calls to recvAtomic getting in 60712724Snikos.nikoleris@arm.com * between, we create this event with a higher priority. 60812724Snikos.nikoleris@arm.com */ 60912724Snikos.nikoleris@arm.com EventFunctionWrapper writebackTempBlockAtomicEvent; 61012724Snikos.nikoleris@arm.com 61112724Snikos.nikoleris@arm.com /** 61212724Snikos.nikoleris@arm.com * Perform any necessary updates to the block and perform any data 61312724Snikos.nikoleris@arm.com * exchange between the packet and the block. The flags of the 61412724Snikos.nikoleris@arm.com * packet are also set accordingly. 61512724Snikos.nikoleris@arm.com * 61612724Snikos.nikoleris@arm.com * @param pkt Request packet from upstream that hit a block 61712724Snikos.nikoleris@arm.com * @param blk Cache block that the packet hit 61812724Snikos.nikoleris@arm.com * @param deferred_response Whether this request originally missed 61912724Snikos.nikoleris@arm.com * @param pending_downgrade Whether the writable flag is to be removed 62012724Snikos.nikoleris@arm.com */ 62112724Snikos.nikoleris@arm.com virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk, 62212724Snikos.nikoleris@arm.com bool deferred_response = false, 62312724Snikos.nikoleris@arm.com bool pending_downgrade = false); 62412724Snikos.nikoleris@arm.com 62512724Snikos.nikoleris@arm.com /** 62612724Snikos.nikoleris@arm.com * Maintain the clusivity of this cache by potentially 62712724Snikos.nikoleris@arm.com * invalidating a block. This method works in conjunction with 62812724Snikos.nikoleris@arm.com * satisfyRequest, but is separate to allow us to handle all MSHR 62912724Snikos.nikoleris@arm.com * targets before potentially dropping a block. 63012724Snikos.nikoleris@arm.com * 63112724Snikos.nikoleris@arm.com * @param from_cache Whether we have dealt with a packet from a cache 63212724Snikos.nikoleris@arm.com * @param blk The block that should potentially be dropped 63312724Snikos.nikoleris@arm.com */ 63412724Snikos.nikoleris@arm.com void maintainClusivity(bool from_cache, CacheBlk *blk); 63512724Snikos.nikoleris@arm.com 63612724Snikos.nikoleris@arm.com /** 63712724Snikos.nikoleris@arm.com * Handle a fill operation caused by a received packet. 63812724Snikos.nikoleris@arm.com * 63912724Snikos.nikoleris@arm.com * Populates a cache block and handles all outstanding requests for the 64012724Snikos.nikoleris@arm.com * satisfied fill request. This version takes two memory requests. One 64112724Snikos.nikoleris@arm.com * contains the fill data, the other is an optional target to satisfy. 64212724Snikos.nikoleris@arm.com * Note that the reason we return a list of writebacks rather than 64312724Snikos.nikoleris@arm.com * inserting them directly in the write buffer is that this function 64412724Snikos.nikoleris@arm.com * is called by both atomic and timing-mode accesses, and in atomic 64512724Snikos.nikoleris@arm.com * mode we don't mess with the write buffer (we just perform the 64612724Snikos.nikoleris@arm.com * writebacks atomically once the original request is complete). 64712724Snikos.nikoleris@arm.com * 64812724Snikos.nikoleris@arm.com * @param pkt The memory request with the fill data. 64912724Snikos.nikoleris@arm.com * @param blk The cache block if it already exists. 65012724Snikos.nikoleris@arm.com * @param writebacks List for any writebacks that need to be performed. 65112724Snikos.nikoleris@arm.com * @param allocate Whether to allocate a block or use the temp block 65212724Snikos.nikoleris@arm.com * @return Pointer to the new cache block. 65312724Snikos.nikoleris@arm.com */ 65412724Snikos.nikoleris@arm.com CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, 65512724Snikos.nikoleris@arm.com PacketList &writebacks, bool allocate); 65612724Snikos.nikoleris@arm.com 65712724Snikos.nikoleris@arm.com /** 65812724Snikos.nikoleris@arm.com * Allocate a new block and perform any necessary writebacks 65912724Snikos.nikoleris@arm.com * 66012724Snikos.nikoleris@arm.com * Find a victim block and if necessary prepare writebacks for any 66112724Snikos.nikoleris@arm.com * existing data. May return nullptr if there are no replaceable 66212754Sodanrc@yahoo.com.br * blocks. If a replaceable block is found, it inserts the new block in 66312754Sodanrc@yahoo.com.br * its place. The new block, however, is not set as valid yet. 66412724Snikos.nikoleris@arm.com * 66512754Sodanrc@yahoo.com.br * @param pkt Packet holding the address to update 66612724Snikos.nikoleris@arm.com * @param writebacks A list of writeback packets for the evicted blocks 66712724Snikos.nikoleris@arm.com * @return the allocated block 66812724Snikos.nikoleris@arm.com */ 66912754Sodanrc@yahoo.com.br CacheBlk *allocateBlock(const PacketPtr pkt, PacketList &writebacks); 67012724Snikos.nikoleris@arm.com /** 67112724Snikos.nikoleris@arm.com * Evict a cache block. 67212724Snikos.nikoleris@arm.com * 67312724Snikos.nikoleris@arm.com * Performs a writeback if necesssary and invalidates the block 67412724Snikos.nikoleris@arm.com * 67512724Snikos.nikoleris@arm.com * @param blk Block to invalidate 67612724Snikos.nikoleris@arm.com * @return A packet with the writeback, can be nullptr 67712724Snikos.nikoleris@arm.com */ 67812724Snikos.nikoleris@arm.com M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk) = 0; 67912724Snikos.nikoleris@arm.com 68012724Snikos.nikoleris@arm.com /** 68112724Snikos.nikoleris@arm.com * Evict a cache block. 68212724Snikos.nikoleris@arm.com * 68312724Snikos.nikoleris@arm.com * Performs a writeback if necesssary and invalidates the block 68412724Snikos.nikoleris@arm.com * 68512724Snikos.nikoleris@arm.com * @param blk Block to invalidate 68612724Snikos.nikoleris@arm.com * @param writebacks Return a list of packets with writebacks 68712724Snikos.nikoleris@arm.com */ 68812724Snikos.nikoleris@arm.com virtual void evictBlock(CacheBlk *blk, PacketList &writebacks) = 0; 68912724Snikos.nikoleris@arm.com 69012724Snikos.nikoleris@arm.com /** 69112724Snikos.nikoleris@arm.com * Invalidate a cache block. 69212724Snikos.nikoleris@arm.com * 69312724Snikos.nikoleris@arm.com * @param blk Block to invalidate 69412724Snikos.nikoleris@arm.com */ 69512724Snikos.nikoleris@arm.com void invalidateBlock(CacheBlk *blk); 69612724Snikos.nikoleris@arm.com 69712724Snikos.nikoleris@arm.com /** 69812724Snikos.nikoleris@arm.com * Create a writeback request for the given block. 69912724Snikos.nikoleris@arm.com * 70012724Snikos.nikoleris@arm.com * @param blk The block to writeback. 70112724Snikos.nikoleris@arm.com * @return The writeback request for the block. 70212724Snikos.nikoleris@arm.com */ 70312724Snikos.nikoleris@arm.com PacketPtr writebackBlk(CacheBlk *blk); 70412724Snikos.nikoleris@arm.com 70512724Snikos.nikoleris@arm.com /** 70612724Snikos.nikoleris@arm.com * Create a writeclean request for the given block. 70712724Snikos.nikoleris@arm.com * 70812724Snikos.nikoleris@arm.com * Creates a request that writes the block to the cache below 70912724Snikos.nikoleris@arm.com * without evicting the block from the current cache. 71012724Snikos.nikoleris@arm.com * 71112724Snikos.nikoleris@arm.com * @param blk The block to write clean. 71212724Snikos.nikoleris@arm.com * @param dest The destination of the write clean operation. 71312724Snikos.nikoleris@arm.com * @param id Use the given packet id for the write clean operation. 71412724Snikos.nikoleris@arm.com * @return The generated write clean packet. 71512724Snikos.nikoleris@arm.com */ 71612724Snikos.nikoleris@arm.com PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id); 71711197Sandreas.hansson@arm.com 71811197Sandreas.hansson@arm.com /** 7199347SAndreas.Sandberg@arm.com * Write back dirty blocks in the cache using functional accesses. 7209347SAndreas.Sandberg@arm.com */ 72112724Snikos.nikoleris@arm.com virtual void memWriteback() override; 72212724Snikos.nikoleris@arm.com 7239347SAndreas.Sandberg@arm.com /** 7249347SAndreas.Sandberg@arm.com * Invalidates all blocks in the cache. 7259347SAndreas.Sandberg@arm.com * 7269347SAndreas.Sandberg@arm.com * @warn Dirty cache lines will not be written back to 7279347SAndreas.Sandberg@arm.com * memory. Make sure to call functionalWriteback() first if you 7289347SAndreas.Sandberg@arm.com * want the to write them to memory. 7299347SAndreas.Sandberg@arm.com */ 73012724Snikos.nikoleris@arm.com virtual void memInvalidate() override; 73112724Snikos.nikoleris@arm.com 7329347SAndreas.Sandberg@arm.com /** 7339347SAndreas.Sandberg@arm.com * Determine if there are any dirty blocks in the cache. 7349347SAndreas.Sandberg@arm.com * 73512724Snikos.nikoleris@arm.com * @return true if at least one block is dirty, false otherwise. 7369347SAndreas.Sandberg@arm.com */ 73712724Snikos.nikoleris@arm.com bool isDirty() const; 7389347SAndreas.Sandberg@arm.com 73910821Sandreas.hansson@arm.com /** 74010821Sandreas.hansson@arm.com * Determine if an address is in the ranges covered by this 74110821Sandreas.hansson@arm.com * cache. This is useful to filter snoops. 74210821Sandreas.hansson@arm.com * 74310821Sandreas.hansson@arm.com * @param addr Address to check against 74410821Sandreas.hansson@arm.com * 74510821Sandreas.hansson@arm.com * @return If the address in question is in range 74610821Sandreas.hansson@arm.com */ 74710821Sandreas.hansson@arm.com bool inRange(Addr addr) const; 74810821Sandreas.hansson@arm.com 74912724Snikos.nikoleris@arm.com /** 75012724Snikos.nikoleris@arm.com * Find next request ready time from among possible sources. 75112724Snikos.nikoleris@arm.com */ 75212724Snikos.nikoleris@arm.com Tick nextQueueReadyTime() const; 75312724Snikos.nikoleris@arm.com 7544626SN/A /** Block size of this cache */ 7556227Snate@binkert.org const unsigned blkSize; 7564626SN/A 7574630SN/A /** 75810693SMarco.Balboni@ARM.com * The latency of tag lookup of a cache. It occurs when there is 75910693SMarco.Balboni@ARM.com * an access to the cache. 7604630SN/A */ 76110693SMarco.Balboni@ARM.com const Cycles lookupLatency; 7629263Smrinmoy.ghosh@arm.com 7639263Smrinmoy.ghosh@arm.com /** 76411722Ssophiane.senni@gmail.com * The latency of data access of a cache. It occurs when there is 76511722Ssophiane.senni@gmail.com * an access to the cache. 76611722Ssophiane.senni@gmail.com */ 76711722Ssophiane.senni@gmail.com const Cycles dataLatency; 76811722Ssophiane.senni@gmail.com 76911722Ssophiane.senni@gmail.com /** 77010693SMarco.Balboni@ARM.com * This is the forward latency of the cache. It occurs when there 77110693SMarco.Balboni@ARM.com * is a cache miss and a request is forwarded downstream, in 77210693SMarco.Balboni@ARM.com * particular an outbound miss. 77310693SMarco.Balboni@ARM.com */ 77410693SMarco.Balboni@ARM.com const Cycles forwardLatency; 77510693SMarco.Balboni@ARM.com 77610693SMarco.Balboni@ARM.com /** The latency to fill a cache block */ 77710693SMarco.Balboni@ARM.com const Cycles fillLatency; 77810693SMarco.Balboni@ARM.com 77910693SMarco.Balboni@ARM.com /** 78010693SMarco.Balboni@ARM.com * The latency of sending reponse to its upper level cache/core on 78110693SMarco.Balboni@ARM.com * a linefill. The responseLatency parameter captures this 78210693SMarco.Balboni@ARM.com * latency. 7839263Smrinmoy.ghosh@arm.com */ 7849288Sandreas.hansson@arm.com const Cycles responseLatency; 7854630SN/A 7864626SN/A /** The number of targets for each MSHR. */ 7874626SN/A const int numTarget; 7884626SN/A 7896122SSteve.Reinhardt@amd.com /** Do we forward snoops from mem side port through to cpu side port? */ 79011331Sandreas.hansson@arm.com bool forwardSnoops; 7914626SN/A 7922810SN/A /** 79312724Snikos.nikoleris@arm.com * Clusivity with respect to the upstream cache, determining if we 79412724Snikos.nikoleris@arm.com * fill into both this cache and the cache above on a miss. Note 79512724Snikos.nikoleris@arm.com * that we currently do not support strict clusivity policies. 79612724Snikos.nikoleris@arm.com */ 79712724Snikos.nikoleris@arm.com const Enums::Clusivity clusivity; 79812724Snikos.nikoleris@arm.com 79912724Snikos.nikoleris@arm.com /** 80010884Sandreas.hansson@arm.com * Is this cache read only, for example the instruction cache, or 80110884Sandreas.hansson@arm.com * table-walker cache. A cache that is read only should never see 80210884Sandreas.hansson@arm.com * any writes, and should never get any dirty data (and hence 80310884Sandreas.hansson@arm.com * never have to do any writebacks). 80410884Sandreas.hansson@arm.com */ 80510884Sandreas.hansson@arm.com const bool isReadOnly; 80610884Sandreas.hansson@arm.com 80710884Sandreas.hansson@arm.com /** 8082810SN/A * Bit vector of the blocking reasons for the access path. 8092810SN/A * @sa #BlockedCause 8102810SN/A */ 8112810SN/A uint8_t blocked; 8122810SN/A 8136122SSteve.Reinhardt@amd.com /** Increasing order number assigned to each incoming request. */ 8146122SSteve.Reinhardt@amd.com uint64_t order; 8156122SSteve.Reinhardt@amd.com 8162810SN/A /** Stores time the cache blocked for statistics. */ 8179288Sandreas.hansson@arm.com Cycles blockedCycle; 8182810SN/A 8194626SN/A /** Pointer to the MSHR that has no targets. */ 8204626SN/A MSHR *noTargetMSHR; 8212810SN/A 8222810SN/A /** The number of misses to trigger an exit event. */ 8232810SN/A Counter missCount; 8242810SN/A 8256122SSteve.Reinhardt@amd.com /** 8266122SSteve.Reinhardt@amd.com * The address range to which the cache responds on the CPU side. 8276122SSteve.Reinhardt@amd.com * Normally this is all possible memory addresses. */ 8289529Sandreas.hansson@arm.com const AddrRangeList addrRanges; 8296122SSteve.Reinhardt@amd.com 8308833Sdam.sunwoo@arm.com public: 8318833Sdam.sunwoo@arm.com /** System we are currently operating in. */ 8328833Sdam.sunwoo@arm.com System *system; 8336978SLisa.Hsu@amd.com 8342810SN/A // Statistics 8352810SN/A /** 8362810SN/A * @addtogroup CacheStatistics 8372810SN/A * @{ 8382810SN/A */ 8392810SN/A 84011483Snikos.nikoleris@arm.com /** Number of hits per thread for each type of command. 84111483Snikos.nikoleris@arm.com @sa Packet::Command */ 8425999Snate@binkert.org Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 8432810SN/A /** Number of hits for demand accesses. */ 8442810SN/A Stats::Formula demandHits; 8452810SN/A /** Number of hit for all accesses. */ 8462810SN/A Stats::Formula overallHits; 8472810SN/A 84811483Snikos.nikoleris@arm.com /** Number of misses per thread for each type of command. 84911483Snikos.nikoleris@arm.com @sa Packet::Command */ 8505999Snate@binkert.org Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 8512810SN/A /** Number of misses for demand accesses. */ 8522810SN/A Stats::Formula demandMisses; 8532810SN/A /** Number of misses for all accesses. */ 8542810SN/A Stats::Formula overallMisses; 8552810SN/A 8562810SN/A /** 8572810SN/A * Total number of cycles per thread/command spent waiting for a miss. 8582810SN/A * Used to calculate the average miss latency. 8592810SN/A */ 8605999Snate@binkert.org Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 8612810SN/A /** Total number of cycles spent waiting for demand misses. */ 8622810SN/A Stats::Formula demandMissLatency; 8632810SN/A /** Total number of cycles spent waiting for all misses. */ 8642810SN/A Stats::Formula overallMissLatency; 8652810SN/A 8662810SN/A /** The number of accesses per command and thread. */ 8674022SN/A Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 8682810SN/A /** The number of demand accesses. */ 8692810SN/A Stats::Formula demandAccesses; 8702810SN/A /** The number of overall accesses. */ 8712810SN/A Stats::Formula overallAccesses; 8722810SN/A 8732810SN/A /** The miss rate per command and thread. */ 8744022SN/A Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 8752810SN/A /** The miss rate of all demand accesses. */ 8762810SN/A Stats::Formula demandMissRate; 8772810SN/A /** The miss rate for all accesses. */ 8782810SN/A Stats::Formula overallMissRate; 8792810SN/A 8802810SN/A /** The average miss latency per command and thread. */ 8814022SN/A Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 8822810SN/A /** The average miss latency for demand misses. */ 8832810SN/A Stats::Formula demandAvgMissLatency; 8842810SN/A /** The average miss latency for all misses. */ 8852810SN/A Stats::Formula overallAvgMissLatency; 8862810SN/A 8872810SN/A /** The total number of cycles blocked for each blocked cause. */ 8885999Snate@binkert.org Stats::Vector blocked_cycles; 8892810SN/A /** The number of times this cache blocked for each blocked cause. */ 8905999Snate@binkert.org Stats::Vector blocked_causes; 8912810SN/A 8922810SN/A /** The average number of cycles blocked for each blocked cause. */ 8932810SN/A Stats::Formula avg_blocked; 8942810SN/A 89511436SRekai.GonzalezAlberquilla@arm.com /** The number of times a HW-prefetched block is evicted w/o reference. */ 89611436SRekai.GonzalezAlberquilla@arm.com Stats::Scalar unusedPrefetches; 89711436SRekai.GonzalezAlberquilla@arm.com 8984626SN/A /** Number of blocks written back per thread. */ 8995999Snate@binkert.org Stats::Vector writebacks; 9004626SN/A 9014626SN/A /** Number of misses that hit in the MSHRs per command and thread. */ 9025999Snate@binkert.org Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 9034626SN/A /** Demand misses that hit in the MSHRs. */ 9044626SN/A Stats::Formula demandMshrHits; 9054626SN/A /** Total number of misses that hit in the MSHRs. */ 9064626SN/A Stats::Formula overallMshrHits; 9074626SN/A 9084626SN/A /** Number of misses that miss in the MSHRs, per command and thread. */ 9095999Snate@binkert.org Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 9104626SN/A /** Demand misses that miss in the MSHRs. */ 9114626SN/A Stats::Formula demandMshrMisses; 9124626SN/A /** Total number of misses that miss in the MSHRs. */ 9134626SN/A Stats::Formula overallMshrMisses; 9144626SN/A 9154626SN/A /** Number of misses that miss in the MSHRs, per command and thread. */ 9165999Snate@binkert.org Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 9174626SN/A /** Total number of misses that miss in the MSHRs. */ 9184626SN/A Stats::Formula overallMshrUncacheable; 9194626SN/A 9204626SN/A /** Total cycle latency of each MSHR miss, per command and thread. */ 9215999Snate@binkert.org Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 9224626SN/A /** Total cycle latency of demand MSHR misses. */ 9234626SN/A Stats::Formula demandMshrMissLatency; 9244626SN/A /** Total cycle latency of overall MSHR misses. */ 9254626SN/A Stats::Formula overallMshrMissLatency; 9264626SN/A 9274626SN/A /** Total cycle latency of each MSHR miss, per command and thread. */ 9285999Snate@binkert.org Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 9294626SN/A /** Total cycle latency of overall MSHR misses. */ 9304626SN/A Stats::Formula overallMshrUncacheableLatency; 9314626SN/A 9327461Snate@binkert.org#if 0 9334626SN/A /** The total number of MSHR accesses per command and thread. */ 9344626SN/A Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 9354626SN/A /** The total number of demand MSHR accesses. */ 9364626SN/A Stats::Formula demandMshrAccesses; 9374626SN/A /** The total number of MSHR accesses. */ 9384626SN/A Stats::Formula overallMshrAccesses; 9397461Snate@binkert.org#endif 9404626SN/A 9414626SN/A /** The miss rate in the MSHRs pre command and thread. */ 9424626SN/A Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 9434626SN/A /** The demand miss rate in the MSHRs. */ 9444626SN/A Stats::Formula demandMshrMissRate; 9454626SN/A /** The overall miss rate in the MSHRs. */ 9464626SN/A Stats::Formula overallMshrMissRate; 9474626SN/A 9484626SN/A /** The average latency of an MSHR miss, per command and thread. */ 9494626SN/A Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 9504626SN/A /** The average latency of a demand MSHR miss. */ 9514626SN/A Stats::Formula demandAvgMshrMissLatency; 9524626SN/A /** The average overall latency of an MSHR miss. */ 9534626SN/A Stats::Formula overallAvgMshrMissLatency; 9544626SN/A 9554626SN/A /** The average latency of an MSHR miss, per command and thread. */ 9564626SN/A Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 9574626SN/A /** The average overall latency of an MSHR miss. */ 9584626SN/A Stats::Formula overallAvgMshrUncacheableLatency; 9594626SN/A 96012702Snikos.nikoleris@arm.com /** Number of replacements of valid blocks. */ 96112702Snikos.nikoleris@arm.com Stats::Scalar replacements; 96212702Snikos.nikoleris@arm.com 9632810SN/A /** 9642810SN/A * @} 9652810SN/A */ 9662810SN/A 9672810SN/A /** 9682810SN/A * Register stats for this object. 9692810SN/A */ 97012724Snikos.nikoleris@arm.com void regStats() override; 9712810SN/A 9722810SN/A public: 97311053Sandreas.hansson@arm.com BaseCache(const BaseCacheParams *p, unsigned blk_size); 97412724Snikos.nikoleris@arm.com ~BaseCache(); 9753606SN/A 97612724Snikos.nikoleris@arm.com void init() override; 9772858SN/A 97812724Snikos.nikoleris@arm.com BaseMasterPort &getMasterPort(const std::string &if_name, 97912724Snikos.nikoleris@arm.com PortID idx = InvalidPortID) override; 98012724Snikos.nikoleris@arm.com BaseSlavePort &getSlavePort(const std::string &if_name, 98112724Snikos.nikoleris@arm.com PortID idx = InvalidPortID) override; 9828922Swilliam.wang@arm.com 9832810SN/A /** 9842810SN/A * Query block size of a cache. 9852810SN/A * @return The block size 9862810SN/A */ 9876227Snate@binkert.org unsigned 9886227Snate@binkert.org getBlockSize() const 9892810SN/A { 9902810SN/A return blkSize; 9912810SN/A } 9922810SN/A 9938883SAli.Saidi@ARM.com const AddrRangeList &getAddrRanges() const { return addrRanges; } 9946122SSteve.Reinhardt@amd.com 99510942Sandreas.hansson@arm.com MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true) 9964628SN/A { 99711892Snikos.nikoleris@arm.com MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize, 99811375Sandreas.hansson@arm.com pkt, time, order++, 99911375Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 100011375Sandreas.hansson@arm.com 100111375Sandreas.hansson@arm.com if (mshrQueue.isFull()) { 100211375Sandreas.hansson@arm.com setBlocked((BlockedCause)MSHRQueue_MSHRs); 100311375Sandreas.hansson@arm.com } 100411375Sandreas.hansson@arm.com 100511375Sandreas.hansson@arm.com if (sched_send) { 100611375Sandreas.hansson@arm.com // schedule the send 100711375Sandreas.hansson@arm.com schedMemSideSendEvent(time); 100811375Sandreas.hansson@arm.com } 100911375Sandreas.hansson@arm.com 101011375Sandreas.hansson@arm.com return mshr; 10114628SN/A } 10124628SN/A 101311375Sandreas.hansson@arm.com void allocateWriteBuffer(PacketPtr pkt, Tick time) 10144628SN/A { 101511191Sandreas.hansson@arm.com // should only see writes or clean evicts here 101611191Sandreas.hansson@arm.com assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict); 101711191Sandreas.hansson@arm.com 101811892Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 101911375Sandreas.hansson@arm.com 102011375Sandreas.hansson@arm.com WriteQueueEntry *wq_entry = 102111375Sandreas.hansson@arm.com writeBuffer.findMatch(blk_addr, pkt->isSecure()); 102211375Sandreas.hansson@arm.com if (wq_entry && !wq_entry->inService) { 102311744Snikos.nikoleris@arm.com DPRINTF(Cache, "Potential to merge writeback %s", pkt->print()); 102411375Sandreas.hansson@arm.com } 102511375Sandreas.hansson@arm.com 102611375Sandreas.hansson@arm.com writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++); 102711375Sandreas.hansson@arm.com 102811375Sandreas.hansson@arm.com if (writeBuffer.isFull()) { 102911375Sandreas.hansson@arm.com setBlocked((BlockedCause)MSHRQueue_WriteBuffer); 103011375Sandreas.hansson@arm.com } 103111375Sandreas.hansson@arm.com 103211375Sandreas.hansson@arm.com // schedule the send 103311375Sandreas.hansson@arm.com schedMemSideSendEvent(time); 10344628SN/A } 10354628SN/A 10362810SN/A /** 10372810SN/A * Returns true if the cache is blocked for accesses. 10382810SN/A */ 10399529Sandreas.hansson@arm.com bool isBlocked() const 10402810SN/A { 10412810SN/A return blocked != 0; 10422810SN/A } 10432810SN/A 10442810SN/A /** 10452810SN/A * Marks the access path of the cache as blocked for the given cause. This 10462810SN/A * also sets the blocked flag in the slave interface. 10472810SN/A * @param cause The reason for the cache blocking. 10482810SN/A */ 10492810SN/A void setBlocked(BlockedCause cause) 10502810SN/A { 10512810SN/A uint8_t flag = 1 << cause; 10522810SN/A if (blocked == 0) { 10532810SN/A blocked_causes[cause]++; 10549288Sandreas.hansson@arm.com blockedCycle = curCycle(); 105512724Snikos.nikoleris@arm.com cpuSidePort.setBlocked(); 10562810SN/A } 10574630SN/A blocked |= flag; 10584630SN/A DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 10592810SN/A } 10602810SN/A 10612810SN/A /** 10622810SN/A * Marks the cache as unblocked for the given cause. This also clears the 10632810SN/A * blocked flags in the appropriate interfaces. 10642810SN/A * @param cause The newly unblocked cause. 10652810SN/A * @warning Calling this function can cause a blocked request on the bus to 10662810SN/A * access the cache. The cache must be in a state to handle that request. 10672810SN/A */ 10682810SN/A void clearBlocked(BlockedCause cause) 10692810SN/A { 10702810SN/A uint8_t flag = 1 << cause; 10714630SN/A blocked &= ~flag; 10724630SN/A DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 10734630SN/A if (blocked == 0) { 10749288Sandreas.hansson@arm.com blocked_cycles[cause] += curCycle() - blockedCycle; 107512724Snikos.nikoleris@arm.com cpuSidePort.clearBlocked(); 10762810SN/A } 10772810SN/A } 10782810SN/A 10792810SN/A /** 108010942Sandreas.hansson@arm.com * Schedule a send event for the memory-side port. If already 108110942Sandreas.hansson@arm.com * scheduled, this may reschedule the event at an earlier 108210942Sandreas.hansson@arm.com * time. When the specified time is reached, the port is free to 108310942Sandreas.hansson@arm.com * send either a response, a request, or a prefetch request. 108410942Sandreas.hansson@arm.com * 108510942Sandreas.hansson@arm.com * @param time The time when to attempt sending a packet. 10862810SN/A */ 108710942Sandreas.hansson@arm.com void schedMemSideSendEvent(Tick time) 10882810SN/A { 108912724Snikos.nikoleris@arm.com memSidePort.schedSendEvent(time); 10902811SN/A } 10913503SN/A 109212724Snikos.nikoleris@arm.com bool inCache(Addr addr, bool is_secure) const { 109312724Snikos.nikoleris@arm.com return tags->findBlock(addr, is_secure); 109412724Snikos.nikoleris@arm.com } 10954626SN/A 109612724Snikos.nikoleris@arm.com bool inMissQueue(Addr addr, bool is_secure) const { 109712724Snikos.nikoleris@arm.com return mshrQueue.findMatch(addr, is_secure); 109812724Snikos.nikoleris@arm.com } 10994626SN/A 11008833Sdam.sunwoo@arm.com void incMissCount(PacketPtr pkt) 11013503SN/A { 11028833Sdam.sunwoo@arm.com assert(pkt->req->masterId() < system->maxMasters()); 11038833Sdam.sunwoo@arm.com misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 110410020Smatt.horsnell@ARM.com pkt->req->incAccessDepth(); 11054626SN/A if (missCount) { 11064626SN/A --missCount; 11074626SN/A if (missCount == 0) 11084626SN/A exitSimLoop("A cache reached the maximum miss count"); 11093503SN/A } 11103503SN/A } 11118833Sdam.sunwoo@arm.com void incHitCount(PacketPtr pkt) 11126978SLisa.Hsu@amd.com { 11138833Sdam.sunwoo@arm.com assert(pkt->req->masterId() < system->maxMasters()); 11148833Sdam.sunwoo@arm.com hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 11156978SLisa.Hsu@amd.com 11166978SLisa.Hsu@amd.com } 11173503SN/A 111812724Snikos.nikoleris@arm.com /** 111912724Snikos.nikoleris@arm.com * Cache block visitor that writes back dirty cache blocks using 112012724Snikos.nikoleris@arm.com * functional writes. 112112724Snikos.nikoleris@arm.com */ 112212728Snikos.nikoleris@arm.com void writebackVisitor(CacheBlk &blk); 112312724Snikos.nikoleris@arm.com 112412724Snikos.nikoleris@arm.com /** 112512724Snikos.nikoleris@arm.com * Cache block visitor that invalidates all blocks in the cache. 112612724Snikos.nikoleris@arm.com * 112712724Snikos.nikoleris@arm.com * @warn Dirty cache lines will not be written back to memory. 112812724Snikos.nikoleris@arm.com */ 112912728Snikos.nikoleris@arm.com void invalidateVisitor(CacheBlk &blk); 113012724Snikos.nikoleris@arm.com 113112724Snikos.nikoleris@arm.com /** 113212724Snikos.nikoleris@arm.com * Take an MSHR, turn it into a suitable downstream packet, and 113312724Snikos.nikoleris@arm.com * send it out. This construct allows a queue entry to choose a suitable 113412724Snikos.nikoleris@arm.com * approach based on its type. 113512724Snikos.nikoleris@arm.com * 113612724Snikos.nikoleris@arm.com * @param mshr The MSHR to turn into a packet and send 113712724Snikos.nikoleris@arm.com * @return True if the port is waiting for a retry 113812724Snikos.nikoleris@arm.com */ 113912724Snikos.nikoleris@arm.com virtual bool sendMSHRQueuePacket(MSHR* mshr); 114012724Snikos.nikoleris@arm.com 114112724Snikos.nikoleris@arm.com /** 114212724Snikos.nikoleris@arm.com * Similar to sendMSHR, but for a write-queue entry 114312724Snikos.nikoleris@arm.com * instead. Create the packet, and send it, and if successful also 114412724Snikos.nikoleris@arm.com * mark the entry in service. 114512724Snikos.nikoleris@arm.com * 114612724Snikos.nikoleris@arm.com * @param wq_entry The write-queue entry to turn into a packet and send 114712724Snikos.nikoleris@arm.com * @return True if the port is waiting for a retry 114812724Snikos.nikoleris@arm.com */ 114912724Snikos.nikoleris@arm.com bool sendWriteQueuePacket(WriteQueueEntry* wq_entry); 115012724Snikos.nikoleris@arm.com 115112724Snikos.nikoleris@arm.com /** 115212724Snikos.nikoleris@arm.com * Serialize the state of the caches 115312724Snikos.nikoleris@arm.com * 115412724Snikos.nikoleris@arm.com * We currently don't support checkpointing cache state, so this panics. 115512724Snikos.nikoleris@arm.com */ 115612724Snikos.nikoleris@arm.com void serialize(CheckpointOut &cp) const override; 115712724Snikos.nikoleris@arm.com void unserialize(CheckpointIn &cp) override; 115812724Snikos.nikoleris@arm.com 115912724Snikos.nikoleris@arm.com}; 116012724Snikos.nikoleris@arm.com 116111051Sandreas.hansson@arm.com#endif //__MEM_CACHE_BASE_HH__ 1162