base.hh revision 11053
12810SN/A/* 210693SMarco.Balboni@ARM.com * Copyright (c) 2012-2013, 2015 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 414458SN/A * Steve Reinhardt 424458SN/A * Ron Dreslinski 432810SN/A */ 442810SN/A 452810SN/A/** 462810SN/A * @file 472810SN/A * Declares a basic cache interface BaseCache. 482810SN/A */ 492810SN/A 5011051Sandreas.hansson@arm.com#ifndef __MEM_CACHE_BASE_HH__ 5111051Sandreas.hansson@arm.com#define __MEM_CACHE_BASE_HH__ 522810SN/A 537676Snate@binkert.org#include <algorithm> 547676Snate@binkert.org#include <list> 557676Snate@binkert.org#include <string> 562810SN/A#include <vector> 572810SN/A 582825SN/A#include "base/misc.hh" 592810SN/A#include "base/statistics.hh" 602810SN/A#include "base/trace.hh" 616215Snate@binkert.org#include "base/types.hh" 628232Snate@binkert.org#include "debug/Cache.hh" 638232Snate@binkert.org#include "debug/CachePort.hh" 645338Sstever@gmail.com#include "mem/cache/mshr_queue.hh" 652810SN/A#include "mem/mem_object.hh" 662810SN/A#include "mem/packet.hh" 678914Sandreas.hansson@arm.com#include "mem/qport.hh" 688229Snate@binkert.org#include "mem/request.hh" 695034SN/A#include "params/BaseCache.hh" 702811SN/A#include "sim/eventq.hh" 718786Sgblack@eecs.umich.edu#include "sim/full_system.hh" 724626SN/A#include "sim/sim_exit.hh" 738833Sdam.sunwoo@arm.com#include "sim/system.hh" 742810SN/A 753194SN/Aclass MSHR; 762810SN/A/** 772810SN/A * A basic cache interface. Implements some common functions for speed. 782810SN/A */ 792810SN/Aclass BaseCache : public MemObject 802810SN/A{ 814628SN/A /** 824628SN/A * Indexes to enumerate the MSHR queues. 834628SN/A */ 844628SN/A enum MSHRQueueIndex { 854628SN/A MSHRQueue_MSHRs, 864628SN/A MSHRQueue_WriteBuffer 874628SN/A }; 884628SN/A 898737Skoansin.tan@gmail.com public: 904628SN/A /** 914628SN/A * Reasons for caches to be blocked. 924628SN/A */ 934628SN/A enum BlockedCause { 944628SN/A Blocked_NoMSHRs = MSHRQueue_MSHRs, 954628SN/A Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 964628SN/A Blocked_NoTargets, 974628SN/A NUM_BLOCKED_CAUSES 984628SN/A }; 994628SN/A 1008737Skoansin.tan@gmail.com protected: 1014628SN/A 1028856Sandreas.hansson@arm.com /** 1038856Sandreas.hansson@arm.com * A cache master port is used for the memory-side port of the 1048856Sandreas.hansson@arm.com * cache, and in addition to the basic timing port that only sends 1058856Sandreas.hansson@arm.com * response packets through a transmit list, it also offers the 1068856Sandreas.hansson@arm.com * ability to schedule and send request packets (requests & 10710942Sandreas.hansson@arm.com * writebacks). The send event is scheduled through schedSendEvent, 1088856Sandreas.hansson@arm.com * and the sendDeferredPacket of the timing port is modified to 1098856Sandreas.hansson@arm.com * consider both the transmit list and the requests from the MSHR. 1108856Sandreas.hansson@arm.com */ 1118922Swilliam.wang@arm.com class CacheMasterPort : public QueuedMasterPort 1122810SN/A { 1138856Sandreas.hansson@arm.com 1142844SN/A public: 1158856Sandreas.hansson@arm.com 1168856Sandreas.hansson@arm.com /** 1178856Sandreas.hansson@arm.com * Schedule a send of a request packet (from the MSHR). Note 11810713Sandreas.hansson@arm.com * that we could already have a retry outstanding. 1198856Sandreas.hansson@arm.com */ 12010942Sandreas.hansson@arm.com void schedSendEvent(Tick time) 1218856Sandreas.hansson@arm.com { 12210942Sandreas.hansson@arm.com DPRINTF(CachePort, "Scheduling send event at %llu\n", time); 12310713Sandreas.hansson@arm.com reqQueue.schedSendEvent(time); 1248856Sandreas.hansson@arm.com } 1258856Sandreas.hansson@arm.com 1263738SN/A protected: 1274458SN/A 1288856Sandreas.hansson@arm.com CacheMasterPort(const std::string &_name, BaseCache *_cache, 12910713Sandreas.hansson@arm.com ReqPacketQueue &_reqQueue, 13010713Sandreas.hansson@arm.com SnoopRespPacketQueue &_snoopRespQueue) : 13110713Sandreas.hansson@arm.com QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue) 1328914Sandreas.hansson@arm.com { } 1332810SN/A 1348856Sandreas.hansson@arm.com /** 1358856Sandreas.hansson@arm.com * Memory-side port always snoops. 1368856Sandreas.hansson@arm.com * 1378914Sandreas.hansson@arm.com * @return always true 1388856Sandreas.hansson@arm.com */ 1398922Swilliam.wang@arm.com virtual bool isSnooping() const { return true; } 1408856Sandreas.hansson@arm.com }; 1413013SN/A 1428856Sandreas.hansson@arm.com /** 1438856Sandreas.hansson@arm.com * A cache slave port is used for the CPU-side port of the cache, 1448856Sandreas.hansson@arm.com * and it is basically a simple timing port that uses a transmit 1458856Sandreas.hansson@arm.com * list for responses to the CPU (or connected master). In 1468856Sandreas.hansson@arm.com * addition, it has the functionality to block the port for 1478856Sandreas.hansson@arm.com * incoming requests. If blocked, the port will issue a retry once 1488856Sandreas.hansson@arm.com * unblocked. 1498856Sandreas.hansson@arm.com */ 1508922Swilliam.wang@arm.com class CacheSlavePort : public QueuedSlavePort 1518856Sandreas.hansson@arm.com { 1525314SN/A 1532811SN/A public: 1548856Sandreas.hansson@arm.com 1558856Sandreas.hansson@arm.com /** Do not accept any new requests. */ 1562810SN/A void setBlocked(); 1572810SN/A 1588856Sandreas.hansson@arm.com /** Return to normal operation and accept new requests. */ 1592810SN/A void clearBlocked(); 1602810SN/A 16110345SCurtis.Dunham@arm.com bool isBlocked() const { return blocked; } 16210345SCurtis.Dunham@arm.com 1638856Sandreas.hansson@arm.com protected: 1648856Sandreas.hansson@arm.com 1658856Sandreas.hansson@arm.com CacheSlavePort(const std::string &_name, BaseCache *_cache, 1668856Sandreas.hansson@arm.com const std::string &_label); 1673606SN/A 1688914Sandreas.hansson@arm.com /** A normal packet queue used to store responses. */ 16910713Sandreas.hansson@arm.com RespPacketQueue queue; 1708914Sandreas.hansson@arm.com 1712810SN/A bool blocked; 1722810SN/A 1732897SN/A bool mustSendRetry; 1742897SN/A 1758856Sandreas.hansson@arm.com private: 1764458SN/A 17710344Sandreas.hansson@arm.com void processSendRetry(); 17810344Sandreas.hansson@arm.com 17910344Sandreas.hansson@arm.com EventWrapper<CacheSlavePort, 18010344Sandreas.hansson@arm.com &CacheSlavePort::processSendRetry> sendRetryEvent; 1818856Sandreas.hansson@arm.com 1822811SN/A }; 1832810SN/A 1848856Sandreas.hansson@arm.com CacheSlavePort *cpuSidePort; 1858856Sandreas.hansson@arm.com CacheMasterPort *memSidePort; 1863338SN/A 1874626SN/A protected: 1884626SN/A 1894626SN/A /** Miss status registers */ 1904626SN/A MSHRQueue mshrQueue; 1914626SN/A 1924626SN/A /** Write/writeback buffer */ 1934626SN/A MSHRQueue writeBuffer; 1944626SN/A 19510693SMarco.Balboni@ARM.com /** 19610693SMarco.Balboni@ARM.com * Allocate a buffer, passing the time indicating when schedule an 19710693SMarco.Balboni@ARM.com * event to the queued port to go and ask the MSHR and write queue 19810693SMarco.Balboni@ARM.com * if they have packets to send. 19910693SMarco.Balboni@ARM.com * 20010693SMarco.Balboni@ARM.com * allocateBufferInternal() function is called in: 20110693SMarco.Balboni@ARM.com * - MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer); 20210767Sandreas.hansson@arm.com * - MSHR allocateMissBuffer (miss in MSHR queue); 20310693SMarco.Balboni@ARM.com */ 2044628SN/A MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 20510942Sandreas.hansson@arm.com PacketPtr pkt, Tick time, 20610942Sandreas.hansson@arm.com bool sched_send) 2074628SN/A { 20810764Sandreas.hansson@arm.com // check that the address is block aligned since we rely on 20910764Sandreas.hansson@arm.com // this in a number of places when checking for matches and 21010764Sandreas.hansson@arm.com // overlap 21110764Sandreas.hansson@arm.com assert(addr == blockAlign(addr)); 21210764Sandreas.hansson@arm.com 2134666SN/A MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 2144628SN/A 2154628SN/A if (mq->isFull()) { 2164628SN/A setBlocked((BlockedCause)mq->index); 2174628SN/A } 2184628SN/A 21910942Sandreas.hansson@arm.com if (sched_send) 22010942Sandreas.hansson@arm.com // schedule the send 22110942Sandreas.hansson@arm.com schedMemSideSendEvent(time); 2224628SN/A 2234628SN/A return mshr; 2244628SN/A } 2254628SN/A 22610679Sandreas.hansson@arm.com void markInServiceInternal(MSHR *mshr, bool pending_dirty_resp) 2274628SN/A { 2284628SN/A MSHRQueue *mq = mshr->queue; 2294628SN/A bool wasFull = mq->isFull(); 23010679Sandreas.hansson@arm.com mq->markInService(mshr, pending_dirty_resp); 2314628SN/A if (wasFull && !mq->isFull()) { 2324628SN/A clearBlocked((BlockedCause)mq->index); 2334628SN/A } 2344628SN/A } 2354628SN/A 2369347SAndreas.Sandberg@arm.com /** 2379347SAndreas.Sandberg@arm.com * Write back dirty blocks in the cache using functional accesses. 2389347SAndreas.Sandberg@arm.com */ 2399347SAndreas.Sandberg@arm.com virtual void memWriteback() = 0; 2409347SAndreas.Sandberg@arm.com /** 2419347SAndreas.Sandberg@arm.com * Invalidates all blocks in the cache. 2429347SAndreas.Sandberg@arm.com * 2439347SAndreas.Sandberg@arm.com * @warn Dirty cache lines will not be written back to 2449347SAndreas.Sandberg@arm.com * memory. Make sure to call functionalWriteback() first if you 2459347SAndreas.Sandberg@arm.com * want the to write them to memory. 2469347SAndreas.Sandberg@arm.com */ 2479347SAndreas.Sandberg@arm.com virtual void memInvalidate() = 0; 2489347SAndreas.Sandberg@arm.com /** 2499347SAndreas.Sandberg@arm.com * Determine if there are any dirty blocks in the cache. 2509347SAndreas.Sandberg@arm.com * 2519347SAndreas.Sandberg@arm.com * \return true if at least one block is dirty, false otherwise. 2529347SAndreas.Sandberg@arm.com */ 2539347SAndreas.Sandberg@arm.com virtual bool isDirty() const = 0; 2549347SAndreas.Sandberg@arm.com 25510821Sandreas.hansson@arm.com /** 25610821Sandreas.hansson@arm.com * Determine if an address is in the ranges covered by this 25710821Sandreas.hansson@arm.com * cache. This is useful to filter snoops. 25810821Sandreas.hansson@arm.com * 25910821Sandreas.hansson@arm.com * @param addr Address to check against 26010821Sandreas.hansson@arm.com * 26110821Sandreas.hansson@arm.com * @return If the address in question is in range 26210821Sandreas.hansson@arm.com */ 26310821Sandreas.hansson@arm.com bool inRange(Addr addr) const; 26410821Sandreas.hansson@arm.com 2654626SN/A /** Block size of this cache */ 2666227Snate@binkert.org const unsigned blkSize; 2674626SN/A 2684630SN/A /** 26910693SMarco.Balboni@ARM.com * The latency of tag lookup of a cache. It occurs when there is 27010693SMarco.Balboni@ARM.com * an access to the cache. 2714630SN/A */ 27210693SMarco.Balboni@ARM.com const Cycles lookupLatency; 2739263Smrinmoy.ghosh@arm.com 2749263Smrinmoy.ghosh@arm.com /** 27510693SMarco.Balboni@ARM.com * This is the forward latency of the cache. It occurs when there 27610693SMarco.Balboni@ARM.com * is a cache miss and a request is forwarded downstream, in 27710693SMarco.Balboni@ARM.com * particular an outbound miss. 27810693SMarco.Balboni@ARM.com */ 27910693SMarco.Balboni@ARM.com const Cycles forwardLatency; 28010693SMarco.Balboni@ARM.com 28110693SMarco.Balboni@ARM.com /** The latency to fill a cache block */ 28210693SMarco.Balboni@ARM.com const Cycles fillLatency; 28310693SMarco.Balboni@ARM.com 28410693SMarco.Balboni@ARM.com /** 28510693SMarco.Balboni@ARM.com * The latency of sending reponse to its upper level cache/core on 28610693SMarco.Balboni@ARM.com * a linefill. The responseLatency parameter captures this 28710693SMarco.Balboni@ARM.com * latency. 2889263Smrinmoy.ghosh@arm.com */ 2899288Sandreas.hansson@arm.com const Cycles responseLatency; 2904630SN/A 2914626SN/A /** The number of targets for each MSHR. */ 2924626SN/A const int numTarget; 2934626SN/A 2946122SSteve.Reinhardt@amd.com /** Do we forward snoops from mem side port through to cpu side port? */ 2959529Sandreas.hansson@arm.com const bool forwardSnoops; 2964626SN/A 2972810SN/A /** 29810884Sandreas.hansson@arm.com * Is this cache read only, for example the instruction cache, or 29910884Sandreas.hansson@arm.com * table-walker cache. A cache that is read only should never see 30010884Sandreas.hansson@arm.com * any writes, and should never get any dirty data (and hence 30110884Sandreas.hansson@arm.com * never have to do any writebacks). 30210884Sandreas.hansson@arm.com */ 30310884Sandreas.hansson@arm.com const bool isReadOnly; 30410884Sandreas.hansson@arm.com 30510884Sandreas.hansson@arm.com /** 3062810SN/A * Bit vector of the blocking reasons for the access path. 3072810SN/A * @sa #BlockedCause 3082810SN/A */ 3092810SN/A uint8_t blocked; 3102810SN/A 3116122SSteve.Reinhardt@amd.com /** Increasing order number assigned to each incoming request. */ 3126122SSteve.Reinhardt@amd.com uint64_t order; 3136122SSteve.Reinhardt@amd.com 3142810SN/A /** Stores time the cache blocked for statistics. */ 3159288Sandreas.hansson@arm.com Cycles blockedCycle; 3162810SN/A 3174626SN/A /** Pointer to the MSHR that has no targets. */ 3184626SN/A MSHR *noTargetMSHR; 3192810SN/A 3202810SN/A /** The number of misses to trigger an exit event. */ 3212810SN/A Counter missCount; 3222810SN/A 3236122SSteve.Reinhardt@amd.com /** 3246122SSteve.Reinhardt@amd.com * The address range to which the cache responds on the CPU side. 3256122SSteve.Reinhardt@amd.com * Normally this is all possible memory addresses. */ 3269529Sandreas.hansson@arm.com const AddrRangeList addrRanges; 3276122SSteve.Reinhardt@amd.com 3288833Sdam.sunwoo@arm.com public: 3298833Sdam.sunwoo@arm.com /** System we are currently operating in. */ 3308833Sdam.sunwoo@arm.com System *system; 3316978SLisa.Hsu@amd.com 3322810SN/A // Statistics 3332810SN/A /** 3342810SN/A * @addtogroup CacheStatistics 3352810SN/A * @{ 3362810SN/A */ 3372810SN/A 3382810SN/A /** Number of hits per thread for each type of command. @sa Packet::Command */ 3395999Snate@binkert.org Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 3402810SN/A /** Number of hits for demand accesses. */ 3412810SN/A Stats::Formula demandHits; 3422810SN/A /** Number of hit for all accesses. */ 3432810SN/A Stats::Formula overallHits; 3442810SN/A 3452810SN/A /** Number of misses per thread for each type of command. @sa Packet::Command */ 3465999Snate@binkert.org Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 3472810SN/A /** Number of misses for demand accesses. */ 3482810SN/A Stats::Formula demandMisses; 3492810SN/A /** Number of misses for all accesses. */ 3502810SN/A Stats::Formula overallMisses; 3512810SN/A 3522810SN/A /** 3532810SN/A * Total number of cycles per thread/command spent waiting for a miss. 3542810SN/A * Used to calculate the average miss latency. 3552810SN/A */ 3565999Snate@binkert.org Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 3572810SN/A /** Total number of cycles spent waiting for demand misses. */ 3582810SN/A Stats::Formula demandMissLatency; 3592810SN/A /** Total number of cycles spent waiting for all misses. */ 3602810SN/A Stats::Formula overallMissLatency; 3612810SN/A 3622810SN/A /** The number of accesses per command and thread. */ 3634022SN/A Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 3642810SN/A /** The number of demand accesses. */ 3652810SN/A Stats::Formula demandAccesses; 3662810SN/A /** The number of overall accesses. */ 3672810SN/A Stats::Formula overallAccesses; 3682810SN/A 3692810SN/A /** The miss rate per command and thread. */ 3704022SN/A Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 3712810SN/A /** The miss rate of all demand accesses. */ 3722810SN/A Stats::Formula demandMissRate; 3732810SN/A /** The miss rate for all accesses. */ 3742810SN/A Stats::Formula overallMissRate; 3752810SN/A 3762810SN/A /** The average miss latency per command and thread. */ 3774022SN/A Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 3782810SN/A /** The average miss latency for demand misses. */ 3792810SN/A Stats::Formula demandAvgMissLatency; 3802810SN/A /** The average miss latency for all misses. */ 3812810SN/A Stats::Formula overallAvgMissLatency; 3822810SN/A 3832810SN/A /** The total number of cycles blocked for each blocked cause. */ 3845999Snate@binkert.org Stats::Vector blocked_cycles; 3852810SN/A /** The number of times this cache blocked for each blocked cause. */ 3865999Snate@binkert.org Stats::Vector blocked_causes; 3872810SN/A 3882810SN/A /** The average number of cycles blocked for each blocked cause. */ 3892810SN/A Stats::Formula avg_blocked; 3902810SN/A 3912810SN/A /** The number of fast writes (WH64) performed. */ 3925999Snate@binkert.org Stats::Scalar fastWrites; 3932810SN/A 3942810SN/A /** The number of cache copies performed. */ 3955999Snate@binkert.org Stats::Scalar cacheCopies; 3962810SN/A 3974626SN/A /** Number of blocks written back per thread. */ 3985999Snate@binkert.org Stats::Vector writebacks; 3994626SN/A 4004626SN/A /** Number of misses that hit in the MSHRs per command and thread. */ 4015999Snate@binkert.org Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 4024626SN/A /** Demand misses that hit in the MSHRs. */ 4034626SN/A Stats::Formula demandMshrHits; 4044626SN/A /** Total number of misses that hit in the MSHRs. */ 4054626SN/A Stats::Formula overallMshrHits; 4064626SN/A 4074626SN/A /** Number of misses that miss in the MSHRs, per command and thread. */ 4085999Snate@binkert.org Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 4094626SN/A /** Demand misses that miss in the MSHRs. */ 4104626SN/A Stats::Formula demandMshrMisses; 4114626SN/A /** Total number of misses that miss in the MSHRs. */ 4124626SN/A Stats::Formula overallMshrMisses; 4134626SN/A 4144626SN/A /** Number of misses that miss in the MSHRs, per command and thread. */ 4155999Snate@binkert.org Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 4164626SN/A /** Total number of misses that miss in the MSHRs. */ 4174626SN/A Stats::Formula overallMshrUncacheable; 4184626SN/A 4194626SN/A /** Total cycle latency of each MSHR miss, per command and thread. */ 4205999Snate@binkert.org Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 4214626SN/A /** Total cycle latency of demand MSHR misses. */ 4224626SN/A Stats::Formula demandMshrMissLatency; 4234626SN/A /** Total cycle latency of overall MSHR misses. */ 4244626SN/A Stats::Formula overallMshrMissLatency; 4254626SN/A 4264626SN/A /** Total cycle latency of each MSHR miss, per command and thread. */ 4275999Snate@binkert.org Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 4284626SN/A /** Total cycle latency of overall MSHR misses. */ 4294626SN/A Stats::Formula overallMshrUncacheableLatency; 4304626SN/A 4317461Snate@binkert.org#if 0 4324626SN/A /** The total number of MSHR accesses per command and thread. */ 4334626SN/A Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 4344626SN/A /** The total number of demand MSHR accesses. */ 4354626SN/A Stats::Formula demandMshrAccesses; 4364626SN/A /** The total number of MSHR accesses. */ 4374626SN/A Stats::Formula overallMshrAccesses; 4387461Snate@binkert.org#endif 4394626SN/A 4404626SN/A /** The miss rate in the MSHRs pre command and thread. */ 4414626SN/A Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 4424626SN/A /** The demand miss rate in the MSHRs. */ 4434626SN/A Stats::Formula demandMshrMissRate; 4444626SN/A /** The overall miss rate in the MSHRs. */ 4454626SN/A Stats::Formula overallMshrMissRate; 4464626SN/A 4474626SN/A /** The average latency of an MSHR miss, per command and thread. */ 4484626SN/A Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 4494626SN/A /** The average latency of a demand MSHR miss. */ 4504626SN/A Stats::Formula demandAvgMshrMissLatency; 4514626SN/A /** The average overall latency of an MSHR miss. */ 4524626SN/A Stats::Formula overallAvgMshrMissLatency; 4534626SN/A 4544626SN/A /** The average latency of an MSHR miss, per command and thread. */ 4554626SN/A Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 4564626SN/A /** The average overall latency of an MSHR miss. */ 4574626SN/A Stats::Formula overallAvgMshrUncacheableLatency; 4584626SN/A 4594626SN/A /** The number of times a thread hit its MSHR cap. */ 4605999Snate@binkert.org Stats::Vector mshr_cap_events; 4614626SN/A /** The number of times software prefetches caused the MSHR to block. */ 4625999Snate@binkert.org Stats::Vector soft_prefetch_mshr_full; 4634626SN/A 4645999Snate@binkert.org Stats::Scalar mshr_no_allocate_misses; 4654626SN/A 4662810SN/A /** 4672810SN/A * @} 4682810SN/A */ 4692810SN/A 4702810SN/A /** 4712810SN/A * Register stats for this object. 4722810SN/A */ 4732810SN/A virtual void regStats(); 4742810SN/A 4752810SN/A public: 47611053Sandreas.hansson@arm.com BaseCache(const BaseCacheParams *p, unsigned blk_size); 4775034SN/A ~BaseCache() {} 4783606SN/A 4792858SN/A virtual void init(); 4802858SN/A 4819294Sandreas.hansson@arm.com virtual BaseMasterPort &getMasterPort(const std::string &if_name, 4829294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 4839294Sandreas.hansson@arm.com virtual BaseSlavePort &getSlavePort(const std::string &if_name, 4849294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 4858922Swilliam.wang@arm.com 4862810SN/A /** 4872810SN/A * Query block size of a cache. 4882810SN/A * @return The block size 4892810SN/A */ 4906227Snate@binkert.org unsigned 4916227Snate@binkert.org getBlockSize() const 4922810SN/A { 4932810SN/A return blkSize; 4942810SN/A } 4952810SN/A 4964626SN/A 4976666Ssteve.reinhardt@amd.com Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 4984626SN/A 4994626SN/A 5008883SAli.Saidi@ARM.com const AddrRangeList &getAddrRanges() const { return addrRanges; } 5016122SSteve.Reinhardt@amd.com 50210942Sandreas.hansson@arm.com MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true) 5034628SN/A { 5044628SN/A return allocateBufferInternal(&mshrQueue, 5054628SN/A blockAlign(pkt->getAddr()), blkSize, 50610942Sandreas.hansson@arm.com pkt, time, sched_send); 5074628SN/A } 5084628SN/A 50910942Sandreas.hansson@arm.com MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time) 5104628SN/A { 51110884Sandreas.hansson@arm.com // should only see clean evictions in a read-only cache 51210884Sandreas.hansson@arm.com assert(!isReadOnly || pkt->cmd == MemCmd::CleanEvict); 5134902SN/A assert(pkt->isWrite() && !pkt->isRead()); 5144902SN/A return allocateBufferInternal(&writeBuffer, 51510764Sandreas.hansson@arm.com blockAlign(pkt->getAddr()), blkSize, 51610942Sandreas.hansson@arm.com pkt, time, true); 5174628SN/A } 5184628SN/A 5192810SN/A /** 5202810SN/A * Returns true if the cache is blocked for accesses. 5212810SN/A */ 5229529Sandreas.hansson@arm.com bool isBlocked() const 5232810SN/A { 5242810SN/A return blocked != 0; 5252810SN/A } 5262810SN/A 5272810SN/A /** 5282810SN/A * Marks the access path of the cache as blocked for the given cause. This 5292810SN/A * also sets the blocked flag in the slave interface. 5302810SN/A * @param cause The reason for the cache blocking. 5312810SN/A */ 5322810SN/A void setBlocked(BlockedCause cause) 5332810SN/A { 5342810SN/A uint8_t flag = 1 << cause; 5352810SN/A if (blocked == 0) { 5362810SN/A blocked_causes[cause]++; 5379288Sandreas.hansson@arm.com blockedCycle = curCycle(); 5384630SN/A cpuSidePort->setBlocked(); 5392810SN/A } 5404630SN/A blocked |= flag; 5414630SN/A DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 5422810SN/A } 5432810SN/A 5442810SN/A /** 5452810SN/A * Marks the cache as unblocked for the given cause. This also clears the 5462810SN/A * blocked flags in the appropriate interfaces. 5472810SN/A * @param cause The newly unblocked cause. 5482810SN/A * @warning Calling this function can cause a blocked request on the bus to 5492810SN/A * access the cache. The cache must be in a state to handle that request. 5502810SN/A */ 5512810SN/A void clearBlocked(BlockedCause cause) 5522810SN/A { 5532810SN/A uint8_t flag = 1 << cause; 5544630SN/A blocked &= ~flag; 5554630SN/A DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 5564630SN/A if (blocked == 0) { 5579288Sandreas.hansson@arm.com blocked_cycles[cause] += curCycle() - blockedCycle; 5584630SN/A cpuSidePort->clearBlocked(); 5592810SN/A } 5602810SN/A } 5612810SN/A 5622810SN/A /** 56310942Sandreas.hansson@arm.com * Schedule a send event for the memory-side port. If already 56410942Sandreas.hansson@arm.com * scheduled, this may reschedule the event at an earlier 56510942Sandreas.hansson@arm.com * time. When the specified time is reached, the port is free to 56610942Sandreas.hansson@arm.com * send either a response, a request, or a prefetch request. 56710942Sandreas.hansson@arm.com * 56810942Sandreas.hansson@arm.com * @param time The time when to attempt sending a packet. 5692810SN/A */ 57010942Sandreas.hansson@arm.com void schedMemSideSendEvent(Tick time) 5712810SN/A { 57210942Sandreas.hansson@arm.com memSidePort->schedSendEvent(time); 5732811SN/A } 5743503SN/A 57510028SGiacomo.Gabrielli@arm.com virtual bool inCache(Addr addr, bool is_secure) const = 0; 5764626SN/A 57710028SGiacomo.Gabrielli@arm.com virtual bool inMissQueue(Addr addr, bool is_secure) const = 0; 5784626SN/A 5798833Sdam.sunwoo@arm.com void incMissCount(PacketPtr pkt) 5803503SN/A { 5818833Sdam.sunwoo@arm.com assert(pkt->req->masterId() < system->maxMasters()); 5828833Sdam.sunwoo@arm.com misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 58310020Smatt.horsnell@ARM.com pkt->req->incAccessDepth(); 5844626SN/A if (missCount) { 5854626SN/A --missCount; 5864626SN/A if (missCount == 0) 5874626SN/A exitSimLoop("A cache reached the maximum miss count"); 5883503SN/A } 5893503SN/A } 5908833Sdam.sunwoo@arm.com void incHitCount(PacketPtr pkt) 5916978SLisa.Hsu@amd.com { 5928833Sdam.sunwoo@arm.com assert(pkt->req->masterId() < system->maxMasters()); 5938833Sdam.sunwoo@arm.com hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 5946978SLisa.Hsu@amd.com 5956978SLisa.Hsu@amd.com } 5963503SN/A 5972810SN/A}; 5982810SN/A 59911051Sandreas.hansson@arm.com#endif //__MEM_CACHE_BASE_HH__ 600