base.cc revision 13222
1/* 2 * Copyright (c) 2012-2013, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Nikos Nikoleris 42 */ 43 44/** 45 * @file 46 * Definition of BaseCache functions. 47 */ 48 49#include "mem/cache/base.hh" 50 51#include "base/compiler.hh" 52#include "base/logging.hh" 53#include "debug/Cache.hh" 54#include "debug/CachePort.hh" 55#include "debug/CacheRepl.hh" 56#include "debug/CacheVerbose.hh" 57#include "mem/cache/mshr.hh" 58#include "mem/cache/prefetch/base.hh" 59#include "mem/cache/queue_entry.hh" 60#include "params/BaseCache.hh" 61#include "sim/core.hh" 62 63class BaseMasterPort; 64class BaseSlavePort; 65 66using namespace std; 67 68BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 69 BaseCache *_cache, 70 const std::string &_label) 71 : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 72 blocked(false), mustSendRetry(false), 73 sendRetryEvent([this]{ processSendRetry(); }, _name) 74{ 75} 76 77BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) 78 : MemObject(p), 79 cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"), 80 memSidePort(p->name + ".mem_side", this, "MemSidePort"), 81 mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below 82 writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below 83 tags(p->tags), 84 prefetcher(p->prefetcher), 85 prefetchOnAccess(p->prefetch_on_access), 86 writebackClean(p->writeback_clean), 87 tempBlockWriteback(nullptr), 88 writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); }, 89 name(), false, 90 EventBase::Delayed_Writeback_Pri), 91 blkSize(blk_size), 92 lookupLatency(p->tag_latency), 93 dataLatency(p->data_latency), 94 forwardLatency(p->tag_latency), 95 fillLatency(p->data_latency), 96 responseLatency(p->response_latency), 97 numTarget(p->tgts_per_mshr), 98 forwardSnoops(true), 99 clusivity(p->clusivity), 100 isReadOnly(p->is_read_only), 101 blocked(0), 102 order(0), 103 noTargetMSHR(nullptr), 104 missCount(p->max_miss_count), 105 addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 106 system(p->system) 107{ 108 // the MSHR queue has no reserve entries as we check the MSHR 109 // queue on every single allocation, whereas the write queue has 110 // as many reserve entries as we have MSHRs, since every MSHR may 111 // eventually require a writeback, and we do not check the write 112 // buffer before committing to an MSHR 113 114 // forward snoops is overridden in init() once we can query 115 // whether the connected master is actually snooping or not 116 117 tempBlock = new TempCacheBlk(blkSize); 118 119 tags->init(this); 120 if (prefetcher) 121 prefetcher->setCache(this); 122} 123 124BaseCache::~BaseCache() 125{ 126 delete tempBlock; 127} 128 129void 130BaseCache::CacheSlavePort::setBlocked() 131{ 132 assert(!blocked); 133 DPRINTF(CachePort, "Port is blocking new requests\n"); 134 blocked = true; 135 // if we already scheduled a retry in this cycle, but it has not yet 136 // happened, cancel it 137 if (sendRetryEvent.scheduled()) { 138 owner.deschedule(sendRetryEvent); 139 DPRINTF(CachePort, "Port descheduled retry\n"); 140 mustSendRetry = true; 141 } 142} 143 144void 145BaseCache::CacheSlavePort::clearBlocked() 146{ 147 assert(blocked); 148 DPRINTF(CachePort, "Port is accepting new requests\n"); 149 blocked = false; 150 if (mustSendRetry) { 151 // @TODO: need to find a better time (next cycle?) 152 owner.schedule(sendRetryEvent, curTick() + 1); 153 } 154} 155 156void 157BaseCache::CacheSlavePort::processSendRetry() 158{ 159 DPRINTF(CachePort, "Port is sending retry\n"); 160 161 // reset the flag and call retry 162 mustSendRetry = false; 163 sendRetryReq(); 164} 165 166Addr 167BaseCache::regenerateBlkAddr(CacheBlk* blk) 168{ 169 if (blk != tempBlock) { 170 return tags->regenerateBlkAddr(blk); 171 } else { 172 return tempBlock->getAddr(); 173 } 174} 175 176void 177BaseCache::init() 178{ 179 if (!cpuSidePort.isConnected() || !memSidePort.isConnected()) 180 fatal("Cache ports on %s are not connected\n", name()); 181 cpuSidePort.sendRangeChange(); 182 forwardSnoops = cpuSidePort.isSnooping(); 183} 184 185BaseMasterPort & 186BaseCache::getMasterPort(const std::string &if_name, PortID idx) 187{ 188 if (if_name == "mem_side") { 189 return memSidePort; 190 } else { 191 return MemObject::getMasterPort(if_name, idx); 192 } 193} 194 195BaseSlavePort & 196BaseCache::getSlavePort(const std::string &if_name, PortID idx) 197{ 198 if (if_name == "cpu_side") { 199 return cpuSidePort; 200 } else { 201 return MemObject::getSlavePort(if_name, idx); 202 } 203} 204 205bool 206BaseCache::inRange(Addr addr) const 207{ 208 for (const auto& r : addrRanges) { 209 if (r.contains(addr)) { 210 return true; 211 } 212 } 213 return false; 214} 215 216void 217BaseCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) 218{ 219 if (pkt->needsResponse()) { 220 pkt->makeTimingResponse(); 221 // @todo: Make someone pay for this 222 pkt->headerDelay = pkt->payloadDelay = 0; 223 224 // In this case we are considering request_time that takes 225 // into account the delay of the xbar, if any, and just 226 // lat, neglecting responseLatency, modelling hit latency 227 // just as lookupLatency or or the value of lat overriden 228 // by access(), that calls accessBlock() function. 229 cpuSidePort.schedTimingResp(pkt, request_time, true); 230 } else { 231 DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, 232 pkt->print()); 233 234 // queue the packet for deletion, as the sending cache is 235 // still relying on it; if the block is found in access(), 236 // CleanEvict and Writeback messages will be deleted 237 // here as well 238 pendingDelete.reset(pkt); 239 } 240} 241 242void 243BaseCache::handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk, 244 Tick forward_time, Tick request_time) 245{ 246 if (mshr) { 247 /// MSHR hit 248 /// @note writebacks will be checked in getNextMSHR() 249 /// for any conflicting requests to the same block 250 251 //@todo remove hw_pf here 252 253 // Coalesce unless it was a software prefetch (see above). 254 if (pkt) { 255 assert(!pkt->isWriteback()); 256 // CleanEvicts corresponding to blocks which have 257 // outstanding requests in MSHRs are simply sunk here 258 if (pkt->cmd == MemCmd::CleanEvict) { 259 pendingDelete.reset(pkt); 260 } else if (pkt->cmd == MemCmd::WriteClean) { 261 // A WriteClean should never coalesce with any 262 // outstanding cache maintenance requests. 263 264 // We use forward_time here because there is an 265 // uncached memory write, forwarded to WriteBuffer. 266 allocateWriteBuffer(pkt, forward_time); 267 } else { 268 DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__, 269 pkt->print()); 270 271 assert(pkt->req->masterId() < system->maxMasters()); 272 mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 273 274 // We use forward_time here because it is the same 275 // considering new targets. We have multiple 276 // requests for the same address here. It 277 // specifies the latency to allocate an internal 278 // buffer and to schedule an event to the queued 279 // port and also takes into account the additional 280 // delay of the xbar. 281 mshr->allocateTarget(pkt, forward_time, order++, 282 allocOnFill(pkt->cmd)); 283 if (mshr->getNumTargets() == numTarget) { 284 noTargetMSHR = mshr; 285 setBlocked(Blocked_NoTargets); 286 // need to be careful with this... if this mshr isn't 287 // ready yet (i.e. time > curTick()), we don't want to 288 // move it ahead of mshrs that are ready 289 // mshrQueue.moveToFront(mshr); 290 } 291 } 292 } 293 } else { 294 // no MSHR 295 assert(pkt->req->masterId() < system->maxMasters()); 296 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 297 298 if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean) { 299 // We use forward_time here because there is an 300 // writeback or writeclean, forwarded to WriteBuffer. 301 allocateWriteBuffer(pkt, forward_time); 302 } else { 303 if (blk && blk->isValid()) { 304 // If we have a write miss to a valid block, we 305 // need to mark the block non-readable. Otherwise 306 // if we allow reads while there's an outstanding 307 // write miss, the read could return stale data 308 // out of the cache block... a more aggressive 309 // system could detect the overlap (if any) and 310 // forward data out of the MSHRs, but we don't do 311 // that yet. Note that we do need to leave the 312 // block valid so that it stays in the cache, in 313 // case we get an upgrade response (and hence no 314 // new data) when the write miss completes. 315 // As long as CPUs do proper store/load forwarding 316 // internally, and have a sufficiently weak memory 317 // model, this is probably unnecessary, but at some 318 // point it must have seemed like we needed it... 319 assert((pkt->needsWritable() && !blk->isWritable()) || 320 pkt->req->isCacheMaintenance()); 321 blk->status &= ~BlkReadable; 322 } 323 // Here we are using forward_time, modelling the latency of 324 // a miss (outbound) just as forwardLatency, neglecting the 325 // lookupLatency component. 326 allocateMissBuffer(pkt, forward_time); 327 } 328 } 329} 330 331void 332BaseCache::recvTimingReq(PacketPtr pkt) 333{ 334 // anything that is merely forwarded pays for the forward latency and 335 // the delay provided by the crossbar 336 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 337 338 // We use lookupLatency here because it is used to specify the latency 339 // to access. 340 Cycles lat = lookupLatency; 341 CacheBlk *blk = nullptr; 342 bool satisfied = false; 343 { 344 PacketList writebacks; 345 // Note that lat is passed by reference here. The function 346 // access() calls accessBlock() which can modify lat value. 347 satisfied = access(pkt, blk, lat, writebacks); 348 349 // copy writebacks to write buffer here to ensure they logically 350 // precede anything happening below 351 doWritebacks(writebacks, forward_time); 352 } 353 354 // Here we charge the headerDelay that takes into account the latencies 355 // of the bus, if the packet comes from it. 356 // The latency charged it is just lat that is the value of lookupLatency 357 // modified by access() function, or if not just lookupLatency. 358 // In case of a hit we are neglecting response latency. 359 // In case of a miss we are neglecting forward latency. 360 Tick request_time = clockEdge(lat) + pkt->headerDelay; 361 // Here we reset the timing of the packet. 362 pkt->headerDelay = pkt->payloadDelay = 0; 363 // track time of availability of next prefetch, if any 364 Tick next_pf_time = MaxTick; 365 366 if (satisfied) { 367 // if need to notify the prefetcher we have to do it before 368 // anything else as later handleTimingReqHit might turn the 369 // packet in a response 370 if (prefetcher && 371 (prefetchOnAccess || (blk && blk->wasPrefetched()))) { 372 if (blk) 373 blk->status &= ~BlkHWPrefetched; 374 375 // Don't notify on SWPrefetch 376 if (!pkt->cmd.isSWPrefetch()) { 377 assert(!pkt->req->isCacheMaintenance()); 378 next_pf_time = prefetcher->notify(pkt); 379 } 380 } 381 382 handleTimingReqHit(pkt, blk, request_time); 383 } else { 384 handleTimingReqMiss(pkt, blk, forward_time, request_time); 385 386 // We should call the prefetcher reguardless if the request is 387 // satisfied or not, reguardless if the request is in the MSHR 388 // or not. The request could be a ReadReq hit, but still not 389 // satisfied (potentially because of a prior write to the same 390 // cache line. So, even when not satisfied, there is an MSHR 391 // already allocated for this, we need to let the prefetcher 392 // know about the request 393 394 // Don't notify prefetcher on SWPrefetch or cache maintenance 395 // operations 396 if (prefetcher && pkt && 397 !pkt->cmd.isSWPrefetch() && 398 !pkt->req->isCacheMaintenance()) { 399 next_pf_time = prefetcher->notify(pkt); 400 } 401 } 402 403 if (next_pf_time != MaxTick) { 404 schedMemSideSendEvent(next_pf_time); 405 } 406} 407 408void 409BaseCache::handleUncacheableWriteResp(PacketPtr pkt) 410{ 411 Tick completion_time = clockEdge(responseLatency) + 412 pkt->headerDelay + pkt->payloadDelay; 413 414 // Reset the bus additional time as it is now accounted for 415 pkt->headerDelay = pkt->payloadDelay = 0; 416 417 cpuSidePort.schedTimingResp(pkt, completion_time, true); 418} 419 420void 421BaseCache::recvTimingResp(PacketPtr pkt) 422{ 423 assert(pkt->isResponse()); 424 425 // all header delay should be paid for by the crossbar, unless 426 // this is a prefetch response from above 427 panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 428 "%s saw a non-zero packet delay\n", name()); 429 430 const bool is_error = pkt->isError(); 431 432 if (is_error) { 433 DPRINTF(Cache, "%s: Cache received %s with error\n", __func__, 434 pkt->print()); 435 } 436 437 DPRINTF(Cache, "%s: Handling response %s\n", __func__, 438 pkt->print()); 439 440 // if this is a write, we should be looking at an uncacheable 441 // write 442 if (pkt->isWrite()) { 443 assert(pkt->req->isUncacheable()); 444 handleUncacheableWriteResp(pkt); 445 return; 446 } 447 448 // we have dealt with any (uncacheable) writes above, from here on 449 // we know we are dealing with an MSHR due to a miss or a prefetch 450 MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState()); 451 assert(mshr); 452 453 if (mshr == noTargetMSHR) { 454 // we always clear at least one target 455 clearBlocked(Blocked_NoTargets); 456 noTargetMSHR = nullptr; 457 } 458 459 // Initial target is used just for stats 460 MSHR::Target *initial_tgt = mshr->getTarget(); 461 int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 462 Tick miss_latency = curTick() - initial_tgt->recvTime; 463 464 if (pkt->req->isUncacheable()) { 465 assert(pkt->req->masterId() < system->maxMasters()); 466 mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 467 miss_latency; 468 } else { 469 assert(pkt->req->masterId() < system->maxMasters()); 470 mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 471 miss_latency; 472 } 473 474 PacketList writebacks; 475 476 bool is_fill = !mshr->isForward && 477 (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 478 479 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 480 481 if (is_fill && !is_error) { 482 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 483 pkt->getAddr()); 484 485 blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill()); 486 assert(blk != nullptr); 487 } 488 489 if (blk && blk->isValid() && pkt->isClean() && !pkt->isInvalidate()) { 490 // The block was marked not readable while there was a pending 491 // cache maintenance operation, restore its flag. 492 blk->status |= BlkReadable; 493 494 // This was a cache clean operation (without invalidate) 495 // and we have a copy of the block already. Since there 496 // is no invalidation, we can promote targets that don't 497 // require a writable copy 498 mshr->promoteReadable(); 499 } 500 501 if (blk && blk->isWritable() && !pkt->req->isCacheInvalidate()) { 502 // If at this point the referenced block is writable and the 503 // response is not a cache invalidate, we promote targets that 504 // were deferred as we couldn't guarrantee a writable copy 505 mshr->promoteWritable(); 506 } 507 508 serviceMSHRTargets(mshr, pkt, blk, writebacks); 509 510 if (mshr->promoteDeferredTargets()) { 511 // avoid later read getting stale data while write miss is 512 // outstanding.. see comment in timingAccess() 513 if (blk) { 514 blk->status &= ~BlkReadable; 515 } 516 mshrQueue.markPending(mshr); 517 schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 518 } else { 519 // while we deallocate an mshr from the queue we still have to 520 // check the isFull condition before and after as we might 521 // have been using the reserved entries already 522 const bool was_full = mshrQueue.isFull(); 523 mshrQueue.deallocate(mshr); 524 if (was_full && !mshrQueue.isFull()) { 525 clearBlocked(Blocked_NoMSHRs); 526 } 527 528 // Request the bus for a prefetch if this deallocation freed enough 529 // MSHRs for a prefetch to take place 530 if (prefetcher && mshrQueue.canPrefetch()) { 531 Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 532 clockEdge()); 533 if (next_pf_time != MaxTick) 534 schedMemSideSendEvent(next_pf_time); 535 } 536 } 537 538 // if we used temp block, check to see if its valid and then clear it out 539 if (blk == tempBlock && tempBlock->isValid()) { 540 evictBlock(blk, writebacks); 541 } 542 543 const Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 544 // copy writebacks to write buffer 545 doWritebacks(writebacks, forward_time); 546 547 DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print()); 548 delete pkt; 549} 550 551 552Tick 553BaseCache::recvAtomic(PacketPtr pkt) 554{ 555 // We are in atomic mode so we pay just for lookupLatency here. 556 Cycles lat = lookupLatency; 557 558 // follow the same flow as in recvTimingReq, and check if a cache 559 // above us is responding 560 if (pkt->cacheResponding() && !pkt->isClean()) { 561 assert(!pkt->req->isCacheInvalidate()); 562 DPRINTF(Cache, "Cache above responding to %s: not responding\n", 563 pkt->print()); 564 565 // if a cache is responding, and it had the line in Owned 566 // rather than Modified state, we need to invalidate any 567 // copies that are not on the same path to memory 568 assert(pkt->needsWritable() && !pkt->responderHadWritable()); 569 lat += ticksToCycles(memSidePort.sendAtomic(pkt)); 570 571 return lat * clockPeriod(); 572 } 573 574 // should assert here that there are no outstanding MSHRs or 575 // writebacks... that would mean that someone used an atomic 576 // access in timing mode 577 578 CacheBlk *blk = nullptr; 579 PacketList writebacks; 580 bool satisfied = access(pkt, blk, lat, writebacks); 581 582 if (pkt->isClean() && blk && blk->isDirty()) { 583 // A cache clean opearation is looking for a dirty 584 // block. If a dirty block is encountered a WriteClean 585 // will update any copies to the path to the memory 586 // until the point of reference. 587 DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 588 __func__, pkt->print(), blk->print()); 589 PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 590 writebacks.push_back(wb_pkt); 591 pkt->setSatisfied(); 592 } 593 594 // handle writebacks resulting from the access here to ensure they 595 // logically precede anything happening below 596 doWritebacksAtomic(writebacks); 597 assert(writebacks.empty()); 598 599 if (!satisfied) { 600 lat += handleAtomicReqMiss(pkt, blk, writebacks); 601 } 602 603 // Note that we don't invoke the prefetcher at all in atomic mode. 604 // It's not clear how to do it properly, particularly for 605 // prefetchers that aggressively generate prefetch candidates and 606 // rely on bandwidth contention to throttle them; these will tend 607 // to pollute the cache in atomic mode since there is no bandwidth 608 // contention. If we ever do want to enable prefetching in atomic 609 // mode, though, this is the place to do it... see timingAccess() 610 // for an example (though we'd want to issue the prefetch(es) 611 // immediately rather than calling requestMemSideBus() as we do 612 // there). 613 614 // do any writebacks resulting from the response handling 615 doWritebacksAtomic(writebacks); 616 617 // if we used temp block, check to see if its valid and if so 618 // clear it out, but only do so after the call to recvAtomic is 619 // finished so that any downstream observers (such as a snoop 620 // filter), first see the fill, and only then see the eviction 621 if (blk == tempBlock && tempBlock->isValid()) { 622 // the atomic CPU calls recvAtomic for fetch and load/store 623 // sequentuially, and we may already have a tempBlock 624 // writeback from the fetch that we have not yet sent 625 if (tempBlockWriteback) { 626 // if that is the case, write the prevoius one back, and 627 // do not schedule any new event 628 writebackTempBlockAtomic(); 629 } else { 630 // the writeback/clean eviction happens after the call to 631 // recvAtomic has finished (but before any successive 632 // calls), so that the response handling from the fill is 633 // allowed to happen first 634 schedule(writebackTempBlockAtomicEvent, curTick()); 635 } 636 637 tempBlockWriteback = evictBlock(blk); 638 } 639 640 if (pkt->needsResponse()) { 641 pkt->makeAtomicResponse(); 642 } 643 644 return lat * clockPeriod(); 645} 646 647void 648BaseCache::functionalAccess(PacketPtr pkt, bool from_cpu_side) 649{ 650 Addr blk_addr = pkt->getBlockAddr(blkSize); 651 bool is_secure = pkt->isSecure(); 652 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 653 MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 654 655 pkt->pushLabel(name()); 656 657 CacheBlkPrintWrapper cbpw(blk); 658 659 // Note that just because an L2/L3 has valid data doesn't mean an 660 // L1 doesn't have a more up-to-date modified copy that still 661 // needs to be found. As a result we always update the request if 662 // we have it, but only declare it satisfied if we are the owner. 663 664 // see if we have data at all (owned or otherwise) 665 bool have_data = blk && blk->isValid() 666 && pkt->trySatisfyFunctional(&cbpw, blk_addr, is_secure, blkSize, 667 blk->data); 668 669 // data we have is dirty if marked as such or if we have an 670 // in-service MSHR that is pending a modified line 671 bool have_dirty = 672 have_data && (blk->isDirty() || 673 (mshr && mshr->inService && mshr->isPendingModified())); 674 675 bool done = have_dirty || 676 cpuSidePort.trySatisfyFunctional(pkt) || 677 mshrQueue.trySatisfyFunctional(pkt, blk_addr) || 678 writeBuffer.trySatisfyFunctional(pkt, blk_addr) || 679 memSidePort.trySatisfyFunctional(pkt); 680 681 DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(), 682 (blk && blk->isValid()) ? "valid " : "", 683 have_data ? "data " : "", done ? "done " : ""); 684 685 // We're leaving the cache, so pop cache->name() label 686 pkt->popLabel(); 687 688 if (done) { 689 pkt->makeResponse(); 690 } else { 691 // if it came as a request from the CPU side then make sure it 692 // continues towards the memory side 693 if (from_cpu_side) { 694 memSidePort.sendFunctional(pkt); 695 } else if (cpuSidePort.isSnooping()) { 696 // if it came from the memory side, it must be a snoop request 697 // and we should only forward it if we are forwarding snoops 698 cpuSidePort.sendFunctionalSnoop(pkt); 699 } 700 } 701} 702 703 704void 705BaseCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 706{ 707 assert(pkt->isRequest()); 708 709 uint64_t overwrite_val; 710 bool overwrite_mem; 711 uint64_t condition_val64; 712 uint32_t condition_val32; 713 714 int offset = pkt->getOffset(blkSize); 715 uint8_t *blk_data = blk->data + offset; 716 717 assert(sizeof(uint64_t) >= pkt->getSize()); 718 719 overwrite_mem = true; 720 // keep a copy of our possible write value, and copy what is at the 721 // memory address into the packet 722 pkt->writeData((uint8_t *)&overwrite_val); 723 pkt->setData(blk_data); 724 725 if (pkt->req->isCondSwap()) { 726 if (pkt->getSize() == sizeof(uint64_t)) { 727 condition_val64 = pkt->req->getExtraData(); 728 overwrite_mem = !std::memcmp(&condition_val64, blk_data, 729 sizeof(uint64_t)); 730 } else if (pkt->getSize() == sizeof(uint32_t)) { 731 condition_val32 = (uint32_t)pkt->req->getExtraData(); 732 overwrite_mem = !std::memcmp(&condition_val32, blk_data, 733 sizeof(uint32_t)); 734 } else 735 panic("Invalid size for conditional read/write\n"); 736 } 737 738 if (overwrite_mem) { 739 std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 740 blk->status |= BlkDirty; 741 } 742} 743 744QueueEntry* 745BaseCache::getNextQueueEntry() 746{ 747 // Check both MSHR queue and write buffer for potential requests, 748 // note that null does not mean there is no request, it could 749 // simply be that it is not ready 750 MSHR *miss_mshr = mshrQueue.getNext(); 751 WriteQueueEntry *wq_entry = writeBuffer.getNext(); 752 753 // If we got a write buffer request ready, first priority is a 754 // full write buffer, otherwise we favour the miss requests 755 if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) { 756 // need to search MSHR queue for conflicting earlier miss. 757 MSHR *conflict_mshr = 758 mshrQueue.findPending(wq_entry->blkAddr, 759 wq_entry->isSecure); 760 761 if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 762 // Service misses in order until conflict is cleared. 763 return conflict_mshr; 764 765 // @todo Note that we ignore the ready time of the conflict here 766 } 767 768 // No conflicts; issue write 769 return wq_entry; 770 } else if (miss_mshr) { 771 // need to check for conflicting earlier writeback 772 WriteQueueEntry *conflict_mshr = 773 writeBuffer.findPending(miss_mshr->blkAddr, 774 miss_mshr->isSecure); 775 if (conflict_mshr) { 776 // not sure why we don't check order here... it was in the 777 // original code but commented out. 778 779 // The only way this happens is if we are 780 // doing a write and we didn't have permissions 781 // then subsequently saw a writeback (owned got evicted) 782 // We need to make sure to perform the writeback first 783 // To preserve the dirty data, then we can issue the write 784 785 // should we return wq_entry here instead? I.e. do we 786 // have to flush writes in order? I don't think so... not 787 // for Alpha anyway. Maybe for x86? 788 return conflict_mshr; 789 790 // @todo Note that we ignore the ready time of the conflict here 791 } 792 793 // No conflicts; issue read 794 return miss_mshr; 795 } 796 797 // fall through... no pending requests. Try a prefetch. 798 assert(!miss_mshr && !wq_entry); 799 if (prefetcher && mshrQueue.canPrefetch()) { 800 // If we have a miss queue slot, we can try a prefetch 801 PacketPtr pkt = prefetcher->getPacket(); 802 if (pkt) { 803 Addr pf_addr = pkt->getBlockAddr(blkSize); 804 if (!tags->findBlock(pf_addr, pkt->isSecure()) && 805 !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 806 !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 807 // Update statistic on number of prefetches issued 808 // (hwpf_mshr_misses) 809 assert(pkt->req->masterId() < system->maxMasters()); 810 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 811 812 // allocate an MSHR and return it, note 813 // that we send the packet straight away, so do not 814 // schedule the send 815 return allocateMissBuffer(pkt, curTick(), false); 816 } else { 817 // free the request and packet 818 delete pkt; 819 } 820 } 821 } 822 823 return nullptr; 824} 825 826void 827BaseCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool, bool) 828{ 829 assert(pkt->isRequest()); 830 831 assert(blk && blk->isValid()); 832 // Occasionally this is not true... if we are a lower-level cache 833 // satisfying a string of Read and ReadEx requests from 834 // upper-level caches, a Read will mark the block as shared but we 835 // can satisfy a following ReadEx anyway since we can rely on the 836 // Read requester(s) to have buffered the ReadEx snoop and to 837 // invalidate their blocks after receiving them. 838 // assert(!pkt->needsWritable() || blk->isWritable()); 839 assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 840 841 // Check RMW operations first since both isRead() and 842 // isWrite() will be true for them 843 if (pkt->cmd == MemCmd::SwapReq) { 844 if (pkt->isAtomicOp()) { 845 // extract data from cache and save it into the data field in 846 // the packet as a return value from this atomic op 847 848 int offset = tags->extractBlkOffset(pkt->getAddr()); 849 uint8_t *blk_data = blk->data + offset; 850 std::memcpy(pkt->getPtr<uint8_t>(), blk_data, pkt->getSize()); 851 852 // execute AMO operation 853 (*(pkt->getAtomicOp()))(blk_data); 854 855 // set block status to dirty 856 blk->status |= BlkDirty; 857 } else { 858 cmpAndSwap(blk, pkt); 859 } 860 } else if (pkt->isWrite()) { 861 // we have the block in a writable state and can go ahead, 862 // note that the line may be also be considered writable in 863 // downstream caches along the path to memory, but always 864 // Exclusive, and never Modified 865 assert(blk->isWritable()); 866 // Write or WriteLine at the first cache with block in writable state 867 if (blk->checkWrite(pkt)) { 868 pkt->writeDataToBlock(blk->data, blkSize); 869 } 870 // Always mark the line as dirty (and thus transition to the 871 // Modified state) even if we are a failed StoreCond so we 872 // supply data to any snoops that have appended themselves to 873 // this cache before knowing the store will fail. 874 blk->status |= BlkDirty; 875 DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print()); 876 } else if (pkt->isRead()) { 877 if (pkt->isLLSC()) { 878 blk->trackLoadLocked(pkt); 879 } 880 881 // all read responses have a data payload 882 assert(pkt->hasRespData()); 883 pkt->setDataFromBlock(blk->data, blkSize); 884 } else if (pkt->isUpgrade()) { 885 // sanity check 886 assert(!pkt->hasSharers()); 887 888 if (blk->isDirty()) { 889 // we were in the Owned state, and a cache above us that 890 // has the line in Shared state needs to be made aware 891 // that the data it already has is in fact dirty 892 pkt->setCacheResponding(); 893 blk->status &= ~BlkDirty; 894 } 895 } else if (pkt->isClean()) { 896 blk->status &= ~BlkDirty; 897 } else { 898 assert(pkt->isInvalidate()); 899 invalidateBlock(blk); 900 DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__, 901 pkt->print()); 902 } 903} 904 905///////////////////////////////////////////////////// 906// 907// Access path: requests coming in from the CPU side 908// 909///////////////////////////////////////////////////// 910 911bool 912BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 913 PacketList &writebacks) 914{ 915 // sanity check 916 assert(pkt->isRequest()); 917 918 chatty_assert(!(isReadOnly && pkt->isWrite()), 919 "Should never see a write in a read-only cache %s\n", 920 name()); 921 922 // Here lat is the value passed as parameter to accessBlock() function 923 // that can modify its value. 924 blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat); 925 926 DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(), 927 blk ? "hit " + blk->print() : "miss"); 928 929 if (pkt->req->isCacheMaintenance()) { 930 // A cache maintenance operation is always forwarded to the 931 // memory below even if the block is found in dirty state. 932 933 // We defer any changes to the state of the block until we 934 // create and mark as in service the mshr for the downstream 935 // packet. 936 return false; 937 } 938 939 if (pkt->isEviction()) { 940 // We check for presence of block in above caches before issuing 941 // Writeback or CleanEvict to write buffer. Therefore the only 942 // possible cases can be of a CleanEvict packet coming from above 943 // encountering a Writeback generated in this cache peer cache and 944 // waiting in the write buffer. Cases of upper level peer caches 945 // generating CleanEvict and Writeback or simply CleanEvict and 946 // CleanEvict almost simultaneously will be caught by snoops sent out 947 // by crossbar. 948 WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 949 pkt->isSecure()); 950 if (wb_entry) { 951 assert(wb_entry->getNumTargets() == 1); 952 PacketPtr wbPkt = wb_entry->getTarget()->pkt; 953 assert(wbPkt->isWriteback()); 954 955 if (pkt->isCleanEviction()) { 956 // The CleanEvict and WritebackClean snoops into other 957 // peer caches of the same level while traversing the 958 // crossbar. If a copy of the block is found, the 959 // packet is deleted in the crossbar. Hence, none of 960 // the other upper level caches connected to this 961 // cache have the block, so we can clear the 962 // BLOCK_CACHED flag in the Writeback if set and 963 // discard the CleanEvict by returning true. 964 wbPkt->clearBlockCached(); 965 return true; 966 } else { 967 assert(pkt->cmd == MemCmd::WritebackDirty); 968 // Dirty writeback from above trumps our clean 969 // writeback... discard here 970 // Note: markInService will remove entry from writeback buffer. 971 markInService(wb_entry); 972 delete wbPkt; 973 } 974 } 975 } 976 977 // Writeback handling is special case. We can write the block into 978 // the cache without having a writeable copy (or any copy at all). 979 if (pkt->isWriteback()) { 980 assert(blkSize == pkt->getSize()); 981 982 // we could get a clean writeback while we are having 983 // outstanding accesses to a block, do the simple thing for 984 // now and drop the clean writeback so that we do not upset 985 // any ordering/decisions about ownership already taken 986 if (pkt->cmd == MemCmd::WritebackClean && 987 mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 988 DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 989 "dropping\n", pkt->getAddr()); 990 return true; 991 } 992 993 if (!blk) { 994 // need to do a replacement 995 blk = allocateBlock(pkt, writebacks); 996 if (!blk) { 997 // no replaceable block available: give up, fwd to next level. 998 incMissCount(pkt); 999 return false; 1000 } 1001 1002 blk->status |= (BlkValid | BlkReadable); 1003 } 1004 // only mark the block dirty if we got a writeback command, 1005 // and leave it as is for a clean writeback 1006 if (pkt->cmd == MemCmd::WritebackDirty) { 1007 // TODO: the coherent cache can assert(!blk->isDirty()); 1008 blk->status |= BlkDirty; 1009 } 1010 // if the packet does not have sharers, it is passing 1011 // writable, and we got the writeback in Modified or Exclusive 1012 // state, if not we are in the Owned or Shared state 1013 if (!pkt->hasSharers()) { 1014 blk->status |= BlkWritable; 1015 } 1016 // nothing else to do; writeback doesn't expect response 1017 assert(!pkt->needsResponse()); 1018 pkt->writeDataToBlock(blk->data, blkSize); 1019 DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 1020 incHitCount(pkt); 1021 // populate the time when the block will be ready to access. 1022 blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay + 1023 pkt->payloadDelay; 1024 return true; 1025 } else if (pkt->cmd == MemCmd::CleanEvict) { 1026 if (blk) { 1027 // Found the block in the tags, need to stop CleanEvict from 1028 // propagating further down the hierarchy. Returning true will 1029 // treat the CleanEvict like a satisfied write request and delete 1030 // it. 1031 return true; 1032 } 1033 // We didn't find the block here, propagate the CleanEvict further 1034 // down the memory hierarchy. Returning false will treat the CleanEvict 1035 // like a Writeback which could not find a replaceable block so has to 1036 // go to next level. 1037 return false; 1038 } else if (pkt->cmd == MemCmd::WriteClean) { 1039 // WriteClean handling is a special case. We can allocate a 1040 // block directly if it doesn't exist and we can update the 1041 // block immediately. The WriteClean transfers the ownership 1042 // of the block as well. 1043 assert(blkSize == pkt->getSize()); 1044 1045 if (!blk) { 1046 if (pkt->writeThrough()) { 1047 // if this is a write through packet, we don't try to 1048 // allocate if the block is not present 1049 return false; 1050 } else { 1051 // a writeback that misses needs to allocate a new block 1052 blk = allocateBlock(pkt, writebacks); 1053 if (!blk) { 1054 // no replaceable block available: give up, fwd to 1055 // next level. 1056 incMissCount(pkt); 1057 return false; 1058 } 1059 1060 blk->status |= (BlkValid | BlkReadable); 1061 } 1062 } 1063 1064 // at this point either this is a writeback or a write-through 1065 // write clean operation and the block is already in this 1066 // cache, we need to update the data and the block flags 1067 assert(blk); 1068 // TODO: the coherent cache can assert(!blk->isDirty()); 1069 if (!pkt->writeThrough()) { 1070 blk->status |= BlkDirty; 1071 } 1072 // nothing else to do; writeback doesn't expect response 1073 assert(!pkt->needsResponse()); 1074 pkt->writeDataToBlock(blk->data, blkSize); 1075 DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 1076 1077 incHitCount(pkt); 1078 // populate the time when the block will be ready to access. 1079 blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay + 1080 pkt->payloadDelay; 1081 // if this a write-through packet it will be sent to cache 1082 // below 1083 return !pkt->writeThrough(); 1084 } else if (blk && (pkt->needsWritable() ? blk->isWritable() : 1085 blk->isReadable())) { 1086 // OK to satisfy access 1087 incHitCount(pkt); 1088 satisfyRequest(pkt, blk); 1089 maintainClusivity(pkt->fromCache(), blk); 1090 1091 return true; 1092 } 1093 1094 // Can't satisfy access normally... either no block (blk == nullptr) 1095 // or have block but need writable 1096 1097 incMissCount(pkt); 1098 1099 if (!blk && pkt->isLLSC() && pkt->isWrite()) { 1100 // complete miss on store conditional... just give up now 1101 pkt->req->setExtraData(0); 1102 return true; 1103 } 1104 1105 return false; 1106} 1107 1108void 1109BaseCache::maintainClusivity(bool from_cache, CacheBlk *blk) 1110{ 1111 if (from_cache && blk && blk->isValid() && !blk->isDirty() && 1112 clusivity == Enums::mostly_excl) { 1113 // if we have responded to a cache, and our block is still 1114 // valid, but not dirty, and this cache is mostly exclusive 1115 // with respect to the cache above, drop the block 1116 invalidateBlock(blk); 1117 } 1118} 1119 1120CacheBlk* 1121BaseCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 1122 bool allocate) 1123{ 1124 assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 1125 Addr addr = pkt->getAddr(); 1126 bool is_secure = pkt->isSecure(); 1127#if TRACING_ON 1128 CacheBlk::State old_state = blk ? blk->status : 0; 1129#endif 1130 1131 // When handling a fill, we should have no writes to this line. 1132 assert(addr == pkt->getBlockAddr(blkSize)); 1133 assert(!writeBuffer.findMatch(addr, is_secure)); 1134 1135 if (!blk) { 1136 // better have read new data... 1137 assert(pkt->hasData()); 1138 1139 // only read responses and write-line requests have data; 1140 // note that we don't write the data here for write-line - that 1141 // happens in the subsequent call to satisfyRequest 1142 assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 1143 1144 // need to do a replacement if allocating, otherwise we stick 1145 // with the temporary storage 1146 blk = allocate ? allocateBlock(pkt, writebacks) : nullptr; 1147 1148 if (!blk) { 1149 // No replaceable block or a mostly exclusive 1150 // cache... just use temporary storage to complete the 1151 // current request and then get rid of it 1152 assert(!tempBlock->isValid()); 1153 blk = tempBlock; 1154 tempBlock->insert(addr, is_secure); 1155 DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 1156 is_secure ? "s" : "ns"); 1157 } 1158 1159 // we should never be overwriting a valid block 1160 assert(!blk->isValid()); 1161 } else { 1162 // existing block... probably an upgrade 1163 assert(regenerateBlkAddr(blk) == addr); 1164 assert(blk->isSecure() == is_secure); 1165 // either we're getting new data or the block should already be valid 1166 assert(pkt->hasData() || blk->isValid()); 1167 // don't clear block status... if block is already dirty we 1168 // don't want to lose that 1169 } 1170 1171 blk->status |= BlkValid | BlkReadable; 1172 1173 // sanity check for whole-line writes, which should always be 1174 // marked as writable as part of the fill, and then later marked 1175 // dirty as part of satisfyRequest 1176 if (pkt->cmd == MemCmd::WriteLineReq) { 1177 assert(!pkt->hasSharers()); 1178 } 1179 1180 // here we deal with setting the appropriate state of the line, 1181 // and we start by looking at the hasSharers flag, and ignore the 1182 // cacheResponding flag (normally signalling dirty data) if the 1183 // packet has sharers, thus the line is never allocated as Owned 1184 // (dirty but not writable), and always ends up being either 1185 // Shared, Exclusive or Modified, see Packet::setCacheResponding 1186 // for more details 1187 if (!pkt->hasSharers()) { 1188 // we could get a writable line from memory (rather than a 1189 // cache) even in a read-only cache, note that we set this bit 1190 // even for a read-only cache, possibly revisit this decision 1191 blk->status |= BlkWritable; 1192 1193 // check if we got this via cache-to-cache transfer (i.e., from a 1194 // cache that had the block in Modified or Owned state) 1195 if (pkt->cacheResponding()) { 1196 // we got the block in Modified state, and invalidated the 1197 // owners copy 1198 blk->status |= BlkDirty; 1199 1200 chatty_assert(!isReadOnly, "Should never see dirty snoop response " 1201 "in read-only cache %s\n", name()); 1202 } 1203 } 1204 1205 DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 1206 addr, is_secure ? "s" : "ns", old_state, blk->print()); 1207 1208 // if we got new data, copy it in (checking for a read response 1209 // and a response that has data is the same in the end) 1210 if (pkt->isRead()) { 1211 // sanity checks 1212 assert(pkt->hasData()); 1213 assert(pkt->getSize() == blkSize); 1214 1215 pkt->writeDataToBlock(blk->data, blkSize); 1216 } 1217 // We pay for fillLatency here. 1218 blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 1219 pkt->payloadDelay; 1220 1221 return blk; 1222} 1223 1224CacheBlk* 1225BaseCache::allocateBlock(const PacketPtr pkt, PacketList &writebacks) 1226{ 1227 // Get address 1228 const Addr addr = pkt->getAddr(); 1229 1230 // Get secure bit 1231 const bool is_secure = pkt->isSecure(); 1232 1233 // Find replacement victim 1234 std::vector<CacheBlk*> evict_blks; 1235 CacheBlk *victim = tags->findVictim(addr, is_secure, evict_blks); 1236 1237 // It is valid to return nullptr if there is no victim 1238 if (!victim) 1239 return nullptr; 1240 1241 // Print victim block's information 1242 DPRINTF(CacheRepl, "Replacement victim: %s\n", victim->print()); 1243 1244 // Check for transient state allocations. If any of the entries listed 1245 // for eviction has a transient state, the allocation fails 1246 for (const auto& blk : evict_blks) { 1247 if (blk->isValid()) { 1248 Addr repl_addr = regenerateBlkAddr(blk); 1249 MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 1250 if (repl_mshr) { 1251 // must be an outstanding upgrade or clean request 1252 // on a block we're about to replace... 1253 assert((!blk->isWritable() && repl_mshr->needsWritable()) || 1254 repl_mshr->isCleaning()); 1255 1256 // too hard to replace block with transient state 1257 // allocation failed, block not inserted 1258 return nullptr; 1259 } 1260 } 1261 } 1262 1263 // The victim will be replaced by a new entry, so increase the replacement 1264 // counter if a valid block is being replaced 1265 if (victim->isValid()) { 1266 DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx " 1267 "(%s): %s\n", regenerateBlkAddr(victim), 1268 victim->isSecure() ? "s" : "ns", 1269 addr, is_secure ? "s" : "ns", 1270 victim->isDirty() ? "writeback" : "clean"); 1271 1272 replacements++; 1273 } 1274 1275 // Evict valid blocks associated to this victim block 1276 for (const auto& blk : evict_blks) { 1277 if (blk->isValid()) { 1278 if (blk->wasPrefetched()) { 1279 unusedPrefetches++; 1280 } 1281 1282 evictBlock(blk, writebacks); 1283 } 1284 } 1285 1286 // Insert new block at victimized entry 1287 tags->insertBlock(addr, is_secure, pkt->req->masterId(), 1288 pkt->req->taskId(), victim); 1289 1290 return victim; 1291} 1292 1293void 1294BaseCache::invalidateBlock(CacheBlk *blk) 1295{ 1296 if (blk != tempBlock) 1297 tags->invalidate(blk); 1298 blk->invalidate(); 1299} 1300 1301PacketPtr 1302BaseCache::writebackBlk(CacheBlk *blk) 1303{ 1304 chatty_assert(!isReadOnly || writebackClean, 1305 "Writeback from read-only cache"); 1306 assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 1307 1308 writebacks[Request::wbMasterId]++; 1309 1310 RequestPtr req = std::make_shared<Request>( 1311 regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 1312 1313 if (blk->isSecure()) 1314 req->setFlags(Request::SECURE); 1315 1316 req->taskId(blk->task_id); 1317 1318 PacketPtr pkt = 1319 new Packet(req, blk->isDirty() ? 1320 MemCmd::WritebackDirty : MemCmd::WritebackClean); 1321 1322 DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n", 1323 pkt->print(), blk->isWritable(), blk->isDirty()); 1324 1325 if (blk->isWritable()) { 1326 // not asserting shared means we pass the block in modified 1327 // state, mark our own block non-writeable 1328 blk->status &= ~BlkWritable; 1329 } else { 1330 // we are in the Owned state, tell the receiver 1331 pkt->setHasSharers(); 1332 } 1333 1334 // make sure the block is not marked dirty 1335 blk->status &= ~BlkDirty; 1336 1337 pkt->allocate(); 1338 pkt->setDataFromBlock(blk->data, blkSize); 1339 1340 return pkt; 1341} 1342 1343PacketPtr 1344BaseCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id) 1345{ 1346 RequestPtr req = std::make_shared<Request>( 1347 regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 1348 1349 if (blk->isSecure()) { 1350 req->setFlags(Request::SECURE); 1351 } 1352 req->taskId(blk->task_id); 1353 1354 PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id); 1355 1356 if (dest) { 1357 req->setFlags(dest); 1358 pkt->setWriteThrough(); 1359 } 1360 1361 DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(), 1362 blk->isWritable(), blk->isDirty()); 1363 1364 if (blk->isWritable()) { 1365 // not asserting shared means we pass the block in modified 1366 // state, mark our own block non-writeable 1367 blk->status &= ~BlkWritable; 1368 } else { 1369 // we are in the Owned state, tell the receiver 1370 pkt->setHasSharers(); 1371 } 1372 1373 // make sure the block is not marked dirty 1374 blk->status &= ~BlkDirty; 1375 1376 pkt->allocate(); 1377 pkt->setDataFromBlock(blk->data, blkSize); 1378 1379 return pkt; 1380} 1381 1382 1383void 1384BaseCache::memWriteback() 1385{ 1386 tags->forEachBlk([this](CacheBlk &blk) { writebackVisitor(blk); }); 1387} 1388 1389void 1390BaseCache::memInvalidate() 1391{ 1392 tags->forEachBlk([this](CacheBlk &blk) { invalidateVisitor(blk); }); 1393} 1394 1395bool 1396BaseCache::isDirty() const 1397{ 1398 return tags->anyBlk([](CacheBlk &blk) { return blk.isDirty(); }); 1399} 1400 1401void 1402BaseCache::writebackVisitor(CacheBlk &blk) 1403{ 1404 if (blk.isDirty()) { 1405 assert(blk.isValid()); 1406 1407 RequestPtr request = std::make_shared<Request>( 1408 regenerateBlkAddr(&blk), blkSize, 0, Request::funcMasterId); 1409 1410 request->taskId(blk.task_id); 1411 if (blk.isSecure()) { 1412 request->setFlags(Request::SECURE); 1413 } 1414 1415 Packet packet(request, MemCmd::WriteReq); 1416 packet.dataStatic(blk.data); 1417 1418 memSidePort.sendFunctional(&packet); 1419 1420 blk.status &= ~BlkDirty; 1421 } 1422} 1423 1424void 1425BaseCache::invalidateVisitor(CacheBlk &blk) 1426{ 1427 if (blk.isDirty()) 1428 warn_once("Invalidating dirty cache lines. " \ 1429 "Expect things to break.\n"); 1430 1431 if (blk.isValid()) { 1432 assert(!blk.isDirty()); 1433 invalidateBlock(&blk); 1434 } 1435} 1436 1437Tick 1438BaseCache::nextQueueReadyTime() const 1439{ 1440 Tick nextReady = std::min(mshrQueue.nextReadyTime(), 1441 writeBuffer.nextReadyTime()); 1442 1443 // Don't signal prefetch ready time if no MSHRs available 1444 // Will signal once enoguh MSHRs are deallocated 1445 if (prefetcher && mshrQueue.canPrefetch()) { 1446 nextReady = std::min(nextReady, 1447 prefetcher->nextPrefetchReadyTime()); 1448 } 1449 1450 return nextReady; 1451} 1452 1453 1454bool 1455BaseCache::sendMSHRQueuePacket(MSHR* mshr) 1456{ 1457 assert(mshr); 1458 1459 // use request from 1st target 1460 PacketPtr tgt_pkt = mshr->getTarget()->pkt; 1461 1462 DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 1463 1464 CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 1465 1466 // either a prefetch that is not present upstream, or a normal 1467 // MSHR request, proceed to get the packet to send downstream 1468 PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable()); 1469 1470 mshr->isForward = (pkt == nullptr); 1471 1472 if (mshr->isForward) { 1473 // not a cache block request, but a response is expected 1474 // make copy of current packet to forward, keep current 1475 // copy for response handling 1476 pkt = new Packet(tgt_pkt, false, true); 1477 assert(!pkt->isWrite()); 1478 } 1479 1480 // play it safe and append (rather than set) the sender state, 1481 // as forwarded packets may already have existing state 1482 pkt->pushSenderState(mshr); 1483 1484 if (pkt->isClean() && blk && blk->isDirty()) { 1485 // A cache clean opearation is looking for a dirty block. Mark 1486 // the packet so that the destination xbar can determine that 1487 // there will be a follow-up write packet as well. 1488 pkt->setSatisfied(); 1489 } 1490 1491 if (!memSidePort.sendTimingReq(pkt)) { 1492 // we are awaiting a retry, but we 1493 // delete the packet and will be creating a new packet 1494 // when we get the opportunity 1495 delete pkt; 1496 1497 // note that we have now masked any requestBus and 1498 // schedSendEvent (we will wait for a retry before 1499 // doing anything), and this is so even if we do not 1500 // care about this packet and might override it before 1501 // it gets retried 1502 return true; 1503 } else { 1504 // As part of the call to sendTimingReq the packet is 1505 // forwarded to all neighbouring caches (and any caches 1506 // above them) as a snoop. Thus at this point we know if 1507 // any of the neighbouring caches are responding, and if 1508 // so, we know it is dirty, and we can determine if it is 1509 // being passed as Modified, making our MSHR the ordering 1510 // point 1511 bool pending_modified_resp = !pkt->hasSharers() && 1512 pkt->cacheResponding(); 1513 markInService(mshr, pending_modified_resp); 1514 1515 if (pkt->isClean() && blk && blk->isDirty()) { 1516 // A cache clean opearation is looking for a dirty 1517 // block. If a dirty block is encountered a WriteClean 1518 // will update any copies to the path to the memory 1519 // until the point of reference. 1520 DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 1521 __func__, pkt->print(), blk->print()); 1522 PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), 1523 pkt->id); 1524 PacketList writebacks; 1525 writebacks.push_back(wb_pkt); 1526 doWritebacks(writebacks, 0); 1527 } 1528 1529 return false; 1530 } 1531} 1532 1533bool 1534BaseCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 1535{ 1536 assert(wq_entry); 1537 1538 // always a single target for write queue entries 1539 PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 1540 1541 DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print()); 1542 1543 // forward as is, both for evictions and uncacheable writes 1544 if (!memSidePort.sendTimingReq(tgt_pkt)) { 1545 // note that we have now masked any requestBus and 1546 // schedSendEvent (we will wait for a retry before 1547 // doing anything), and this is so even if we do not 1548 // care about this packet and might override it before 1549 // it gets retried 1550 return true; 1551 } else { 1552 markInService(wq_entry); 1553 return false; 1554 } 1555} 1556 1557void 1558BaseCache::serialize(CheckpointOut &cp) const 1559{ 1560 bool dirty(isDirty()); 1561 1562 if (dirty) { 1563 warn("*** The cache still contains dirty data. ***\n"); 1564 warn(" Make sure to drain the system using the correct flags.\n"); 1565 warn(" This checkpoint will not restore correctly " \ 1566 "and dirty data in the cache will be lost!\n"); 1567 } 1568 1569 // Since we don't checkpoint the data in the cache, any dirty data 1570 // will be lost when restoring from a checkpoint of a system that 1571 // wasn't drained properly. Flag the checkpoint as invalid if the 1572 // cache contains dirty data. 1573 bool bad_checkpoint(dirty); 1574 SERIALIZE_SCALAR(bad_checkpoint); 1575} 1576 1577void 1578BaseCache::unserialize(CheckpointIn &cp) 1579{ 1580 bool bad_checkpoint; 1581 UNSERIALIZE_SCALAR(bad_checkpoint); 1582 if (bad_checkpoint) { 1583 fatal("Restoring from checkpoints with dirty caches is not " 1584 "supported in the classic memory system. Please remove any " 1585 "caches or drain them properly before taking checkpoints.\n"); 1586 } 1587} 1588 1589void 1590BaseCache::regStats() 1591{ 1592 MemObject::regStats(); 1593 1594 using namespace Stats; 1595 1596 // Hit statistics 1597 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1598 MemCmd cmd(access_idx); 1599 const string &cstr = cmd.toString(); 1600 1601 hits[access_idx] 1602 .init(system->maxMasters()) 1603 .name(name() + "." + cstr + "_hits") 1604 .desc("number of " + cstr + " hits") 1605 .flags(total | nozero | nonan) 1606 ; 1607 for (int i = 0; i < system->maxMasters(); i++) { 1608 hits[access_idx].subname(i, system->getMasterName(i)); 1609 } 1610 } 1611 1612// These macros make it easier to sum the right subset of commands and 1613// to change the subset of commands that are considered "demand" vs 1614// "non-demand" 1615#define SUM_DEMAND(s) \ 1616 (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \ 1617 s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq]) 1618 1619// should writebacks be included here? prior code was inconsistent... 1620#define SUM_NON_DEMAND(s) \ 1621 (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 1622 1623 demandHits 1624 .name(name() + ".demand_hits") 1625 .desc("number of demand (read+write) hits") 1626 .flags(total | nozero | nonan) 1627 ; 1628 demandHits = SUM_DEMAND(hits); 1629 for (int i = 0; i < system->maxMasters(); i++) { 1630 demandHits.subname(i, system->getMasterName(i)); 1631 } 1632 1633 overallHits 1634 .name(name() + ".overall_hits") 1635 .desc("number of overall hits") 1636 .flags(total | nozero | nonan) 1637 ; 1638 overallHits = demandHits + SUM_NON_DEMAND(hits); 1639 for (int i = 0; i < system->maxMasters(); i++) { 1640 overallHits.subname(i, system->getMasterName(i)); 1641 } 1642 1643 // Miss statistics 1644 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1645 MemCmd cmd(access_idx); 1646 const string &cstr = cmd.toString(); 1647 1648 misses[access_idx] 1649 .init(system->maxMasters()) 1650 .name(name() + "." + cstr + "_misses") 1651 .desc("number of " + cstr + " misses") 1652 .flags(total | nozero | nonan) 1653 ; 1654 for (int i = 0; i < system->maxMasters(); i++) { 1655 misses[access_idx].subname(i, system->getMasterName(i)); 1656 } 1657 } 1658 1659 demandMisses 1660 .name(name() + ".demand_misses") 1661 .desc("number of demand (read+write) misses") 1662 .flags(total | nozero | nonan) 1663 ; 1664 demandMisses = SUM_DEMAND(misses); 1665 for (int i = 0; i < system->maxMasters(); i++) { 1666 demandMisses.subname(i, system->getMasterName(i)); 1667 } 1668 1669 overallMisses 1670 .name(name() + ".overall_misses") 1671 .desc("number of overall misses") 1672 .flags(total | nozero | nonan) 1673 ; 1674 overallMisses = demandMisses + SUM_NON_DEMAND(misses); 1675 for (int i = 0; i < system->maxMasters(); i++) { 1676 overallMisses.subname(i, system->getMasterName(i)); 1677 } 1678 1679 // Miss latency statistics 1680 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1681 MemCmd cmd(access_idx); 1682 const string &cstr = cmd.toString(); 1683 1684 missLatency[access_idx] 1685 .init(system->maxMasters()) 1686 .name(name() + "." + cstr + "_miss_latency") 1687 .desc("number of " + cstr + " miss cycles") 1688 .flags(total | nozero | nonan) 1689 ; 1690 for (int i = 0; i < system->maxMasters(); i++) { 1691 missLatency[access_idx].subname(i, system->getMasterName(i)); 1692 } 1693 } 1694 1695 demandMissLatency 1696 .name(name() + ".demand_miss_latency") 1697 .desc("number of demand (read+write) miss cycles") 1698 .flags(total | nozero | nonan) 1699 ; 1700 demandMissLatency = SUM_DEMAND(missLatency); 1701 for (int i = 0; i < system->maxMasters(); i++) { 1702 demandMissLatency.subname(i, system->getMasterName(i)); 1703 } 1704 1705 overallMissLatency 1706 .name(name() + ".overall_miss_latency") 1707 .desc("number of overall miss cycles") 1708 .flags(total | nozero | nonan) 1709 ; 1710 overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 1711 for (int i = 0; i < system->maxMasters(); i++) { 1712 overallMissLatency.subname(i, system->getMasterName(i)); 1713 } 1714 1715 // access formulas 1716 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1717 MemCmd cmd(access_idx); 1718 const string &cstr = cmd.toString(); 1719 1720 accesses[access_idx] 1721 .name(name() + "." + cstr + "_accesses") 1722 .desc("number of " + cstr + " accesses(hits+misses)") 1723 .flags(total | nozero | nonan) 1724 ; 1725 accesses[access_idx] = hits[access_idx] + misses[access_idx]; 1726 1727 for (int i = 0; i < system->maxMasters(); i++) { 1728 accesses[access_idx].subname(i, system->getMasterName(i)); 1729 } 1730 } 1731 1732 demandAccesses 1733 .name(name() + ".demand_accesses") 1734 .desc("number of demand (read+write) accesses") 1735 .flags(total | nozero | nonan) 1736 ; 1737 demandAccesses = demandHits + demandMisses; 1738 for (int i = 0; i < system->maxMasters(); i++) { 1739 demandAccesses.subname(i, system->getMasterName(i)); 1740 } 1741 1742 overallAccesses 1743 .name(name() + ".overall_accesses") 1744 .desc("number of overall (read+write) accesses") 1745 .flags(total | nozero | nonan) 1746 ; 1747 overallAccesses = overallHits + overallMisses; 1748 for (int i = 0; i < system->maxMasters(); i++) { 1749 overallAccesses.subname(i, system->getMasterName(i)); 1750 } 1751 1752 // miss rate formulas 1753 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1754 MemCmd cmd(access_idx); 1755 const string &cstr = cmd.toString(); 1756 1757 missRate[access_idx] 1758 .name(name() + "." + cstr + "_miss_rate") 1759 .desc("miss rate for " + cstr + " accesses") 1760 .flags(total | nozero | nonan) 1761 ; 1762 missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 1763 1764 for (int i = 0; i < system->maxMasters(); i++) { 1765 missRate[access_idx].subname(i, system->getMasterName(i)); 1766 } 1767 } 1768 1769 demandMissRate 1770 .name(name() + ".demand_miss_rate") 1771 .desc("miss rate for demand accesses") 1772 .flags(total | nozero | nonan) 1773 ; 1774 demandMissRate = demandMisses / demandAccesses; 1775 for (int i = 0; i < system->maxMasters(); i++) { 1776 demandMissRate.subname(i, system->getMasterName(i)); 1777 } 1778 1779 overallMissRate 1780 .name(name() + ".overall_miss_rate") 1781 .desc("miss rate for overall accesses") 1782 .flags(total | nozero | nonan) 1783 ; 1784 overallMissRate = overallMisses / overallAccesses; 1785 for (int i = 0; i < system->maxMasters(); i++) { 1786 overallMissRate.subname(i, system->getMasterName(i)); 1787 } 1788 1789 // miss latency formulas 1790 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1791 MemCmd cmd(access_idx); 1792 const string &cstr = cmd.toString(); 1793 1794 avgMissLatency[access_idx] 1795 .name(name() + "." + cstr + "_avg_miss_latency") 1796 .desc("average " + cstr + " miss latency") 1797 .flags(total | nozero | nonan) 1798 ; 1799 avgMissLatency[access_idx] = 1800 missLatency[access_idx] / misses[access_idx]; 1801 1802 for (int i = 0; i < system->maxMasters(); i++) { 1803 avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 1804 } 1805 } 1806 1807 demandAvgMissLatency 1808 .name(name() + ".demand_avg_miss_latency") 1809 .desc("average overall miss latency") 1810 .flags(total | nozero | nonan) 1811 ; 1812 demandAvgMissLatency = demandMissLatency / demandMisses; 1813 for (int i = 0; i < system->maxMasters(); i++) { 1814 demandAvgMissLatency.subname(i, system->getMasterName(i)); 1815 } 1816 1817 overallAvgMissLatency 1818 .name(name() + ".overall_avg_miss_latency") 1819 .desc("average overall miss latency") 1820 .flags(total | nozero | nonan) 1821 ; 1822 overallAvgMissLatency = overallMissLatency / overallMisses; 1823 for (int i = 0; i < system->maxMasters(); i++) { 1824 overallAvgMissLatency.subname(i, system->getMasterName(i)); 1825 } 1826 1827 blocked_cycles.init(NUM_BLOCKED_CAUSES); 1828 blocked_cycles 1829 .name(name() + ".blocked_cycles") 1830 .desc("number of cycles access was blocked") 1831 .subname(Blocked_NoMSHRs, "no_mshrs") 1832 .subname(Blocked_NoTargets, "no_targets") 1833 ; 1834 1835 1836 blocked_causes.init(NUM_BLOCKED_CAUSES); 1837 blocked_causes 1838 .name(name() + ".blocked") 1839 .desc("number of cycles access was blocked") 1840 .subname(Blocked_NoMSHRs, "no_mshrs") 1841 .subname(Blocked_NoTargets, "no_targets") 1842 ; 1843 1844 avg_blocked 1845 .name(name() + ".avg_blocked_cycles") 1846 .desc("average number of cycles each access was blocked") 1847 .subname(Blocked_NoMSHRs, "no_mshrs") 1848 .subname(Blocked_NoTargets, "no_targets") 1849 ; 1850 1851 avg_blocked = blocked_cycles / blocked_causes; 1852 1853 unusedPrefetches 1854 .name(name() + ".unused_prefetches") 1855 .desc("number of HardPF blocks evicted w/o reference") 1856 .flags(nozero) 1857 ; 1858 1859 writebacks 1860 .init(system->maxMasters()) 1861 .name(name() + ".writebacks") 1862 .desc("number of writebacks") 1863 .flags(total | nozero | nonan) 1864 ; 1865 for (int i = 0; i < system->maxMasters(); i++) { 1866 writebacks.subname(i, system->getMasterName(i)); 1867 } 1868 1869 // MSHR statistics 1870 // MSHR hit statistics 1871 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1872 MemCmd cmd(access_idx); 1873 const string &cstr = cmd.toString(); 1874 1875 mshr_hits[access_idx] 1876 .init(system->maxMasters()) 1877 .name(name() + "." + cstr + "_mshr_hits") 1878 .desc("number of " + cstr + " MSHR hits") 1879 .flags(total | nozero | nonan) 1880 ; 1881 for (int i = 0; i < system->maxMasters(); i++) { 1882 mshr_hits[access_idx].subname(i, system->getMasterName(i)); 1883 } 1884 } 1885 1886 demandMshrHits 1887 .name(name() + ".demand_mshr_hits") 1888 .desc("number of demand (read+write) MSHR hits") 1889 .flags(total | nozero | nonan) 1890 ; 1891 demandMshrHits = SUM_DEMAND(mshr_hits); 1892 for (int i = 0; i < system->maxMasters(); i++) { 1893 demandMshrHits.subname(i, system->getMasterName(i)); 1894 } 1895 1896 overallMshrHits 1897 .name(name() + ".overall_mshr_hits") 1898 .desc("number of overall MSHR hits") 1899 .flags(total | nozero | nonan) 1900 ; 1901 overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 1902 for (int i = 0; i < system->maxMasters(); i++) { 1903 overallMshrHits.subname(i, system->getMasterName(i)); 1904 } 1905 1906 // MSHR miss statistics 1907 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1908 MemCmd cmd(access_idx); 1909 const string &cstr = cmd.toString(); 1910 1911 mshr_misses[access_idx] 1912 .init(system->maxMasters()) 1913 .name(name() + "." + cstr + "_mshr_misses") 1914 .desc("number of " + cstr + " MSHR misses") 1915 .flags(total | nozero | nonan) 1916 ; 1917 for (int i = 0; i < system->maxMasters(); i++) { 1918 mshr_misses[access_idx].subname(i, system->getMasterName(i)); 1919 } 1920 } 1921 1922 demandMshrMisses 1923 .name(name() + ".demand_mshr_misses") 1924 .desc("number of demand (read+write) MSHR misses") 1925 .flags(total | nozero | nonan) 1926 ; 1927 demandMshrMisses = SUM_DEMAND(mshr_misses); 1928 for (int i = 0; i < system->maxMasters(); i++) { 1929 demandMshrMisses.subname(i, system->getMasterName(i)); 1930 } 1931 1932 overallMshrMisses 1933 .name(name() + ".overall_mshr_misses") 1934 .desc("number of overall MSHR misses") 1935 .flags(total | nozero | nonan) 1936 ; 1937 overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 1938 for (int i = 0; i < system->maxMasters(); i++) { 1939 overallMshrMisses.subname(i, system->getMasterName(i)); 1940 } 1941 1942 // MSHR miss latency statistics 1943 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1944 MemCmd cmd(access_idx); 1945 const string &cstr = cmd.toString(); 1946 1947 mshr_miss_latency[access_idx] 1948 .init(system->maxMasters()) 1949 .name(name() + "." + cstr + "_mshr_miss_latency") 1950 .desc("number of " + cstr + " MSHR miss cycles") 1951 .flags(total | nozero | nonan) 1952 ; 1953 for (int i = 0; i < system->maxMasters(); i++) { 1954 mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 1955 } 1956 } 1957 1958 demandMshrMissLatency 1959 .name(name() + ".demand_mshr_miss_latency") 1960 .desc("number of demand (read+write) MSHR miss cycles") 1961 .flags(total | nozero | nonan) 1962 ; 1963 demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 1964 for (int i = 0; i < system->maxMasters(); i++) { 1965 demandMshrMissLatency.subname(i, system->getMasterName(i)); 1966 } 1967 1968 overallMshrMissLatency 1969 .name(name() + ".overall_mshr_miss_latency") 1970 .desc("number of overall MSHR miss cycles") 1971 .flags(total | nozero | nonan) 1972 ; 1973 overallMshrMissLatency = 1974 demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 1975 for (int i = 0; i < system->maxMasters(); i++) { 1976 overallMshrMissLatency.subname(i, system->getMasterName(i)); 1977 } 1978 1979 // MSHR uncacheable statistics 1980 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1981 MemCmd cmd(access_idx); 1982 const string &cstr = cmd.toString(); 1983 1984 mshr_uncacheable[access_idx] 1985 .init(system->maxMasters()) 1986 .name(name() + "." + cstr + "_mshr_uncacheable") 1987 .desc("number of " + cstr + " MSHR uncacheable") 1988 .flags(total | nozero | nonan) 1989 ; 1990 for (int i = 0; i < system->maxMasters(); i++) { 1991 mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 1992 } 1993 } 1994 1995 overallMshrUncacheable 1996 .name(name() + ".overall_mshr_uncacheable_misses") 1997 .desc("number of overall MSHR uncacheable misses") 1998 .flags(total | nozero | nonan) 1999 ; 2000 overallMshrUncacheable = 2001 SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 2002 for (int i = 0; i < system->maxMasters(); i++) { 2003 overallMshrUncacheable.subname(i, system->getMasterName(i)); 2004 } 2005 2006 // MSHR miss latency statistics 2007 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2008 MemCmd cmd(access_idx); 2009 const string &cstr = cmd.toString(); 2010 2011 mshr_uncacheable_lat[access_idx] 2012 .init(system->maxMasters()) 2013 .name(name() + "." + cstr + "_mshr_uncacheable_latency") 2014 .desc("number of " + cstr + " MSHR uncacheable cycles") 2015 .flags(total | nozero | nonan) 2016 ; 2017 for (int i = 0; i < system->maxMasters(); i++) { 2018 mshr_uncacheable_lat[access_idx].subname( 2019 i, system->getMasterName(i)); 2020 } 2021 } 2022 2023 overallMshrUncacheableLatency 2024 .name(name() + ".overall_mshr_uncacheable_latency") 2025 .desc("number of overall MSHR uncacheable cycles") 2026 .flags(total | nozero | nonan) 2027 ; 2028 overallMshrUncacheableLatency = 2029 SUM_DEMAND(mshr_uncacheable_lat) + 2030 SUM_NON_DEMAND(mshr_uncacheable_lat); 2031 for (int i = 0; i < system->maxMasters(); i++) { 2032 overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 2033 } 2034 2035#if 0 2036 // MSHR access formulas 2037 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2038 MemCmd cmd(access_idx); 2039 const string &cstr = cmd.toString(); 2040 2041 mshrAccesses[access_idx] 2042 .name(name() + "." + cstr + "_mshr_accesses") 2043 .desc("number of " + cstr + " mshr accesses(hits+misses)") 2044 .flags(total | nozero | nonan) 2045 ; 2046 mshrAccesses[access_idx] = 2047 mshr_hits[access_idx] + mshr_misses[access_idx] 2048 + mshr_uncacheable[access_idx]; 2049 } 2050 2051 demandMshrAccesses 2052 .name(name() + ".demand_mshr_accesses") 2053 .desc("number of demand (read+write) mshr accesses") 2054 .flags(total | nozero | nonan) 2055 ; 2056 demandMshrAccesses = demandMshrHits + demandMshrMisses; 2057 2058 overallMshrAccesses 2059 .name(name() + ".overall_mshr_accesses") 2060 .desc("number of overall (read+write) mshr accesses") 2061 .flags(total | nozero | nonan) 2062 ; 2063 overallMshrAccesses = overallMshrHits + overallMshrMisses 2064 + overallMshrUncacheable; 2065#endif 2066 2067 // MSHR miss rate formulas 2068 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2069 MemCmd cmd(access_idx); 2070 const string &cstr = cmd.toString(); 2071 2072 mshrMissRate[access_idx] 2073 .name(name() + "." + cstr + "_mshr_miss_rate") 2074 .desc("mshr miss rate for " + cstr + " accesses") 2075 .flags(total | nozero | nonan) 2076 ; 2077 mshrMissRate[access_idx] = 2078 mshr_misses[access_idx] / accesses[access_idx]; 2079 2080 for (int i = 0; i < system->maxMasters(); i++) { 2081 mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 2082 } 2083 } 2084 2085 demandMshrMissRate 2086 .name(name() + ".demand_mshr_miss_rate") 2087 .desc("mshr miss rate for demand accesses") 2088 .flags(total | nozero | nonan) 2089 ; 2090 demandMshrMissRate = demandMshrMisses / demandAccesses; 2091 for (int i = 0; i < system->maxMasters(); i++) { 2092 demandMshrMissRate.subname(i, system->getMasterName(i)); 2093 } 2094 2095 overallMshrMissRate 2096 .name(name() + ".overall_mshr_miss_rate") 2097 .desc("mshr miss rate for overall accesses") 2098 .flags(total | nozero | nonan) 2099 ; 2100 overallMshrMissRate = overallMshrMisses / overallAccesses; 2101 for (int i = 0; i < system->maxMasters(); i++) { 2102 overallMshrMissRate.subname(i, system->getMasterName(i)); 2103 } 2104 2105 // mshrMiss latency formulas 2106 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2107 MemCmd cmd(access_idx); 2108 const string &cstr = cmd.toString(); 2109 2110 avgMshrMissLatency[access_idx] 2111 .name(name() + "." + cstr + "_avg_mshr_miss_latency") 2112 .desc("average " + cstr + " mshr miss latency") 2113 .flags(total | nozero | nonan) 2114 ; 2115 avgMshrMissLatency[access_idx] = 2116 mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 2117 2118 for (int i = 0; i < system->maxMasters(); i++) { 2119 avgMshrMissLatency[access_idx].subname( 2120 i, system->getMasterName(i)); 2121 } 2122 } 2123 2124 demandAvgMshrMissLatency 2125 .name(name() + ".demand_avg_mshr_miss_latency") 2126 .desc("average overall mshr miss latency") 2127 .flags(total | nozero | nonan) 2128 ; 2129 demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 2130 for (int i = 0; i < system->maxMasters(); i++) { 2131 demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 2132 } 2133 2134 overallAvgMshrMissLatency 2135 .name(name() + ".overall_avg_mshr_miss_latency") 2136 .desc("average overall mshr miss latency") 2137 .flags(total | nozero | nonan) 2138 ; 2139 overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 2140 for (int i = 0; i < system->maxMasters(); i++) { 2141 overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 2142 } 2143 2144 // mshrUncacheable latency formulas 2145 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2146 MemCmd cmd(access_idx); 2147 const string &cstr = cmd.toString(); 2148 2149 avgMshrUncacheableLatency[access_idx] 2150 .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 2151 .desc("average " + cstr + " mshr uncacheable latency") 2152 .flags(total | nozero | nonan) 2153 ; 2154 avgMshrUncacheableLatency[access_idx] = 2155 mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 2156 2157 for (int i = 0; i < system->maxMasters(); i++) { 2158 avgMshrUncacheableLatency[access_idx].subname( 2159 i, system->getMasterName(i)); 2160 } 2161 } 2162 2163 overallAvgMshrUncacheableLatency 2164 .name(name() + ".overall_avg_mshr_uncacheable_latency") 2165 .desc("average overall mshr uncacheable latency") 2166 .flags(total | nozero | nonan) 2167 ; 2168 overallAvgMshrUncacheableLatency = 2169 overallMshrUncacheableLatency / overallMshrUncacheable; 2170 for (int i = 0; i < system->maxMasters(); i++) { 2171 overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 2172 } 2173 2174 replacements 2175 .name(name() + ".replacements") 2176 .desc("number of replacements") 2177 ; 2178} 2179 2180/////////////// 2181// 2182// CpuSidePort 2183// 2184/////////////// 2185bool 2186BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 2187{ 2188 // Snoops shouldn't happen when bypassing caches 2189 assert(!cache->system->bypassCaches()); 2190 2191 assert(pkt->isResponse()); 2192 2193 // Express snoop responses from master to slave, e.g., from L1 to L2 2194 cache->recvTimingSnoopResp(pkt); 2195 return true; 2196} 2197 2198 2199bool 2200BaseCache::CpuSidePort::tryTiming(PacketPtr pkt) 2201{ 2202 if (cache->system->bypassCaches() || pkt->isExpressSnoop()) { 2203 // always let express snoop packets through even if blocked 2204 return true; 2205 } else if (blocked || mustSendRetry) { 2206 // either already committed to send a retry, or blocked 2207 mustSendRetry = true; 2208 return false; 2209 } 2210 mustSendRetry = false; 2211 return true; 2212} 2213 2214bool 2215BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 2216{ 2217 assert(pkt->isRequest()); 2218 2219 if (cache->system->bypassCaches()) { 2220 // Just forward the packet if caches are disabled. 2221 // @todo This should really enqueue the packet rather 2222 bool M5_VAR_USED success = cache->memSidePort.sendTimingReq(pkt); 2223 assert(success); 2224 return true; 2225 } else if (tryTiming(pkt)) { 2226 cache->recvTimingReq(pkt); 2227 return true; 2228 } 2229 return false; 2230} 2231 2232Tick 2233BaseCache::CpuSidePort::recvAtomic(PacketPtr pkt) 2234{ 2235 if (cache->system->bypassCaches()) { 2236 // Forward the request if the system is in cache bypass mode. 2237 return cache->memSidePort.sendAtomic(pkt); 2238 } else { 2239 return cache->recvAtomic(pkt); 2240 } 2241} 2242 2243void 2244BaseCache::CpuSidePort::recvFunctional(PacketPtr pkt) 2245{ 2246 if (cache->system->bypassCaches()) { 2247 // The cache should be flushed if we are in cache bypass mode, 2248 // so we don't need to check if we need to update anything. 2249 cache->memSidePort.sendFunctional(pkt); 2250 return; 2251 } 2252 2253 // functional request 2254 cache->functionalAccess(pkt, true); 2255} 2256 2257AddrRangeList 2258BaseCache::CpuSidePort::getAddrRanges() const 2259{ 2260 return cache->getAddrRanges(); 2261} 2262 2263 2264BaseCache:: 2265CpuSidePort::CpuSidePort(const std::string &_name, BaseCache *_cache, 2266 const std::string &_label) 2267 : CacheSlavePort(_name, _cache, _label), cache(_cache) 2268{ 2269} 2270 2271/////////////// 2272// 2273// MemSidePort 2274// 2275/////////////// 2276bool 2277BaseCache::MemSidePort::recvTimingResp(PacketPtr pkt) 2278{ 2279 cache->recvTimingResp(pkt); 2280 return true; 2281} 2282 2283// Express snooping requests to memside port 2284void 2285BaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 2286{ 2287 // Snoops shouldn't happen when bypassing caches 2288 assert(!cache->system->bypassCaches()); 2289 2290 // handle snooping requests 2291 cache->recvTimingSnoopReq(pkt); 2292} 2293 2294Tick 2295BaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 2296{ 2297 // Snoops shouldn't happen when bypassing caches 2298 assert(!cache->system->bypassCaches()); 2299 2300 return cache->recvAtomicSnoop(pkt); 2301} 2302 2303void 2304BaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 2305{ 2306 // Snoops shouldn't happen when bypassing caches 2307 assert(!cache->system->bypassCaches()); 2308 2309 // functional snoop (note that in contrast to atomic we don't have 2310 // a specific functionalSnoop method, as they have the same 2311 // behaviour regardless) 2312 cache->functionalAccess(pkt, false); 2313} 2314 2315void 2316BaseCache::CacheReqPacketQueue::sendDeferredPacket() 2317{ 2318 // sanity check 2319 assert(!waitingOnRetry); 2320 2321 // there should never be any deferred request packets in the 2322 // queue, instead we resly on the cache to provide the packets 2323 // from the MSHR queue or write queue 2324 assert(deferredPacketReadyTime() == MaxTick); 2325 2326 // check for request packets (requests & writebacks) 2327 QueueEntry* entry = cache.getNextQueueEntry(); 2328 2329 if (!entry) { 2330 // can happen if e.g. we attempt a writeback and fail, but 2331 // before the retry, the writeback is eliminated because 2332 // we snoop another cache's ReadEx. 2333 } else { 2334 // let our snoop responses go first if there are responses to 2335 // the same addresses 2336 if (checkConflictingSnoop(entry->blkAddr)) { 2337 return; 2338 } 2339 waitingOnRetry = entry->sendPacket(cache); 2340 } 2341 2342 // if we succeeded and are not waiting for a retry, schedule the 2343 // next send considering when the next queue is ready, note that 2344 // snoop responses have their own packet queue and thus schedule 2345 // their own events 2346 if (!waitingOnRetry) { 2347 schedSendEvent(cache.nextQueueReadyTime()); 2348 } 2349} 2350 2351BaseCache::MemSidePort::MemSidePort(const std::string &_name, 2352 BaseCache *_cache, 2353 const std::string &_label) 2354 : CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 2355 _reqQueue(*_cache, *this, _snoopRespQueue, _label), 2356 _snoopRespQueue(*_cache, *this, _label), cache(_cache) 2357{ 2358} 2359