base.cc revision 9347
12810SN/A/*
28856Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited
38856Sandreas.hansson@arm.com * All rights reserved.
48856Sandreas.hansson@arm.com *
58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall
68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual
78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating
88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software
98856Sandreas.hansson@arm.com * licensed hereunder.  You may use the software subject to the license
108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated
118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software,
128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form.
138856Sandreas.hansson@arm.com *
142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
152810SN/A * All rights reserved.
162810SN/A *
172810SN/A * Redistribution and use in source and binary forms, with or without
182810SN/A * modification, are permitted provided that the following conditions are
192810SN/A * met: redistributions of source code must retain the above copyright
202810SN/A * notice, this list of conditions and the following disclaimer;
212810SN/A * redistributions in binary form must reproduce the above copyright
222810SN/A * notice, this list of conditions and the following disclaimer in the
232810SN/A * documentation and/or other materials provided with the distribution;
242810SN/A * neither the name of the copyright holders nor the names of its
252810SN/A * contributors may be used to endorse or promote products derived from
262810SN/A * this software without specific prior written permission.
272810SN/A *
282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392810SN/A *
402810SN/A * Authors: Erik Hallnor
412810SN/A */
422810SN/A
432810SN/A/**
442810SN/A * @file
452810SN/A * Definition of BaseCache functions.
462810SN/A */
472810SN/A
483348SN/A#include "cpu/base.hh"
493348SN/A#include "cpu/smt.hh"
508232Snate@binkert.org#include "debug/Cache.hh"
519152Satgutier@umich.edu#include "debug/Drain.hh"
525338Sstever@gmail.com#include "mem/cache/base.hh"
535338Sstever@gmail.com#include "mem/cache/mshr.hh"
548786Sgblack@eecs.umich.edu#include "sim/full_system.hh"
552810SN/A
562810SN/Ausing namespace std;
572810SN/A
588856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
598856Sandreas.hansson@arm.com                                          BaseCache *_cache,
608856Sandreas.hansson@arm.com                                          const std::string &_label)
618922Swilliam.wang@arm.com    : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label),
628914Sandreas.hansson@arm.com      blocked(false), mustSendRetry(false), sendRetryEvent(this)
638856Sandreas.hansson@arm.com{
648856Sandreas.hansson@arm.com}
654475SN/A
665034SN/ABaseCache::BaseCache(const Params *p)
675034SN/A    : MemObject(p),
685314SN/A      mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs),
695314SN/A      writeBuffer("write buffer", p->write_buffers, p->mshrs+1000,
704628SN/A                  MSHRQueue_WriteBuffer),
715034SN/A      blkSize(p->block_size),
729263Smrinmoy.ghosh@arm.com      hitLatency(p->hit_latency),
739263Smrinmoy.ghosh@arm.com      responseLatency(p->response_latency),
745034SN/A      numTarget(p->tgts_per_mshr),
756122SSteve.Reinhardt@amd.com      forwardSnoops(p->forward_snoops),
768134SAli.Saidi@ARM.com      isTopLevel(p->is_top_level),
774626SN/A      blocked(0),
784626SN/A      noTargetMSHR(NULL),
795034SN/A      missCount(p->max_miss_count),
809342SAndreas.Sandberg@arm.com      drainManager(NULL),
818883SAli.Saidi@ARM.com      addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
828833Sdam.sunwoo@arm.com      system(p->system)
834458SN/A{
849288Sandreas.hansson@arm.com    // ensure the clock is not running at an unreasonable clock speed
859288Sandreas.hansson@arm.com    if (clock == 1)
869288Sandreas.hansson@arm.com        panic("Cache %s has a cycle time of 1 tick. Specify a clock.\n",
879288Sandreas.hansson@arm.com              name());
882810SN/A}
892810SN/A
903013SN/Avoid
918856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::setBlocked()
922810SN/A{
933013SN/A    assert(!blocked);
948856Sandreas.hansson@arm.com    DPRINTF(CachePort, "Cache port %s blocking new requests\n", name());
952810SN/A    blocked = true;
962810SN/A}
972810SN/A
982810SN/Avoid
998856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::clearBlocked()
1002810SN/A{
1013013SN/A    assert(blocked);
1028856Sandreas.hansson@arm.com    DPRINTF(CachePort, "Cache port %s accepting new requests\n", name());
1033013SN/A    blocked = false;
1048856Sandreas.hansson@arm.com    if (mustSendRetry) {
1058856Sandreas.hansson@arm.com        DPRINTF(CachePort, "Cache port %s sending retry\n", name());
1062897SN/A        mustSendRetry = false;
1074666SN/A        // @TODO: need to find a better time (next bus cycle?)
1088922Swilliam.wang@arm.com        owner.schedule(sendRetryEvent, curTick() + 1);
1092897SN/A    }
1102810SN/A}
1112810SN/A
1122844SN/A
1132810SN/Avoid
1142858SN/ABaseCache::init()
1152858SN/A{
1168856Sandreas.hansson@arm.com    if (!cpuSidePort->isConnected() || !memSidePort->isConnected())
1178922Swilliam.wang@arm.com        fatal("Cache ports on %s are not connected\n", name());
1188711Sandreas.hansson@arm.com    cpuSidePort->sendRangeChange();
1192858SN/A}
1202858SN/A
1219294Sandreas.hansson@arm.comBaseMasterPort &
1229294Sandreas.hansson@arm.comBaseCache::getMasterPort(const std::string &if_name, PortID idx)
1238922Swilliam.wang@arm.com{
1248922Swilliam.wang@arm.com    if (if_name == "mem_side") {
1258922Swilliam.wang@arm.com        return *memSidePort;
1268922Swilliam.wang@arm.com    }  else {
1278922Swilliam.wang@arm.com        return MemObject::getMasterPort(if_name, idx);
1288922Swilliam.wang@arm.com    }
1298922Swilliam.wang@arm.com}
1308922Swilliam.wang@arm.com
1319294Sandreas.hansson@arm.comBaseSlavePort &
1329294Sandreas.hansson@arm.comBaseCache::getSlavePort(const std::string &if_name, PortID idx)
1338922Swilliam.wang@arm.com{
1348922Swilliam.wang@arm.com    if (if_name == "cpu_side") {
1358922Swilliam.wang@arm.com        return *cpuSidePort;
1368922Swilliam.wang@arm.com    } else {
1378922Swilliam.wang@arm.com        return MemObject::getSlavePort(if_name, idx);
1388922Swilliam.wang@arm.com    }
1398922Swilliam.wang@arm.com}
1404628SN/A
1412858SN/Avoid
1422810SN/ABaseCache::regStats()
1432810SN/A{
1442810SN/A    using namespace Stats;
1452810SN/A
1462810SN/A    // Hit statistics
1474022SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1484022SN/A        MemCmd cmd(access_idx);
1494022SN/A        const string &cstr = cmd.toString();
1502810SN/A
1512810SN/A        hits[access_idx]
1528833Sdam.sunwoo@arm.com            .init(system->maxMasters())
1532810SN/A            .name(name() + "." + cstr + "_hits")
1542810SN/A            .desc("number of " + cstr + " hits")
1552810SN/A            .flags(total | nozero | nonan)
1562810SN/A            ;
1578833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
1588833Sdam.sunwoo@arm.com            hits[access_idx].subname(i, system->getMasterName(i));
1598833Sdam.sunwoo@arm.com        }
1602810SN/A    }
1612810SN/A
1624871SN/A// These macros make it easier to sum the right subset of commands and
1634871SN/A// to change the subset of commands that are considered "demand" vs
1644871SN/A// "non-demand"
1654871SN/A#define SUM_DEMAND(s) \
1664871SN/A    (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::ReadExReq])
1674871SN/A
1684871SN/A// should writebacks be included here?  prior code was inconsistent...
1694871SN/A#define SUM_NON_DEMAND(s) \
1704871SN/A    (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq])
1714871SN/A
1722810SN/A    demandHits
1732810SN/A        .name(name() + ".demand_hits")
1742810SN/A        .desc("number of demand (read+write) hits")
1758833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
1762810SN/A        ;
1774871SN/A    demandHits = SUM_DEMAND(hits);
1788833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
1798833Sdam.sunwoo@arm.com        demandHits.subname(i, system->getMasterName(i));
1808833Sdam.sunwoo@arm.com    }
1812810SN/A
1822810SN/A    overallHits
1832810SN/A        .name(name() + ".overall_hits")
1842810SN/A        .desc("number of overall hits")
1858833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
1862810SN/A        ;
1874871SN/A    overallHits = demandHits + SUM_NON_DEMAND(hits);
1888833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
1898833Sdam.sunwoo@arm.com        overallHits.subname(i, system->getMasterName(i));
1908833Sdam.sunwoo@arm.com    }
1912810SN/A
1922810SN/A    // Miss statistics
1934022SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1944022SN/A        MemCmd cmd(access_idx);
1954022SN/A        const string &cstr = cmd.toString();
1962810SN/A
1972810SN/A        misses[access_idx]
1988833Sdam.sunwoo@arm.com            .init(system->maxMasters())
1992810SN/A            .name(name() + "." + cstr + "_misses")
2002810SN/A            .desc("number of " + cstr + " misses")
2012810SN/A            .flags(total | nozero | nonan)
2022810SN/A            ;
2038833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
2048833Sdam.sunwoo@arm.com            misses[access_idx].subname(i, system->getMasterName(i));
2058833Sdam.sunwoo@arm.com        }
2062810SN/A    }
2072810SN/A
2082810SN/A    demandMisses
2092810SN/A        .name(name() + ".demand_misses")
2102810SN/A        .desc("number of demand (read+write) misses")
2118833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
2122810SN/A        ;
2134871SN/A    demandMisses = SUM_DEMAND(misses);
2148833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
2158833Sdam.sunwoo@arm.com        demandMisses.subname(i, system->getMasterName(i));
2168833Sdam.sunwoo@arm.com    }
2172810SN/A
2182810SN/A    overallMisses
2192810SN/A        .name(name() + ".overall_misses")
2202810SN/A        .desc("number of overall misses")
2218833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
2222810SN/A        ;
2234871SN/A    overallMisses = demandMisses + SUM_NON_DEMAND(misses);
2248833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
2258833Sdam.sunwoo@arm.com        overallMisses.subname(i, system->getMasterName(i));
2268833Sdam.sunwoo@arm.com    }
2272810SN/A
2282810SN/A    // Miss latency statistics
2294022SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2304022SN/A        MemCmd cmd(access_idx);
2314022SN/A        const string &cstr = cmd.toString();
2322810SN/A
2332810SN/A        missLatency[access_idx]
2348833Sdam.sunwoo@arm.com            .init(system->maxMasters())
2352810SN/A            .name(name() + "." + cstr + "_miss_latency")
2362810SN/A            .desc("number of " + cstr + " miss cycles")
2372810SN/A            .flags(total | nozero | nonan)
2382810SN/A            ;
2398833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
2408833Sdam.sunwoo@arm.com            missLatency[access_idx].subname(i, system->getMasterName(i));
2418833Sdam.sunwoo@arm.com        }
2422810SN/A    }
2432810SN/A
2442810SN/A    demandMissLatency
2452810SN/A        .name(name() + ".demand_miss_latency")
2462810SN/A        .desc("number of demand (read+write) miss cycles")
2478833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
2482810SN/A        ;
2494871SN/A    demandMissLatency = SUM_DEMAND(missLatency);
2508833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
2518833Sdam.sunwoo@arm.com        demandMissLatency.subname(i, system->getMasterName(i));
2528833Sdam.sunwoo@arm.com    }
2532810SN/A
2542810SN/A    overallMissLatency
2552810SN/A        .name(name() + ".overall_miss_latency")
2562810SN/A        .desc("number of overall miss cycles")
2578833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
2582810SN/A        ;
2594871SN/A    overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency);
2608833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
2618833Sdam.sunwoo@arm.com        overallMissLatency.subname(i, system->getMasterName(i));
2628833Sdam.sunwoo@arm.com    }
2632810SN/A
2642810SN/A    // access formulas
2654022SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2664022SN/A        MemCmd cmd(access_idx);
2674022SN/A        const string &cstr = cmd.toString();
2682810SN/A
2692810SN/A        accesses[access_idx]
2702810SN/A            .name(name() + "." + cstr + "_accesses")
2712810SN/A            .desc("number of " + cstr + " accesses(hits+misses)")
2722810SN/A            .flags(total | nozero | nonan)
2732810SN/A            ;
2748833Sdam.sunwoo@arm.com        accesses[access_idx] = hits[access_idx] + misses[access_idx];
2752810SN/A
2768833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
2778833Sdam.sunwoo@arm.com            accesses[access_idx].subname(i, system->getMasterName(i));
2788833Sdam.sunwoo@arm.com        }
2792810SN/A    }
2802810SN/A
2812810SN/A    demandAccesses
2822810SN/A        .name(name() + ".demand_accesses")
2832810SN/A        .desc("number of demand (read+write) accesses")
2848833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
2852810SN/A        ;
2862810SN/A    demandAccesses = demandHits + demandMisses;
2878833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
2888833Sdam.sunwoo@arm.com        demandAccesses.subname(i, system->getMasterName(i));
2898833Sdam.sunwoo@arm.com    }
2902810SN/A
2912810SN/A    overallAccesses
2922810SN/A        .name(name() + ".overall_accesses")
2932810SN/A        .desc("number of overall (read+write) accesses")
2948833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
2952810SN/A        ;
2962810SN/A    overallAccesses = overallHits + overallMisses;
2978833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
2988833Sdam.sunwoo@arm.com        overallAccesses.subname(i, system->getMasterName(i));
2998833Sdam.sunwoo@arm.com    }
3002810SN/A
3012810SN/A    // miss rate formulas
3024022SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
3034022SN/A        MemCmd cmd(access_idx);
3044022SN/A        const string &cstr = cmd.toString();
3052810SN/A
3062810SN/A        missRate[access_idx]
3072810SN/A            .name(name() + "." + cstr + "_miss_rate")
3082810SN/A            .desc("miss rate for " + cstr + " accesses")
3092810SN/A            .flags(total | nozero | nonan)
3102810SN/A            ;
3118833Sdam.sunwoo@arm.com        missRate[access_idx] = misses[access_idx] / accesses[access_idx];
3122810SN/A
3138833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
3148833Sdam.sunwoo@arm.com            missRate[access_idx].subname(i, system->getMasterName(i));
3158833Sdam.sunwoo@arm.com        }
3162810SN/A    }
3172810SN/A
3182810SN/A    demandMissRate
3192810SN/A        .name(name() + ".demand_miss_rate")
3202810SN/A        .desc("miss rate for demand accesses")
3218833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
3222810SN/A        ;
3232810SN/A    demandMissRate = demandMisses / demandAccesses;
3248833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
3258833Sdam.sunwoo@arm.com        demandMissRate.subname(i, system->getMasterName(i));
3268833Sdam.sunwoo@arm.com    }
3272810SN/A
3282810SN/A    overallMissRate
3292810SN/A        .name(name() + ".overall_miss_rate")
3302810SN/A        .desc("miss rate for overall accesses")
3318833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
3322810SN/A        ;
3332810SN/A    overallMissRate = overallMisses / overallAccesses;
3348833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
3358833Sdam.sunwoo@arm.com        overallMissRate.subname(i, system->getMasterName(i));
3368833Sdam.sunwoo@arm.com    }
3372810SN/A
3382810SN/A    // miss latency formulas
3394022SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
3404022SN/A        MemCmd cmd(access_idx);
3414022SN/A        const string &cstr = cmd.toString();
3422810SN/A
3432810SN/A        avgMissLatency[access_idx]
3442810SN/A            .name(name() + "." + cstr + "_avg_miss_latency")
3452810SN/A            .desc("average " + cstr + " miss latency")
3462810SN/A            .flags(total | nozero | nonan)
3472810SN/A            ;
3482810SN/A        avgMissLatency[access_idx] =
3492810SN/A            missLatency[access_idx] / misses[access_idx];
3508833Sdam.sunwoo@arm.com
3518833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
3528833Sdam.sunwoo@arm.com            avgMissLatency[access_idx].subname(i, system->getMasterName(i));
3538833Sdam.sunwoo@arm.com        }
3542810SN/A    }
3552810SN/A
3562810SN/A    demandAvgMissLatency
3572810SN/A        .name(name() + ".demand_avg_miss_latency")
3582810SN/A        .desc("average overall miss latency")
3598833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
3602810SN/A        ;
3612810SN/A    demandAvgMissLatency = demandMissLatency / demandMisses;
3628833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
3638833Sdam.sunwoo@arm.com        demandAvgMissLatency.subname(i, system->getMasterName(i));
3648833Sdam.sunwoo@arm.com    }
3652810SN/A
3662810SN/A    overallAvgMissLatency
3672810SN/A        .name(name() + ".overall_avg_miss_latency")
3682810SN/A        .desc("average overall miss latency")
3698833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
3702810SN/A        ;
3712810SN/A    overallAvgMissLatency = overallMissLatency / overallMisses;
3728833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
3738833Sdam.sunwoo@arm.com        overallAvgMissLatency.subname(i, system->getMasterName(i));
3748833Sdam.sunwoo@arm.com    }
3752810SN/A
3762810SN/A    blocked_cycles.init(NUM_BLOCKED_CAUSES);
3772810SN/A    blocked_cycles
3782810SN/A        .name(name() + ".blocked_cycles")
3792810SN/A        .desc("number of cycles access was blocked")
3802810SN/A        .subname(Blocked_NoMSHRs, "no_mshrs")
3812810SN/A        .subname(Blocked_NoTargets, "no_targets")
3822810SN/A        ;
3832810SN/A
3842810SN/A
3852810SN/A    blocked_causes.init(NUM_BLOCKED_CAUSES);
3862810SN/A    blocked_causes
3872810SN/A        .name(name() + ".blocked")
3882810SN/A        .desc("number of cycles access was blocked")
3892810SN/A        .subname(Blocked_NoMSHRs, "no_mshrs")
3902810SN/A        .subname(Blocked_NoTargets, "no_targets")
3912810SN/A        ;
3922810SN/A
3932810SN/A    avg_blocked
3942810SN/A        .name(name() + ".avg_blocked_cycles")
3952810SN/A        .desc("average number of cycles each access was blocked")
3962810SN/A        .subname(Blocked_NoMSHRs, "no_mshrs")
3972810SN/A        .subname(Blocked_NoTargets, "no_targets")
3982810SN/A        ;
3992810SN/A
4002810SN/A    avg_blocked = blocked_cycles / blocked_causes;
4012810SN/A
4022810SN/A    fastWrites
4032810SN/A        .name(name() + ".fast_writes")
4042810SN/A        .desc("number of fast writes performed")
4052810SN/A        ;
4062810SN/A
4072810SN/A    cacheCopies
4082810SN/A        .name(name() + ".cache_copies")
4092810SN/A        .desc("number of cache copies performed")
4102810SN/A        ;
4112826SN/A
4124626SN/A    writebacks
4138833Sdam.sunwoo@arm.com        .init(system->maxMasters())
4144626SN/A        .name(name() + ".writebacks")
4154626SN/A        .desc("number of writebacks")
4168833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
4174626SN/A        ;
4188833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
4198833Sdam.sunwoo@arm.com        writebacks.subname(i, system->getMasterName(i));
4208833Sdam.sunwoo@arm.com    }
4214626SN/A
4224626SN/A    // MSHR statistics
4234626SN/A    // MSHR hit statistics
4244626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
4254626SN/A        MemCmd cmd(access_idx);
4264626SN/A        const string &cstr = cmd.toString();
4274626SN/A
4284626SN/A        mshr_hits[access_idx]
4298833Sdam.sunwoo@arm.com            .init(system->maxMasters())
4304626SN/A            .name(name() + "." + cstr + "_mshr_hits")
4314626SN/A            .desc("number of " + cstr + " MSHR hits")
4324626SN/A            .flags(total | nozero | nonan)
4334626SN/A            ;
4348833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
4358833Sdam.sunwoo@arm.com            mshr_hits[access_idx].subname(i, system->getMasterName(i));
4368833Sdam.sunwoo@arm.com        }
4374626SN/A    }
4384626SN/A
4394626SN/A    demandMshrHits
4404626SN/A        .name(name() + ".demand_mshr_hits")
4414626SN/A        .desc("number of demand (read+write) MSHR hits")
4428833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
4434626SN/A        ;
4444871SN/A    demandMshrHits = SUM_DEMAND(mshr_hits);
4458833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
4468833Sdam.sunwoo@arm.com        demandMshrHits.subname(i, system->getMasterName(i));
4478833Sdam.sunwoo@arm.com    }
4484626SN/A
4494626SN/A    overallMshrHits
4504626SN/A        .name(name() + ".overall_mshr_hits")
4514626SN/A        .desc("number of overall MSHR hits")
4528833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
4534626SN/A        ;
4544871SN/A    overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits);
4558833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
4568833Sdam.sunwoo@arm.com        overallMshrHits.subname(i, system->getMasterName(i));
4578833Sdam.sunwoo@arm.com    }
4584626SN/A
4594626SN/A    // MSHR miss statistics
4604626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
4614626SN/A        MemCmd cmd(access_idx);
4624626SN/A        const string &cstr = cmd.toString();
4634626SN/A
4644626SN/A        mshr_misses[access_idx]
4658833Sdam.sunwoo@arm.com            .init(system->maxMasters())
4664626SN/A            .name(name() + "." + cstr + "_mshr_misses")
4674626SN/A            .desc("number of " + cstr + " MSHR misses")
4684626SN/A            .flags(total | nozero | nonan)
4694626SN/A            ;
4708833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
4718833Sdam.sunwoo@arm.com            mshr_misses[access_idx].subname(i, system->getMasterName(i));
4728833Sdam.sunwoo@arm.com        }
4734626SN/A    }
4744626SN/A
4754626SN/A    demandMshrMisses
4764626SN/A        .name(name() + ".demand_mshr_misses")
4774626SN/A        .desc("number of demand (read+write) MSHR misses")
4788833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
4794626SN/A        ;
4804871SN/A    demandMshrMisses = SUM_DEMAND(mshr_misses);
4818833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
4828833Sdam.sunwoo@arm.com        demandMshrMisses.subname(i, system->getMasterName(i));
4838833Sdam.sunwoo@arm.com    }
4844626SN/A
4854626SN/A    overallMshrMisses
4864626SN/A        .name(name() + ".overall_mshr_misses")
4874626SN/A        .desc("number of overall MSHR misses")
4888833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
4894626SN/A        ;
4904871SN/A    overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses);
4918833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
4928833Sdam.sunwoo@arm.com        overallMshrMisses.subname(i, system->getMasterName(i));
4938833Sdam.sunwoo@arm.com    }
4944626SN/A
4954626SN/A    // MSHR miss latency statistics
4964626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
4974626SN/A        MemCmd cmd(access_idx);
4984626SN/A        const string &cstr = cmd.toString();
4994626SN/A
5004626SN/A        mshr_miss_latency[access_idx]
5018833Sdam.sunwoo@arm.com            .init(system->maxMasters())
5024626SN/A            .name(name() + "." + cstr + "_mshr_miss_latency")
5034626SN/A            .desc("number of " + cstr + " MSHR miss cycles")
5044626SN/A            .flags(total | nozero | nonan)
5054626SN/A            ;
5068833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
5078833Sdam.sunwoo@arm.com            mshr_miss_latency[access_idx].subname(i, system->getMasterName(i));
5088833Sdam.sunwoo@arm.com        }
5094626SN/A    }
5104626SN/A
5114626SN/A    demandMshrMissLatency
5124626SN/A        .name(name() + ".demand_mshr_miss_latency")
5134626SN/A        .desc("number of demand (read+write) MSHR miss cycles")
5148833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
5154626SN/A        ;
5164871SN/A    demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency);
5178833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
5188833Sdam.sunwoo@arm.com        demandMshrMissLatency.subname(i, system->getMasterName(i));
5198833Sdam.sunwoo@arm.com    }
5204626SN/A
5214626SN/A    overallMshrMissLatency
5224626SN/A        .name(name() + ".overall_mshr_miss_latency")
5234626SN/A        .desc("number of overall MSHR miss cycles")
5248833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
5254626SN/A        ;
5264871SN/A    overallMshrMissLatency =
5274871SN/A        demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency);
5288833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
5298833Sdam.sunwoo@arm.com        overallMshrMissLatency.subname(i, system->getMasterName(i));
5308833Sdam.sunwoo@arm.com    }
5314626SN/A
5324626SN/A    // MSHR uncacheable statistics
5334626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
5344626SN/A        MemCmd cmd(access_idx);
5354626SN/A        const string &cstr = cmd.toString();
5364626SN/A
5374626SN/A        mshr_uncacheable[access_idx]
5388833Sdam.sunwoo@arm.com            .init(system->maxMasters())
5394626SN/A            .name(name() + "." + cstr + "_mshr_uncacheable")
5404626SN/A            .desc("number of " + cstr + " MSHR uncacheable")
5414626SN/A            .flags(total | nozero | nonan)
5424626SN/A            ;
5438833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
5448833Sdam.sunwoo@arm.com            mshr_uncacheable[access_idx].subname(i, system->getMasterName(i));
5458833Sdam.sunwoo@arm.com        }
5464626SN/A    }
5474626SN/A
5484626SN/A    overallMshrUncacheable
5494626SN/A        .name(name() + ".overall_mshr_uncacheable_misses")
5504626SN/A        .desc("number of overall MSHR uncacheable misses")
5518833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
5524626SN/A        ;
5534871SN/A    overallMshrUncacheable =
5544871SN/A        SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable);
5558833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
5568833Sdam.sunwoo@arm.com        overallMshrUncacheable.subname(i, system->getMasterName(i));
5578833Sdam.sunwoo@arm.com    }
5584626SN/A
5594626SN/A    // MSHR miss latency statistics
5604626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
5614626SN/A        MemCmd cmd(access_idx);
5624626SN/A        const string &cstr = cmd.toString();
5634626SN/A
5644626SN/A        mshr_uncacheable_lat[access_idx]
5658833Sdam.sunwoo@arm.com            .init(system->maxMasters())
5664626SN/A            .name(name() + "." + cstr + "_mshr_uncacheable_latency")
5674626SN/A            .desc("number of " + cstr + " MSHR uncacheable cycles")
5684626SN/A            .flags(total | nozero | nonan)
5694626SN/A            ;
5708833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
5718833Sdam.sunwoo@arm.com            mshr_uncacheable_lat[access_idx].subname(i, system->getMasterName(i));
5728833Sdam.sunwoo@arm.com        }
5734626SN/A    }
5744626SN/A
5754626SN/A    overallMshrUncacheableLatency
5764626SN/A        .name(name() + ".overall_mshr_uncacheable_latency")
5774626SN/A        .desc("number of overall MSHR uncacheable cycles")
5788833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
5794626SN/A        ;
5804871SN/A    overallMshrUncacheableLatency =
5814871SN/A        SUM_DEMAND(mshr_uncacheable_lat) +
5824871SN/A        SUM_NON_DEMAND(mshr_uncacheable_lat);
5838833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
5848833Sdam.sunwoo@arm.com        overallMshrUncacheableLatency.subname(i, system->getMasterName(i));
5858833Sdam.sunwoo@arm.com    }
5864626SN/A
5874626SN/A#if 0
5884626SN/A    // MSHR access formulas
5894626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
5904626SN/A        MemCmd cmd(access_idx);
5914626SN/A        const string &cstr = cmd.toString();
5924626SN/A
5934626SN/A        mshrAccesses[access_idx]
5944626SN/A            .name(name() + "." + cstr + "_mshr_accesses")
5954626SN/A            .desc("number of " + cstr + " mshr accesses(hits+misses)")
5964626SN/A            .flags(total | nozero | nonan)
5974626SN/A            ;
5984626SN/A        mshrAccesses[access_idx] =
5994626SN/A            mshr_hits[access_idx] + mshr_misses[access_idx]
6004626SN/A            + mshr_uncacheable[access_idx];
6014626SN/A    }
6024626SN/A
6034626SN/A    demandMshrAccesses
6044626SN/A        .name(name() + ".demand_mshr_accesses")
6054626SN/A        .desc("number of demand (read+write) mshr accesses")
6064626SN/A        .flags(total | nozero | nonan)
6074626SN/A        ;
6084626SN/A    demandMshrAccesses = demandMshrHits + demandMshrMisses;
6094626SN/A
6104626SN/A    overallMshrAccesses
6114626SN/A        .name(name() + ".overall_mshr_accesses")
6124626SN/A        .desc("number of overall (read+write) mshr accesses")
6134626SN/A        .flags(total | nozero | nonan)
6144626SN/A        ;
6154626SN/A    overallMshrAccesses = overallMshrHits + overallMshrMisses
6164626SN/A        + overallMshrUncacheable;
6174626SN/A#endif
6184626SN/A
6194626SN/A    // MSHR miss rate formulas
6204626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
6214626SN/A        MemCmd cmd(access_idx);
6224626SN/A        const string &cstr = cmd.toString();
6234626SN/A
6244626SN/A        mshrMissRate[access_idx]
6254626SN/A            .name(name() + "." + cstr + "_mshr_miss_rate")
6264626SN/A            .desc("mshr miss rate for " + cstr + " accesses")
6274626SN/A            .flags(total | nozero | nonan)
6284626SN/A            ;
6294626SN/A        mshrMissRate[access_idx] =
6304626SN/A            mshr_misses[access_idx] / accesses[access_idx];
6318833Sdam.sunwoo@arm.com
6328833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
6338833Sdam.sunwoo@arm.com            mshrMissRate[access_idx].subname(i, system->getMasterName(i));
6348833Sdam.sunwoo@arm.com        }
6354626SN/A    }
6364626SN/A
6374626SN/A    demandMshrMissRate
6384626SN/A        .name(name() + ".demand_mshr_miss_rate")
6394626SN/A        .desc("mshr miss rate for demand accesses")
6408833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
6414626SN/A        ;
6424626SN/A    demandMshrMissRate = demandMshrMisses / demandAccesses;
6438833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
6448833Sdam.sunwoo@arm.com        demandMshrMissRate.subname(i, system->getMasterName(i));
6458833Sdam.sunwoo@arm.com    }
6464626SN/A
6474626SN/A    overallMshrMissRate
6484626SN/A        .name(name() + ".overall_mshr_miss_rate")
6494626SN/A        .desc("mshr miss rate for overall accesses")
6508833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
6514626SN/A        ;
6524626SN/A    overallMshrMissRate = overallMshrMisses / overallAccesses;
6538833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
6548833Sdam.sunwoo@arm.com        overallMshrMissRate.subname(i, system->getMasterName(i));
6558833Sdam.sunwoo@arm.com    }
6564626SN/A
6574626SN/A    // mshrMiss latency formulas
6584626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
6594626SN/A        MemCmd cmd(access_idx);
6604626SN/A        const string &cstr = cmd.toString();
6614626SN/A
6624626SN/A        avgMshrMissLatency[access_idx]
6634626SN/A            .name(name() + "." + cstr + "_avg_mshr_miss_latency")
6644626SN/A            .desc("average " + cstr + " mshr miss latency")
6654626SN/A            .flags(total | nozero | nonan)
6664626SN/A            ;
6674626SN/A        avgMshrMissLatency[access_idx] =
6684626SN/A            mshr_miss_latency[access_idx] / mshr_misses[access_idx];
6698833Sdam.sunwoo@arm.com
6708833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
6718833Sdam.sunwoo@arm.com            avgMshrMissLatency[access_idx].subname(i, system->getMasterName(i));
6728833Sdam.sunwoo@arm.com        }
6734626SN/A    }
6744626SN/A
6754626SN/A    demandAvgMshrMissLatency
6764626SN/A        .name(name() + ".demand_avg_mshr_miss_latency")
6774626SN/A        .desc("average overall mshr miss latency")
6788833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
6794626SN/A        ;
6804626SN/A    demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses;
6818833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
6828833Sdam.sunwoo@arm.com        demandAvgMshrMissLatency.subname(i, system->getMasterName(i));
6838833Sdam.sunwoo@arm.com    }
6844626SN/A
6854626SN/A    overallAvgMshrMissLatency
6864626SN/A        .name(name() + ".overall_avg_mshr_miss_latency")
6874626SN/A        .desc("average overall mshr miss latency")
6888833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
6894626SN/A        ;
6904626SN/A    overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses;
6918833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
6928833Sdam.sunwoo@arm.com        overallAvgMshrMissLatency.subname(i, system->getMasterName(i));
6938833Sdam.sunwoo@arm.com    }
6944626SN/A
6954626SN/A    // mshrUncacheable latency formulas
6964626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
6974626SN/A        MemCmd cmd(access_idx);
6984626SN/A        const string &cstr = cmd.toString();
6994626SN/A
7004626SN/A        avgMshrUncacheableLatency[access_idx]
7014626SN/A            .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency")
7024626SN/A            .desc("average " + cstr + " mshr uncacheable latency")
7034626SN/A            .flags(total | nozero | nonan)
7044626SN/A            ;
7054626SN/A        avgMshrUncacheableLatency[access_idx] =
7064626SN/A            mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx];
7078833Sdam.sunwoo@arm.com
7088833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
7098833Sdam.sunwoo@arm.com            avgMshrUncacheableLatency[access_idx].subname(i, system->getMasterName(i));
7108833Sdam.sunwoo@arm.com        }
7114626SN/A    }
7124626SN/A
7134626SN/A    overallAvgMshrUncacheableLatency
7144626SN/A        .name(name() + ".overall_avg_mshr_uncacheable_latency")
7154626SN/A        .desc("average overall mshr uncacheable latency")
7168833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
7174626SN/A        ;
7184626SN/A    overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable;
7198833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
7208833Sdam.sunwoo@arm.com        overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i));
7218833Sdam.sunwoo@arm.com    }
7224626SN/A
7234626SN/A    mshr_cap_events
7248833Sdam.sunwoo@arm.com        .init(system->maxMasters())
7254626SN/A        .name(name() + ".mshr_cap_events")
7264626SN/A        .desc("number of times MSHR cap was activated")
7278833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
7284626SN/A        ;
7298833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
7308833Sdam.sunwoo@arm.com        mshr_cap_events.subname(i, system->getMasterName(i));
7318833Sdam.sunwoo@arm.com    }
7324626SN/A
7334626SN/A    //software prefetching stats
7344626SN/A    soft_prefetch_mshr_full
7358833Sdam.sunwoo@arm.com        .init(system->maxMasters())
7364626SN/A        .name(name() + ".soft_prefetch_mshr_full")
7374626SN/A        .desc("number of mshr full events for SW prefetching instrutions")
7388833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
7394626SN/A        ;
7408833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
7418833Sdam.sunwoo@arm.com        soft_prefetch_mshr_full.subname(i, system->getMasterName(i));
7428833Sdam.sunwoo@arm.com    }
7434626SN/A
7444626SN/A    mshr_no_allocate_misses
7454626SN/A        .name(name() +".no_allocate_misses")
7464626SN/A        .desc("Number of misses that were no-allocate")
7474626SN/A        ;
7484626SN/A
7492810SN/A}
7503503SN/A
7513503SN/Aunsigned int
7529342SAndreas.Sandberg@arm.comBaseCache::drain(DrainManager *dm)
7533503SN/A{
7549347SAndreas.Sandberg@arm.com    int count = memSidePort->drain(dm) + cpuSidePort->drain(dm) +
7559347SAndreas.Sandberg@arm.com        mshrQueue.drain(dm) + writeBuffer.drain(dm);
7564626SN/A
7573503SN/A    // Set status
7584626SN/A    if (count != 0) {
7599342SAndreas.Sandberg@arm.com        drainManager = dm;
7603503SN/A
7619342SAndreas.Sandberg@arm.com        setDrainState(Drainable::Draining);
7629152Satgutier@umich.edu        DPRINTF(Drain, "Cache not drained\n");
7634626SN/A        return count;
7643503SN/A    }
7653503SN/A
7669342SAndreas.Sandberg@arm.com    setDrainState(Drainable::Drained);
7673503SN/A    return 0;
7683503SN/A}
769