base.cc revision 9152
12810SN/A/* 28856Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 412810SN/A */ 422810SN/A 432810SN/A/** 442810SN/A * @file 452810SN/A * Definition of BaseCache functions. 462810SN/A */ 472810SN/A 483348SN/A#include "cpu/base.hh" 493348SN/A#include "cpu/smt.hh" 508232Snate@binkert.org#include "debug/Cache.hh" 519152Satgutier@umich.edu#include "debug/Drain.hh" 525338Sstever@gmail.com#include "mem/cache/base.hh" 535338Sstever@gmail.com#include "mem/cache/mshr.hh" 548786Sgblack@eecs.umich.edu#include "sim/full_system.hh" 552810SN/A 562810SN/Ausing namespace std; 572810SN/A 588856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 598856Sandreas.hansson@arm.com BaseCache *_cache, 608856Sandreas.hansson@arm.com const std::string &_label) 618922Swilliam.wang@arm.com : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 628914Sandreas.hansson@arm.com blocked(false), mustSendRetry(false), sendRetryEvent(this) 638856Sandreas.hansson@arm.com{ 648856Sandreas.hansson@arm.com} 654475SN/A 665034SN/ABaseCache::BaseCache(const Params *p) 675034SN/A : MemObject(p), 685314SN/A mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs), 695314SN/A writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 704628SN/A MSHRQueue_WriteBuffer), 715034SN/A blkSize(p->block_size), 725034SN/A hitLatency(p->latency), 735034SN/A numTarget(p->tgts_per_mshr), 746122SSteve.Reinhardt@amd.com forwardSnoops(p->forward_snoops), 758134SAli.Saidi@ARM.com isTopLevel(p->is_top_level), 764626SN/A blocked(0), 774626SN/A noTargetMSHR(NULL), 785034SN/A missCount(p->max_miss_count), 796122SSteve.Reinhardt@amd.com drainEvent(NULL), 808883SAli.Saidi@ARM.com addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 818833Sdam.sunwoo@arm.com system(p->system) 824458SN/A{ 832810SN/A} 842810SN/A 853013SN/Avoid 868856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::setBlocked() 872810SN/A{ 883013SN/A assert(!blocked); 898856Sandreas.hansson@arm.com DPRINTF(CachePort, "Cache port %s blocking new requests\n", name()); 902810SN/A blocked = true; 912810SN/A} 922810SN/A 932810SN/Avoid 948856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::clearBlocked() 952810SN/A{ 963013SN/A assert(blocked); 978856Sandreas.hansson@arm.com DPRINTF(CachePort, "Cache port %s accepting new requests\n", name()); 983013SN/A blocked = false; 998856Sandreas.hansson@arm.com if (mustSendRetry) { 1008856Sandreas.hansson@arm.com DPRINTF(CachePort, "Cache port %s sending retry\n", name()); 1012897SN/A mustSendRetry = false; 1024666SN/A // @TODO: need to find a better time (next bus cycle?) 1038922Swilliam.wang@arm.com owner.schedule(sendRetryEvent, curTick() + 1); 1042897SN/A } 1052810SN/A} 1062810SN/A 1072844SN/A 1082810SN/Avoid 1092858SN/ABaseCache::init() 1102858SN/A{ 1118856Sandreas.hansson@arm.com if (!cpuSidePort->isConnected() || !memSidePort->isConnected()) 1128922Swilliam.wang@arm.com fatal("Cache ports on %s are not connected\n", name()); 1138711Sandreas.hansson@arm.com cpuSidePort->sendRangeChange(); 1142858SN/A} 1152858SN/A 1168922Swilliam.wang@arm.comMasterPort & 1178922Swilliam.wang@arm.comBaseCache::getMasterPort(const std::string &if_name, int idx) 1188922Swilliam.wang@arm.com{ 1198922Swilliam.wang@arm.com if (if_name == "mem_side") { 1208922Swilliam.wang@arm.com return *memSidePort; 1218922Swilliam.wang@arm.com } else { 1228922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1238922Swilliam.wang@arm.com } 1248922Swilliam.wang@arm.com} 1258922Swilliam.wang@arm.com 1268922Swilliam.wang@arm.comSlavePort & 1278922Swilliam.wang@arm.comBaseCache::getSlavePort(const std::string &if_name, int idx) 1288922Swilliam.wang@arm.com{ 1298922Swilliam.wang@arm.com if (if_name == "cpu_side") { 1308922Swilliam.wang@arm.com return *cpuSidePort; 1318922Swilliam.wang@arm.com } else { 1328922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 1338922Swilliam.wang@arm.com } 1348922Swilliam.wang@arm.com} 1354628SN/A 1362858SN/Avoid 1372810SN/ABaseCache::regStats() 1382810SN/A{ 1392810SN/A using namespace Stats; 1402810SN/A 1412810SN/A // Hit statistics 1424022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1434022SN/A MemCmd cmd(access_idx); 1444022SN/A const string &cstr = cmd.toString(); 1452810SN/A 1462810SN/A hits[access_idx] 1478833Sdam.sunwoo@arm.com .init(system->maxMasters()) 1482810SN/A .name(name() + "." + cstr + "_hits") 1492810SN/A .desc("number of " + cstr + " hits") 1502810SN/A .flags(total | nozero | nonan) 1512810SN/A ; 1528833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1538833Sdam.sunwoo@arm.com hits[access_idx].subname(i, system->getMasterName(i)); 1548833Sdam.sunwoo@arm.com } 1552810SN/A } 1562810SN/A 1574871SN/A// These macros make it easier to sum the right subset of commands and 1584871SN/A// to change the subset of commands that are considered "demand" vs 1594871SN/A// "non-demand" 1604871SN/A#define SUM_DEMAND(s) \ 1614871SN/A (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::ReadExReq]) 1624871SN/A 1634871SN/A// should writebacks be included here? prior code was inconsistent... 1644871SN/A#define SUM_NON_DEMAND(s) \ 1654871SN/A (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 1664871SN/A 1672810SN/A demandHits 1682810SN/A .name(name() + ".demand_hits") 1692810SN/A .desc("number of demand (read+write) hits") 1708833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1712810SN/A ; 1724871SN/A demandHits = SUM_DEMAND(hits); 1738833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1748833Sdam.sunwoo@arm.com demandHits.subname(i, system->getMasterName(i)); 1758833Sdam.sunwoo@arm.com } 1762810SN/A 1772810SN/A overallHits 1782810SN/A .name(name() + ".overall_hits") 1792810SN/A .desc("number of overall hits") 1808833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1812810SN/A ; 1824871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 1838833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1848833Sdam.sunwoo@arm.com overallHits.subname(i, system->getMasterName(i)); 1858833Sdam.sunwoo@arm.com } 1862810SN/A 1872810SN/A // Miss statistics 1884022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1894022SN/A MemCmd cmd(access_idx); 1904022SN/A const string &cstr = cmd.toString(); 1912810SN/A 1922810SN/A misses[access_idx] 1938833Sdam.sunwoo@arm.com .init(system->maxMasters()) 1942810SN/A .name(name() + "." + cstr + "_misses") 1952810SN/A .desc("number of " + cstr + " misses") 1962810SN/A .flags(total | nozero | nonan) 1972810SN/A ; 1988833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1998833Sdam.sunwoo@arm.com misses[access_idx].subname(i, system->getMasterName(i)); 2008833Sdam.sunwoo@arm.com } 2012810SN/A } 2022810SN/A 2032810SN/A demandMisses 2042810SN/A .name(name() + ".demand_misses") 2052810SN/A .desc("number of demand (read+write) misses") 2068833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2072810SN/A ; 2084871SN/A demandMisses = SUM_DEMAND(misses); 2098833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2108833Sdam.sunwoo@arm.com demandMisses.subname(i, system->getMasterName(i)); 2118833Sdam.sunwoo@arm.com } 2122810SN/A 2132810SN/A overallMisses 2142810SN/A .name(name() + ".overall_misses") 2152810SN/A .desc("number of overall misses") 2168833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2172810SN/A ; 2184871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 2198833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2208833Sdam.sunwoo@arm.com overallMisses.subname(i, system->getMasterName(i)); 2218833Sdam.sunwoo@arm.com } 2222810SN/A 2232810SN/A // Miss latency statistics 2244022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2254022SN/A MemCmd cmd(access_idx); 2264022SN/A const string &cstr = cmd.toString(); 2272810SN/A 2282810SN/A missLatency[access_idx] 2298833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2302810SN/A .name(name() + "." + cstr + "_miss_latency") 2312810SN/A .desc("number of " + cstr + " miss cycles") 2322810SN/A .flags(total | nozero | nonan) 2332810SN/A ; 2348833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2358833Sdam.sunwoo@arm.com missLatency[access_idx].subname(i, system->getMasterName(i)); 2368833Sdam.sunwoo@arm.com } 2372810SN/A } 2382810SN/A 2392810SN/A demandMissLatency 2402810SN/A .name(name() + ".demand_miss_latency") 2412810SN/A .desc("number of demand (read+write) miss cycles") 2428833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2432810SN/A ; 2444871SN/A demandMissLatency = SUM_DEMAND(missLatency); 2458833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2468833Sdam.sunwoo@arm.com demandMissLatency.subname(i, system->getMasterName(i)); 2478833Sdam.sunwoo@arm.com } 2482810SN/A 2492810SN/A overallMissLatency 2502810SN/A .name(name() + ".overall_miss_latency") 2512810SN/A .desc("number of overall miss cycles") 2528833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2532810SN/A ; 2544871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 2558833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2568833Sdam.sunwoo@arm.com overallMissLatency.subname(i, system->getMasterName(i)); 2578833Sdam.sunwoo@arm.com } 2582810SN/A 2592810SN/A // access formulas 2604022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2614022SN/A MemCmd cmd(access_idx); 2624022SN/A const string &cstr = cmd.toString(); 2632810SN/A 2642810SN/A accesses[access_idx] 2652810SN/A .name(name() + "." + cstr + "_accesses") 2662810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 2672810SN/A .flags(total | nozero | nonan) 2682810SN/A ; 2698833Sdam.sunwoo@arm.com accesses[access_idx] = hits[access_idx] + misses[access_idx]; 2702810SN/A 2718833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2728833Sdam.sunwoo@arm.com accesses[access_idx].subname(i, system->getMasterName(i)); 2738833Sdam.sunwoo@arm.com } 2742810SN/A } 2752810SN/A 2762810SN/A demandAccesses 2772810SN/A .name(name() + ".demand_accesses") 2782810SN/A .desc("number of demand (read+write) accesses") 2798833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2802810SN/A ; 2812810SN/A demandAccesses = demandHits + demandMisses; 2828833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2838833Sdam.sunwoo@arm.com demandAccesses.subname(i, system->getMasterName(i)); 2848833Sdam.sunwoo@arm.com } 2852810SN/A 2862810SN/A overallAccesses 2872810SN/A .name(name() + ".overall_accesses") 2882810SN/A .desc("number of overall (read+write) accesses") 2898833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2902810SN/A ; 2912810SN/A overallAccesses = overallHits + overallMisses; 2928833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2938833Sdam.sunwoo@arm.com overallAccesses.subname(i, system->getMasterName(i)); 2948833Sdam.sunwoo@arm.com } 2952810SN/A 2962810SN/A // miss rate formulas 2974022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2984022SN/A MemCmd cmd(access_idx); 2994022SN/A const string &cstr = cmd.toString(); 3002810SN/A 3012810SN/A missRate[access_idx] 3022810SN/A .name(name() + "." + cstr + "_miss_rate") 3032810SN/A .desc("miss rate for " + cstr + " accesses") 3042810SN/A .flags(total | nozero | nonan) 3052810SN/A ; 3068833Sdam.sunwoo@arm.com missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 3072810SN/A 3088833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3098833Sdam.sunwoo@arm.com missRate[access_idx].subname(i, system->getMasterName(i)); 3108833Sdam.sunwoo@arm.com } 3112810SN/A } 3122810SN/A 3132810SN/A demandMissRate 3142810SN/A .name(name() + ".demand_miss_rate") 3152810SN/A .desc("miss rate for demand accesses") 3168833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3172810SN/A ; 3182810SN/A demandMissRate = demandMisses / demandAccesses; 3198833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3208833Sdam.sunwoo@arm.com demandMissRate.subname(i, system->getMasterName(i)); 3218833Sdam.sunwoo@arm.com } 3222810SN/A 3232810SN/A overallMissRate 3242810SN/A .name(name() + ".overall_miss_rate") 3252810SN/A .desc("miss rate for overall accesses") 3268833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3272810SN/A ; 3282810SN/A overallMissRate = overallMisses / overallAccesses; 3298833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3308833Sdam.sunwoo@arm.com overallMissRate.subname(i, system->getMasterName(i)); 3318833Sdam.sunwoo@arm.com } 3322810SN/A 3332810SN/A // miss latency formulas 3344022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3354022SN/A MemCmd cmd(access_idx); 3364022SN/A const string &cstr = cmd.toString(); 3372810SN/A 3382810SN/A avgMissLatency[access_idx] 3392810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 3402810SN/A .desc("average " + cstr + " miss latency") 3412810SN/A .flags(total | nozero | nonan) 3422810SN/A ; 3432810SN/A avgMissLatency[access_idx] = 3442810SN/A missLatency[access_idx] / misses[access_idx]; 3458833Sdam.sunwoo@arm.com 3468833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3478833Sdam.sunwoo@arm.com avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 3488833Sdam.sunwoo@arm.com } 3492810SN/A } 3502810SN/A 3512810SN/A demandAvgMissLatency 3522810SN/A .name(name() + ".demand_avg_miss_latency") 3532810SN/A .desc("average overall miss latency") 3548833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3552810SN/A ; 3562810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 3578833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3588833Sdam.sunwoo@arm.com demandAvgMissLatency.subname(i, system->getMasterName(i)); 3598833Sdam.sunwoo@arm.com } 3602810SN/A 3612810SN/A overallAvgMissLatency 3622810SN/A .name(name() + ".overall_avg_miss_latency") 3632810SN/A .desc("average overall miss latency") 3648833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3652810SN/A ; 3662810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 3678833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3688833Sdam.sunwoo@arm.com overallAvgMissLatency.subname(i, system->getMasterName(i)); 3698833Sdam.sunwoo@arm.com } 3702810SN/A 3712810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 3722810SN/A blocked_cycles 3732810SN/A .name(name() + ".blocked_cycles") 3742810SN/A .desc("number of cycles access was blocked") 3752810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3762810SN/A .subname(Blocked_NoTargets, "no_targets") 3772810SN/A ; 3782810SN/A 3792810SN/A 3802810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 3812810SN/A blocked_causes 3822810SN/A .name(name() + ".blocked") 3832810SN/A .desc("number of cycles access was blocked") 3842810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3852810SN/A .subname(Blocked_NoTargets, "no_targets") 3862810SN/A ; 3872810SN/A 3882810SN/A avg_blocked 3892810SN/A .name(name() + ".avg_blocked_cycles") 3902810SN/A .desc("average number of cycles each access was blocked") 3912810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3922810SN/A .subname(Blocked_NoTargets, "no_targets") 3932810SN/A ; 3942810SN/A 3952810SN/A avg_blocked = blocked_cycles / blocked_causes; 3962810SN/A 3972810SN/A fastWrites 3982810SN/A .name(name() + ".fast_writes") 3992810SN/A .desc("number of fast writes performed") 4002810SN/A ; 4012810SN/A 4022810SN/A cacheCopies 4032810SN/A .name(name() + ".cache_copies") 4042810SN/A .desc("number of cache copies performed") 4052810SN/A ; 4062826SN/A 4074626SN/A writebacks 4088833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4094626SN/A .name(name() + ".writebacks") 4104626SN/A .desc("number of writebacks") 4118833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4124626SN/A ; 4138833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4148833Sdam.sunwoo@arm.com writebacks.subname(i, system->getMasterName(i)); 4158833Sdam.sunwoo@arm.com } 4164626SN/A 4174626SN/A // MSHR statistics 4184626SN/A // MSHR hit statistics 4194626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4204626SN/A MemCmd cmd(access_idx); 4214626SN/A const string &cstr = cmd.toString(); 4224626SN/A 4234626SN/A mshr_hits[access_idx] 4248833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4254626SN/A .name(name() + "." + cstr + "_mshr_hits") 4264626SN/A .desc("number of " + cstr + " MSHR hits") 4274626SN/A .flags(total | nozero | nonan) 4284626SN/A ; 4298833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4308833Sdam.sunwoo@arm.com mshr_hits[access_idx].subname(i, system->getMasterName(i)); 4318833Sdam.sunwoo@arm.com } 4324626SN/A } 4334626SN/A 4344626SN/A demandMshrHits 4354626SN/A .name(name() + ".demand_mshr_hits") 4364626SN/A .desc("number of demand (read+write) MSHR hits") 4378833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4384626SN/A ; 4394871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 4408833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4418833Sdam.sunwoo@arm.com demandMshrHits.subname(i, system->getMasterName(i)); 4428833Sdam.sunwoo@arm.com } 4434626SN/A 4444626SN/A overallMshrHits 4454626SN/A .name(name() + ".overall_mshr_hits") 4464626SN/A .desc("number of overall MSHR hits") 4478833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4484626SN/A ; 4494871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 4508833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4518833Sdam.sunwoo@arm.com overallMshrHits.subname(i, system->getMasterName(i)); 4528833Sdam.sunwoo@arm.com } 4534626SN/A 4544626SN/A // MSHR miss statistics 4554626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4564626SN/A MemCmd cmd(access_idx); 4574626SN/A const string &cstr = cmd.toString(); 4584626SN/A 4594626SN/A mshr_misses[access_idx] 4608833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4614626SN/A .name(name() + "." + cstr + "_mshr_misses") 4624626SN/A .desc("number of " + cstr + " MSHR misses") 4634626SN/A .flags(total | nozero | nonan) 4644626SN/A ; 4658833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4668833Sdam.sunwoo@arm.com mshr_misses[access_idx].subname(i, system->getMasterName(i)); 4678833Sdam.sunwoo@arm.com } 4684626SN/A } 4694626SN/A 4704626SN/A demandMshrMisses 4714626SN/A .name(name() + ".demand_mshr_misses") 4724626SN/A .desc("number of demand (read+write) MSHR misses") 4738833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4744626SN/A ; 4754871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 4768833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4778833Sdam.sunwoo@arm.com demandMshrMisses.subname(i, system->getMasterName(i)); 4788833Sdam.sunwoo@arm.com } 4794626SN/A 4804626SN/A overallMshrMisses 4814626SN/A .name(name() + ".overall_mshr_misses") 4824626SN/A .desc("number of overall MSHR misses") 4838833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4844626SN/A ; 4854871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 4868833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4878833Sdam.sunwoo@arm.com overallMshrMisses.subname(i, system->getMasterName(i)); 4888833Sdam.sunwoo@arm.com } 4894626SN/A 4904626SN/A // MSHR miss latency statistics 4914626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4924626SN/A MemCmd cmd(access_idx); 4934626SN/A const string &cstr = cmd.toString(); 4944626SN/A 4954626SN/A mshr_miss_latency[access_idx] 4968833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4974626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 4984626SN/A .desc("number of " + cstr + " MSHR miss cycles") 4994626SN/A .flags(total | nozero | nonan) 5004626SN/A ; 5018833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5028833Sdam.sunwoo@arm.com mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 5038833Sdam.sunwoo@arm.com } 5044626SN/A } 5054626SN/A 5064626SN/A demandMshrMissLatency 5074626SN/A .name(name() + ".demand_mshr_miss_latency") 5084626SN/A .desc("number of demand (read+write) MSHR miss cycles") 5098833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5104626SN/A ; 5114871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 5128833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5138833Sdam.sunwoo@arm.com demandMshrMissLatency.subname(i, system->getMasterName(i)); 5148833Sdam.sunwoo@arm.com } 5154626SN/A 5164626SN/A overallMshrMissLatency 5174626SN/A .name(name() + ".overall_mshr_miss_latency") 5184626SN/A .desc("number of overall MSHR miss cycles") 5198833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5204626SN/A ; 5214871SN/A overallMshrMissLatency = 5224871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 5238833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5248833Sdam.sunwoo@arm.com overallMshrMissLatency.subname(i, system->getMasterName(i)); 5258833Sdam.sunwoo@arm.com } 5264626SN/A 5274626SN/A // MSHR uncacheable statistics 5284626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5294626SN/A MemCmd cmd(access_idx); 5304626SN/A const string &cstr = cmd.toString(); 5314626SN/A 5324626SN/A mshr_uncacheable[access_idx] 5338833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5344626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 5354626SN/A .desc("number of " + cstr + " MSHR uncacheable") 5364626SN/A .flags(total | nozero | nonan) 5374626SN/A ; 5388833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5398833Sdam.sunwoo@arm.com mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 5408833Sdam.sunwoo@arm.com } 5414626SN/A } 5424626SN/A 5434626SN/A overallMshrUncacheable 5444626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 5454626SN/A .desc("number of overall MSHR uncacheable misses") 5468833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5474626SN/A ; 5484871SN/A overallMshrUncacheable = 5494871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 5508833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5518833Sdam.sunwoo@arm.com overallMshrUncacheable.subname(i, system->getMasterName(i)); 5528833Sdam.sunwoo@arm.com } 5534626SN/A 5544626SN/A // MSHR miss latency statistics 5554626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5564626SN/A MemCmd cmd(access_idx); 5574626SN/A const string &cstr = cmd.toString(); 5584626SN/A 5594626SN/A mshr_uncacheable_lat[access_idx] 5608833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5614626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 5624626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 5634626SN/A .flags(total | nozero | nonan) 5644626SN/A ; 5658833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5668833Sdam.sunwoo@arm.com mshr_uncacheable_lat[access_idx].subname(i, system->getMasterName(i)); 5678833Sdam.sunwoo@arm.com } 5684626SN/A } 5694626SN/A 5704626SN/A overallMshrUncacheableLatency 5714626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 5724626SN/A .desc("number of overall MSHR uncacheable cycles") 5738833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5744626SN/A ; 5754871SN/A overallMshrUncacheableLatency = 5764871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 5774871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 5788833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5798833Sdam.sunwoo@arm.com overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 5808833Sdam.sunwoo@arm.com } 5814626SN/A 5824626SN/A#if 0 5834626SN/A // MSHR access formulas 5844626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5854626SN/A MemCmd cmd(access_idx); 5864626SN/A const string &cstr = cmd.toString(); 5874626SN/A 5884626SN/A mshrAccesses[access_idx] 5894626SN/A .name(name() + "." + cstr + "_mshr_accesses") 5904626SN/A .desc("number of " + cstr + " mshr accesses(hits+misses)") 5914626SN/A .flags(total | nozero | nonan) 5924626SN/A ; 5934626SN/A mshrAccesses[access_idx] = 5944626SN/A mshr_hits[access_idx] + mshr_misses[access_idx] 5954626SN/A + mshr_uncacheable[access_idx]; 5964626SN/A } 5974626SN/A 5984626SN/A demandMshrAccesses 5994626SN/A .name(name() + ".demand_mshr_accesses") 6004626SN/A .desc("number of demand (read+write) mshr accesses") 6014626SN/A .flags(total | nozero | nonan) 6024626SN/A ; 6034626SN/A demandMshrAccesses = demandMshrHits + demandMshrMisses; 6044626SN/A 6054626SN/A overallMshrAccesses 6064626SN/A .name(name() + ".overall_mshr_accesses") 6074626SN/A .desc("number of overall (read+write) mshr accesses") 6084626SN/A .flags(total | nozero | nonan) 6094626SN/A ; 6104626SN/A overallMshrAccesses = overallMshrHits + overallMshrMisses 6114626SN/A + overallMshrUncacheable; 6124626SN/A#endif 6134626SN/A 6144626SN/A // MSHR miss rate formulas 6154626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6164626SN/A MemCmd cmd(access_idx); 6174626SN/A const string &cstr = cmd.toString(); 6184626SN/A 6194626SN/A mshrMissRate[access_idx] 6204626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 6214626SN/A .desc("mshr miss rate for " + cstr + " accesses") 6224626SN/A .flags(total | nozero | nonan) 6234626SN/A ; 6244626SN/A mshrMissRate[access_idx] = 6254626SN/A mshr_misses[access_idx] / accesses[access_idx]; 6268833Sdam.sunwoo@arm.com 6278833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6288833Sdam.sunwoo@arm.com mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 6298833Sdam.sunwoo@arm.com } 6304626SN/A } 6314626SN/A 6324626SN/A demandMshrMissRate 6334626SN/A .name(name() + ".demand_mshr_miss_rate") 6344626SN/A .desc("mshr miss rate for demand accesses") 6358833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6364626SN/A ; 6374626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 6388833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6398833Sdam.sunwoo@arm.com demandMshrMissRate.subname(i, system->getMasterName(i)); 6408833Sdam.sunwoo@arm.com } 6414626SN/A 6424626SN/A overallMshrMissRate 6434626SN/A .name(name() + ".overall_mshr_miss_rate") 6444626SN/A .desc("mshr miss rate for overall accesses") 6458833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6464626SN/A ; 6474626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 6488833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6498833Sdam.sunwoo@arm.com overallMshrMissRate.subname(i, system->getMasterName(i)); 6508833Sdam.sunwoo@arm.com } 6514626SN/A 6524626SN/A // mshrMiss latency formulas 6534626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6544626SN/A MemCmd cmd(access_idx); 6554626SN/A const string &cstr = cmd.toString(); 6564626SN/A 6574626SN/A avgMshrMissLatency[access_idx] 6584626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 6594626SN/A .desc("average " + cstr + " mshr miss latency") 6604626SN/A .flags(total | nozero | nonan) 6614626SN/A ; 6624626SN/A avgMshrMissLatency[access_idx] = 6634626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 6648833Sdam.sunwoo@arm.com 6658833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6668833Sdam.sunwoo@arm.com avgMshrMissLatency[access_idx].subname(i, system->getMasterName(i)); 6678833Sdam.sunwoo@arm.com } 6684626SN/A } 6694626SN/A 6704626SN/A demandAvgMshrMissLatency 6714626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 6724626SN/A .desc("average overall mshr miss latency") 6738833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6744626SN/A ; 6754626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 6768833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6778833Sdam.sunwoo@arm.com demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 6788833Sdam.sunwoo@arm.com } 6794626SN/A 6804626SN/A overallAvgMshrMissLatency 6814626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 6824626SN/A .desc("average overall mshr miss latency") 6838833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6844626SN/A ; 6854626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 6868833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6878833Sdam.sunwoo@arm.com overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 6888833Sdam.sunwoo@arm.com } 6894626SN/A 6904626SN/A // mshrUncacheable latency formulas 6914626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6924626SN/A MemCmd cmd(access_idx); 6934626SN/A const string &cstr = cmd.toString(); 6944626SN/A 6954626SN/A avgMshrUncacheableLatency[access_idx] 6964626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 6974626SN/A .desc("average " + cstr + " mshr uncacheable latency") 6984626SN/A .flags(total | nozero | nonan) 6994626SN/A ; 7004626SN/A avgMshrUncacheableLatency[access_idx] = 7014626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 7028833Sdam.sunwoo@arm.com 7038833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7048833Sdam.sunwoo@arm.com avgMshrUncacheableLatency[access_idx].subname(i, system->getMasterName(i)); 7058833Sdam.sunwoo@arm.com } 7064626SN/A } 7074626SN/A 7084626SN/A overallAvgMshrUncacheableLatency 7094626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 7104626SN/A .desc("average overall mshr uncacheable latency") 7118833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7124626SN/A ; 7134626SN/A overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable; 7148833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7158833Sdam.sunwoo@arm.com overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 7168833Sdam.sunwoo@arm.com } 7174626SN/A 7184626SN/A mshr_cap_events 7198833Sdam.sunwoo@arm.com .init(system->maxMasters()) 7204626SN/A .name(name() + ".mshr_cap_events") 7214626SN/A .desc("number of times MSHR cap was activated") 7228833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7234626SN/A ; 7248833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7258833Sdam.sunwoo@arm.com mshr_cap_events.subname(i, system->getMasterName(i)); 7268833Sdam.sunwoo@arm.com } 7274626SN/A 7284626SN/A //software prefetching stats 7294626SN/A soft_prefetch_mshr_full 7308833Sdam.sunwoo@arm.com .init(system->maxMasters()) 7314626SN/A .name(name() + ".soft_prefetch_mshr_full") 7324626SN/A .desc("number of mshr full events for SW prefetching instrutions") 7338833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7344626SN/A ; 7358833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7368833Sdam.sunwoo@arm.com soft_prefetch_mshr_full.subname(i, system->getMasterName(i)); 7378833Sdam.sunwoo@arm.com } 7384626SN/A 7394626SN/A mshr_no_allocate_misses 7404626SN/A .name(name() +".no_allocate_misses") 7414626SN/A .desc("Number of misses that were no-allocate") 7424626SN/A ; 7434626SN/A 7442810SN/A} 7453503SN/A 7463503SN/Aunsigned int 7473503SN/ABaseCache::drain(Event *de) 7483503SN/A{ 7494626SN/A int count = memSidePort->drain(de) + cpuSidePort->drain(de); 7504626SN/A 7513503SN/A // Set status 7524626SN/A if (count != 0) { 7533503SN/A drainEvent = de; 7543503SN/A 7553503SN/A changeState(SimObject::Draining); 7569152Satgutier@umich.edu DPRINTF(Drain, "Cache not drained\n"); 7574626SN/A return count; 7583503SN/A } 7593503SN/A 7603503SN/A changeState(SimObject::Drained); 7613503SN/A return 0; 7623503SN/A} 763