base.cc revision 8134
12810SN/A/* 22810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use in source and binary forms, with or without 62810SN/A * modification, are permitted provided that the following conditions are 72810SN/A * met: redistributions of source code must retain the above copyright 82810SN/A * notice, this list of conditions and the following disclaimer; 92810SN/A * redistributions in binary form must reproduce the above copyright 102810SN/A * notice, this list of conditions and the following disclaimer in the 112810SN/A * documentation and/or other materials provided with the distribution; 122810SN/A * neither the name of the copyright holders nor the names of its 132810SN/A * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Erik Hallnor 292810SN/A */ 302810SN/A 312810SN/A/** 322810SN/A * @file 332810SN/A * Definition of BaseCache functions. 342810SN/A */ 352810SN/A 363348SN/A#include "cpu/base.hh" 373348SN/A#include "cpu/smt.hh" 385338Sstever@gmail.com#include "mem/cache/base.hh" 395338Sstever@gmail.com#include "mem/cache/mshr.hh" 402810SN/A 412810SN/Ausing namespace std; 422810SN/A 434965SN/ABaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache, 446122SSteve.Reinhardt@amd.com const std::string &_label) 455314SN/A : SimpleTimingPort(_name, _cache), cache(_cache), 465314SN/A label(_label), otherPort(NULL), 476122SSteve.Reinhardt@amd.com blocked(false), mustSendRetry(false) 482810SN/A{ 494475SN/A} 504475SN/A 514475SN/A 525034SN/ABaseCache::BaseCache(const Params *p) 535034SN/A : MemObject(p), 545314SN/A mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs), 555314SN/A writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 564628SN/A MSHRQueue_WriteBuffer), 575034SN/A blkSize(p->block_size), 585034SN/A hitLatency(p->latency), 595034SN/A numTarget(p->tgts_per_mshr), 606122SSteve.Reinhardt@amd.com forwardSnoops(p->forward_snoops), 618134SAli.Saidi@ARM.com isTopLevel(p->is_top_level), 624626SN/A blocked(0), 634626SN/A noTargetMSHR(NULL), 645034SN/A missCount(p->max_miss_count), 656122SSteve.Reinhardt@amd.com drainEvent(NULL), 666978SLisa.Hsu@amd.com addrRange(p->addr_range), 676978SLisa.Hsu@amd.com _numCpus(p->num_cpus) 684458SN/A{ 692810SN/A} 702810SN/A 712811SN/Avoid 722810SN/ABaseCache::CachePort::recvStatusChange(Port::Status status) 732810SN/A{ 744458SN/A if (status == Port::RangeChange) { 754458SN/A otherPort->sendStatusChange(Port::RangeChange); 764458SN/A } 772810SN/A} 782810SN/A 795314SN/A 805314SN/Abool 815314SN/ABaseCache::CachePort::checkFunctional(PacketPtr pkt) 825314SN/A{ 835314SN/A pkt->pushLabel(label); 845314SN/A bool done = SimpleTimingPort::checkFunctional(pkt); 855314SN/A pkt->popLabel(); 865314SN/A return done; 875314SN/A} 885314SN/A 895314SN/A 906227Snate@binkert.orgunsigned 916227Snate@binkert.orgBaseCache::CachePort::deviceBlockSize() const 922810SN/A{ 932810SN/A return cache->getBlockSize(); 942810SN/A} 952810SN/A 963606SN/A 974458SN/Abool 984458SN/ABaseCache::CachePort::recvRetryCommon() 993013SN/A{ 1003236SN/A assert(waitingOnRetry); 1014458SN/A waitingOnRetry = false; 1024458SN/A return false; 1034458SN/A} 1043246SN/A 1053309SN/A 1063013SN/Avoid 1072810SN/ABaseCache::CachePort::setBlocked() 1082810SN/A{ 1093013SN/A assert(!blocked); 1103013SN/A DPRINTF(Cache, "Cache Blocking\n"); 1112810SN/A blocked = true; 1123013SN/A //Clear the retry flag 1133013SN/A mustSendRetry = false; 1142810SN/A} 1152810SN/A 1162810SN/Avoid 1172810SN/ABaseCache::CachePort::clearBlocked() 1182810SN/A{ 1193013SN/A assert(blocked); 1203013SN/A DPRINTF(Cache, "Cache Unblocking\n"); 1213013SN/A blocked = false; 1222897SN/A if (mustSendRetry) 1232897SN/A { 1243013SN/A DPRINTF(Cache, "Cache Sending Retry\n"); 1252897SN/A mustSendRetry = false; 1264666SN/A SendRetryEvent *ev = new SendRetryEvent(this, true); 1274666SN/A // @TODO: need to find a better time (next bus cycle?) 1287823Ssteve.reinhardt@amd.com schedule(ev, curTick() + 1); 1292897SN/A } 1302810SN/A} 1312810SN/A 1322844SN/A 1332810SN/Avoid 1342858SN/ABaseCache::init() 1352858SN/A{ 1362858SN/A if (!cpuSidePort || !memSidePort) 1372858SN/A panic("Cache not hooked up on both sides\n"); 1382858SN/A cpuSidePort->sendStatusChange(Port::RangeChange); 1392858SN/A} 1402858SN/A 1414628SN/A 1422858SN/Avoid 1432810SN/ABaseCache::regStats() 1442810SN/A{ 1452810SN/A using namespace Stats; 1462810SN/A 1472810SN/A // Hit statistics 1484022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1494022SN/A MemCmd cmd(access_idx); 1504022SN/A const string &cstr = cmd.toString(); 1512810SN/A 1522810SN/A hits[access_idx] 1536978SLisa.Hsu@amd.com#if FULL_SYSTEM 1546978SLisa.Hsu@amd.com .init(_numCpus + 1) 1556978SLisa.Hsu@amd.com#else 1566978SLisa.Hsu@amd.com .init(_numCpus) 1576978SLisa.Hsu@amd.com#endif 1582810SN/A .name(name() + "." + cstr + "_hits") 1592810SN/A .desc("number of " + cstr + " hits") 1602810SN/A .flags(total | nozero | nonan) 1612810SN/A ; 1622810SN/A } 1632810SN/A 1644871SN/A// These macros make it easier to sum the right subset of commands and 1654871SN/A// to change the subset of commands that are considered "demand" vs 1664871SN/A// "non-demand" 1674871SN/A#define SUM_DEMAND(s) \ 1684871SN/A (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::ReadExReq]) 1694871SN/A 1704871SN/A// should writebacks be included here? prior code was inconsistent... 1714871SN/A#define SUM_NON_DEMAND(s) \ 1724871SN/A (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 1734871SN/A 1742810SN/A demandHits 1752810SN/A .name(name() + ".demand_hits") 1762810SN/A .desc("number of demand (read+write) hits") 1772810SN/A .flags(total) 1782810SN/A ; 1794871SN/A demandHits = SUM_DEMAND(hits); 1802810SN/A 1812810SN/A overallHits 1822810SN/A .name(name() + ".overall_hits") 1832810SN/A .desc("number of overall hits") 1842810SN/A .flags(total) 1852810SN/A ; 1864871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 1872810SN/A 1882810SN/A // Miss statistics 1894022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1904022SN/A MemCmd cmd(access_idx); 1914022SN/A const string &cstr = cmd.toString(); 1922810SN/A 1932810SN/A misses[access_idx] 1946978SLisa.Hsu@amd.com#if FULL_SYSTEM 1956978SLisa.Hsu@amd.com .init(_numCpus + 1) 1966978SLisa.Hsu@amd.com#else 1976978SLisa.Hsu@amd.com .init(_numCpus) 1986978SLisa.Hsu@amd.com#endif 1992810SN/A .name(name() + "." + cstr + "_misses") 2002810SN/A .desc("number of " + cstr + " misses") 2012810SN/A .flags(total | nozero | nonan) 2022810SN/A ; 2032810SN/A } 2042810SN/A 2052810SN/A demandMisses 2062810SN/A .name(name() + ".demand_misses") 2072810SN/A .desc("number of demand (read+write) misses") 2082810SN/A .flags(total) 2092810SN/A ; 2104871SN/A demandMisses = SUM_DEMAND(misses); 2112810SN/A 2122810SN/A overallMisses 2132810SN/A .name(name() + ".overall_misses") 2142810SN/A .desc("number of overall misses") 2152810SN/A .flags(total) 2162810SN/A ; 2174871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 2182810SN/A 2192810SN/A // Miss latency statistics 2204022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2214022SN/A MemCmd cmd(access_idx); 2224022SN/A const string &cstr = cmd.toString(); 2232810SN/A 2242810SN/A missLatency[access_idx] 2252810SN/A .init(maxThreadsPerCPU) 2262810SN/A .name(name() + "." + cstr + "_miss_latency") 2272810SN/A .desc("number of " + cstr + " miss cycles") 2282810SN/A .flags(total | nozero | nonan) 2292810SN/A ; 2302810SN/A } 2312810SN/A 2322810SN/A demandMissLatency 2332810SN/A .name(name() + ".demand_miss_latency") 2342810SN/A .desc("number of demand (read+write) miss cycles") 2352810SN/A .flags(total) 2362810SN/A ; 2374871SN/A demandMissLatency = SUM_DEMAND(missLatency); 2382810SN/A 2392810SN/A overallMissLatency 2402810SN/A .name(name() + ".overall_miss_latency") 2412810SN/A .desc("number of overall miss cycles") 2422810SN/A .flags(total) 2432810SN/A ; 2444871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 2452810SN/A 2462810SN/A // access formulas 2474022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2484022SN/A MemCmd cmd(access_idx); 2494022SN/A const string &cstr = cmd.toString(); 2502810SN/A 2512810SN/A accesses[access_idx] 2522810SN/A .name(name() + "." + cstr + "_accesses") 2532810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 2542810SN/A .flags(total | nozero | nonan) 2552810SN/A ; 2562810SN/A 2572810SN/A accesses[access_idx] = hits[access_idx] + misses[access_idx]; 2582810SN/A } 2592810SN/A 2602810SN/A demandAccesses 2612810SN/A .name(name() + ".demand_accesses") 2622810SN/A .desc("number of demand (read+write) accesses") 2632810SN/A .flags(total) 2642810SN/A ; 2652810SN/A demandAccesses = demandHits + demandMisses; 2662810SN/A 2672810SN/A overallAccesses 2682810SN/A .name(name() + ".overall_accesses") 2692810SN/A .desc("number of overall (read+write) accesses") 2702810SN/A .flags(total) 2712810SN/A ; 2722810SN/A overallAccesses = overallHits + overallMisses; 2732810SN/A 2742810SN/A // miss rate formulas 2754022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2764022SN/A MemCmd cmd(access_idx); 2774022SN/A const string &cstr = cmd.toString(); 2782810SN/A 2792810SN/A missRate[access_idx] 2802810SN/A .name(name() + "." + cstr + "_miss_rate") 2812810SN/A .desc("miss rate for " + cstr + " accesses") 2822810SN/A .flags(total | nozero | nonan) 2832810SN/A ; 2842810SN/A 2852810SN/A missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 2862810SN/A } 2872810SN/A 2882810SN/A demandMissRate 2892810SN/A .name(name() + ".demand_miss_rate") 2902810SN/A .desc("miss rate for demand accesses") 2912810SN/A .flags(total) 2922810SN/A ; 2932810SN/A demandMissRate = demandMisses / demandAccesses; 2942810SN/A 2952810SN/A overallMissRate 2962810SN/A .name(name() + ".overall_miss_rate") 2972810SN/A .desc("miss rate for overall accesses") 2982810SN/A .flags(total) 2992810SN/A ; 3002810SN/A overallMissRate = overallMisses / overallAccesses; 3012810SN/A 3022810SN/A // miss latency formulas 3034022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3044022SN/A MemCmd cmd(access_idx); 3054022SN/A const string &cstr = cmd.toString(); 3062810SN/A 3072810SN/A avgMissLatency[access_idx] 3082810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 3092810SN/A .desc("average " + cstr + " miss latency") 3102810SN/A .flags(total | nozero | nonan) 3112810SN/A ; 3122810SN/A 3132810SN/A avgMissLatency[access_idx] = 3142810SN/A missLatency[access_idx] / misses[access_idx]; 3152810SN/A } 3162810SN/A 3172810SN/A demandAvgMissLatency 3182810SN/A .name(name() + ".demand_avg_miss_latency") 3192810SN/A .desc("average overall miss latency") 3202810SN/A .flags(total) 3212810SN/A ; 3222810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 3232810SN/A 3242810SN/A overallAvgMissLatency 3252810SN/A .name(name() + ".overall_avg_miss_latency") 3262810SN/A .desc("average overall miss latency") 3272810SN/A .flags(total) 3282810SN/A ; 3292810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 3302810SN/A 3312810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 3322810SN/A blocked_cycles 3332810SN/A .name(name() + ".blocked_cycles") 3342810SN/A .desc("number of cycles access was blocked") 3352810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3362810SN/A .subname(Blocked_NoTargets, "no_targets") 3372810SN/A ; 3382810SN/A 3392810SN/A 3402810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 3412810SN/A blocked_causes 3422810SN/A .name(name() + ".blocked") 3432810SN/A .desc("number of cycles access was blocked") 3442810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3452810SN/A .subname(Blocked_NoTargets, "no_targets") 3462810SN/A ; 3472810SN/A 3482810SN/A avg_blocked 3492810SN/A .name(name() + ".avg_blocked_cycles") 3502810SN/A .desc("average number of cycles each access was blocked") 3512810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3522810SN/A .subname(Blocked_NoTargets, "no_targets") 3532810SN/A ; 3542810SN/A 3552810SN/A avg_blocked = blocked_cycles / blocked_causes; 3562810SN/A 3572810SN/A fastWrites 3582810SN/A .name(name() + ".fast_writes") 3592810SN/A .desc("number of fast writes performed") 3602810SN/A ; 3612810SN/A 3622810SN/A cacheCopies 3632810SN/A .name(name() + ".cache_copies") 3642810SN/A .desc("number of cache copies performed") 3652810SN/A ; 3662826SN/A 3674626SN/A writebacks 3684626SN/A .init(maxThreadsPerCPU) 3694626SN/A .name(name() + ".writebacks") 3704626SN/A .desc("number of writebacks") 3714626SN/A .flags(total) 3724626SN/A ; 3734626SN/A 3744626SN/A // MSHR statistics 3754626SN/A // MSHR hit statistics 3764626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3774626SN/A MemCmd cmd(access_idx); 3784626SN/A const string &cstr = cmd.toString(); 3794626SN/A 3804626SN/A mshr_hits[access_idx] 3814626SN/A .init(maxThreadsPerCPU) 3824626SN/A .name(name() + "." + cstr + "_mshr_hits") 3834626SN/A .desc("number of " + cstr + " MSHR hits") 3844626SN/A .flags(total | nozero | nonan) 3854626SN/A ; 3864626SN/A } 3874626SN/A 3884626SN/A demandMshrHits 3894626SN/A .name(name() + ".demand_mshr_hits") 3904626SN/A .desc("number of demand (read+write) MSHR hits") 3914626SN/A .flags(total) 3924626SN/A ; 3934871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 3944626SN/A 3954626SN/A overallMshrHits 3964626SN/A .name(name() + ".overall_mshr_hits") 3974626SN/A .desc("number of overall MSHR hits") 3984626SN/A .flags(total) 3994626SN/A ; 4004871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 4014626SN/A 4024626SN/A // MSHR miss statistics 4034626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4044626SN/A MemCmd cmd(access_idx); 4054626SN/A const string &cstr = cmd.toString(); 4064626SN/A 4074626SN/A mshr_misses[access_idx] 4084626SN/A .init(maxThreadsPerCPU) 4094626SN/A .name(name() + "." + cstr + "_mshr_misses") 4104626SN/A .desc("number of " + cstr + " MSHR misses") 4114626SN/A .flags(total | nozero | nonan) 4124626SN/A ; 4134626SN/A } 4144626SN/A 4154626SN/A demandMshrMisses 4164626SN/A .name(name() + ".demand_mshr_misses") 4174626SN/A .desc("number of demand (read+write) MSHR misses") 4184626SN/A .flags(total) 4194626SN/A ; 4204871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 4214626SN/A 4224626SN/A overallMshrMisses 4234626SN/A .name(name() + ".overall_mshr_misses") 4244626SN/A .desc("number of overall MSHR misses") 4254626SN/A .flags(total) 4264626SN/A ; 4274871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 4284626SN/A 4294626SN/A // MSHR miss latency statistics 4304626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4314626SN/A MemCmd cmd(access_idx); 4324626SN/A const string &cstr = cmd.toString(); 4334626SN/A 4344626SN/A mshr_miss_latency[access_idx] 4354626SN/A .init(maxThreadsPerCPU) 4364626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 4374626SN/A .desc("number of " + cstr + " MSHR miss cycles") 4384626SN/A .flags(total | nozero | nonan) 4394626SN/A ; 4404626SN/A } 4414626SN/A 4424626SN/A demandMshrMissLatency 4434626SN/A .name(name() + ".demand_mshr_miss_latency") 4444626SN/A .desc("number of demand (read+write) MSHR miss cycles") 4454626SN/A .flags(total) 4464626SN/A ; 4474871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 4484626SN/A 4494626SN/A overallMshrMissLatency 4504626SN/A .name(name() + ".overall_mshr_miss_latency") 4514626SN/A .desc("number of overall MSHR miss cycles") 4524626SN/A .flags(total) 4534626SN/A ; 4544871SN/A overallMshrMissLatency = 4554871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 4564626SN/A 4574626SN/A // MSHR uncacheable statistics 4584626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4594626SN/A MemCmd cmd(access_idx); 4604626SN/A const string &cstr = cmd.toString(); 4614626SN/A 4624626SN/A mshr_uncacheable[access_idx] 4634626SN/A .init(maxThreadsPerCPU) 4644626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 4654626SN/A .desc("number of " + cstr + " MSHR uncacheable") 4664626SN/A .flags(total | nozero | nonan) 4674626SN/A ; 4684626SN/A } 4694626SN/A 4704626SN/A overallMshrUncacheable 4714626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 4724626SN/A .desc("number of overall MSHR uncacheable misses") 4734626SN/A .flags(total) 4744626SN/A ; 4754871SN/A overallMshrUncacheable = 4764871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 4774626SN/A 4784626SN/A // MSHR miss latency statistics 4794626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4804626SN/A MemCmd cmd(access_idx); 4814626SN/A const string &cstr = cmd.toString(); 4824626SN/A 4834626SN/A mshr_uncacheable_lat[access_idx] 4844626SN/A .init(maxThreadsPerCPU) 4854626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 4864626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 4874626SN/A .flags(total | nozero | nonan) 4884626SN/A ; 4894626SN/A } 4904626SN/A 4914626SN/A overallMshrUncacheableLatency 4924626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 4934626SN/A .desc("number of overall MSHR uncacheable cycles") 4944626SN/A .flags(total) 4954626SN/A ; 4964871SN/A overallMshrUncacheableLatency = 4974871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 4984871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 4994626SN/A 5004626SN/A#if 0 5014626SN/A // MSHR access formulas 5024626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5034626SN/A MemCmd cmd(access_idx); 5044626SN/A const string &cstr = cmd.toString(); 5054626SN/A 5064626SN/A mshrAccesses[access_idx] 5074626SN/A .name(name() + "." + cstr + "_mshr_accesses") 5084626SN/A .desc("number of " + cstr + " mshr accesses(hits+misses)") 5094626SN/A .flags(total | nozero | nonan) 5104626SN/A ; 5114626SN/A mshrAccesses[access_idx] = 5124626SN/A mshr_hits[access_idx] + mshr_misses[access_idx] 5134626SN/A + mshr_uncacheable[access_idx]; 5144626SN/A } 5154626SN/A 5164626SN/A demandMshrAccesses 5174626SN/A .name(name() + ".demand_mshr_accesses") 5184626SN/A .desc("number of demand (read+write) mshr accesses") 5194626SN/A .flags(total | nozero | nonan) 5204626SN/A ; 5214626SN/A demandMshrAccesses = demandMshrHits + demandMshrMisses; 5224626SN/A 5234626SN/A overallMshrAccesses 5244626SN/A .name(name() + ".overall_mshr_accesses") 5254626SN/A .desc("number of overall (read+write) mshr accesses") 5264626SN/A .flags(total | nozero | nonan) 5274626SN/A ; 5284626SN/A overallMshrAccesses = overallMshrHits + overallMshrMisses 5294626SN/A + overallMshrUncacheable; 5304626SN/A#endif 5314626SN/A 5324626SN/A // MSHR miss rate formulas 5334626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5344626SN/A MemCmd cmd(access_idx); 5354626SN/A const string &cstr = cmd.toString(); 5364626SN/A 5374626SN/A mshrMissRate[access_idx] 5384626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 5394626SN/A .desc("mshr miss rate for " + cstr + " accesses") 5404626SN/A .flags(total | nozero | nonan) 5414626SN/A ; 5424626SN/A 5434626SN/A mshrMissRate[access_idx] = 5444626SN/A mshr_misses[access_idx] / accesses[access_idx]; 5454626SN/A } 5464626SN/A 5474626SN/A demandMshrMissRate 5484626SN/A .name(name() + ".demand_mshr_miss_rate") 5494626SN/A .desc("mshr miss rate for demand accesses") 5504626SN/A .flags(total) 5514626SN/A ; 5524626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 5534626SN/A 5544626SN/A overallMshrMissRate 5554626SN/A .name(name() + ".overall_mshr_miss_rate") 5564626SN/A .desc("mshr miss rate for overall accesses") 5574626SN/A .flags(total) 5584626SN/A ; 5594626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 5604626SN/A 5614626SN/A // mshrMiss latency formulas 5624626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5634626SN/A MemCmd cmd(access_idx); 5644626SN/A const string &cstr = cmd.toString(); 5654626SN/A 5664626SN/A avgMshrMissLatency[access_idx] 5674626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 5684626SN/A .desc("average " + cstr + " mshr miss latency") 5694626SN/A .flags(total | nozero | nonan) 5704626SN/A ; 5714626SN/A 5724626SN/A avgMshrMissLatency[access_idx] = 5734626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 5744626SN/A } 5754626SN/A 5764626SN/A demandAvgMshrMissLatency 5774626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 5784626SN/A .desc("average overall mshr miss latency") 5794626SN/A .flags(total) 5804626SN/A ; 5814626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 5824626SN/A 5834626SN/A overallAvgMshrMissLatency 5844626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 5854626SN/A .desc("average overall mshr miss latency") 5864626SN/A .flags(total) 5874626SN/A ; 5884626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 5894626SN/A 5904626SN/A // mshrUncacheable latency formulas 5914626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5924626SN/A MemCmd cmd(access_idx); 5934626SN/A const string &cstr = cmd.toString(); 5944626SN/A 5954626SN/A avgMshrUncacheableLatency[access_idx] 5964626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 5974626SN/A .desc("average " + cstr + " mshr uncacheable latency") 5984626SN/A .flags(total | nozero | nonan) 5994626SN/A ; 6004626SN/A 6014626SN/A avgMshrUncacheableLatency[access_idx] = 6024626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 6034626SN/A } 6044626SN/A 6054626SN/A overallAvgMshrUncacheableLatency 6064626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 6074626SN/A .desc("average overall mshr uncacheable latency") 6084626SN/A .flags(total) 6094626SN/A ; 6104626SN/A overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable; 6114626SN/A 6124626SN/A mshr_cap_events 6134626SN/A .init(maxThreadsPerCPU) 6144626SN/A .name(name() + ".mshr_cap_events") 6154626SN/A .desc("number of times MSHR cap was activated") 6164626SN/A .flags(total) 6174626SN/A ; 6184626SN/A 6194626SN/A //software prefetching stats 6204626SN/A soft_prefetch_mshr_full 6214626SN/A .init(maxThreadsPerCPU) 6224626SN/A .name(name() + ".soft_prefetch_mshr_full") 6234626SN/A .desc("number of mshr full events for SW prefetching instrutions") 6244626SN/A .flags(total) 6254626SN/A ; 6264626SN/A 6274626SN/A mshr_no_allocate_misses 6284626SN/A .name(name() +".no_allocate_misses") 6294626SN/A .desc("Number of misses that were no-allocate") 6304626SN/A ; 6314626SN/A 6322810SN/A} 6333503SN/A 6343503SN/Aunsigned int 6353503SN/ABaseCache::drain(Event *de) 6363503SN/A{ 6374626SN/A int count = memSidePort->drain(de) + cpuSidePort->drain(de); 6384626SN/A 6393503SN/A // Set status 6404626SN/A if (count != 0) { 6413503SN/A drainEvent = de; 6423503SN/A 6433503SN/A changeState(SimObject::Draining); 6444626SN/A return count; 6453503SN/A } 6463503SN/A 6473503SN/A changeState(SimObject::Drained); 6483503SN/A return 0; 6493503SN/A} 650