base.cc revision 13945
12810SN/A/* 213932Snikos.nikoleris@arm.com * Copyright (c) 2012-2013, 2018-2019 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 4112724Snikos.nikoleris@arm.com * Nikos Nikoleris 422810SN/A */ 432810SN/A 442810SN/A/** 452810SN/A * @file 462810SN/A * Definition of BaseCache functions. 472810SN/A */ 482810SN/A 4911486Snikos.nikoleris@arm.com#include "mem/cache/base.hh" 5011486Snikos.nikoleris@arm.com 5112724Snikos.nikoleris@arm.com#include "base/compiler.hh" 5212724Snikos.nikoleris@arm.com#include "base/logging.hh" 538232Snate@binkert.org#include "debug/Cache.hh" 5412724Snikos.nikoleris@arm.com#include "debug/CachePort.hh" 5513222Sodanrc@yahoo.com.br#include "debug/CacheRepl.hh" 5612724Snikos.nikoleris@arm.com#include "debug/CacheVerbose.hh" 5713945Sodanrc@yahoo.com.br#include "mem/cache/compressors/base.hh" 5811486Snikos.nikoleris@arm.com#include "mem/cache/mshr.hh" 5912724Snikos.nikoleris@arm.com#include "mem/cache/prefetch/base.hh" 6012724Snikos.nikoleris@arm.com#include "mem/cache/queue_entry.hh" 6112724Snikos.nikoleris@arm.com#include "params/BaseCache.hh" 6213352Snikos.nikoleris@arm.com#include "params/WriteAllocator.hh" 6312724Snikos.nikoleris@arm.com#include "sim/core.hh" 6412724Snikos.nikoleris@arm.com 6512724Snikos.nikoleris@arm.comclass BaseMasterPort; 6612724Snikos.nikoleris@arm.comclass BaseSlavePort; 672810SN/A 682810SN/Ausing namespace std; 692810SN/A 708856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 718856Sandreas.hansson@arm.com BaseCache *_cache, 728856Sandreas.hansson@arm.com const std::string &_label) 7313564Snikos.nikoleris@arm.com : QueuedSlavePort(_name, _cache, queue), 7413564Snikos.nikoleris@arm.com queue(*_cache, *this, true, _label), 7512084Sspwilson2@wisc.edu blocked(false), mustSendRetry(false), 7612084Sspwilson2@wisc.edu sendRetryEvent([this]{ processSendRetry(); }, _name) 778856Sandreas.hansson@arm.com{ 788856Sandreas.hansson@arm.com} 794475SN/A 8011053Sandreas.hansson@arm.comBaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) 8113892Sgabeblack@google.com : ClockedObject(p), 8212724Snikos.nikoleris@arm.com cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"), 8312724Snikos.nikoleris@arm.com memSidePort(p->name + ".mem_side", this, "MemSidePort"), 8411377Sandreas.hansson@arm.com mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below 8511377Sandreas.hansson@arm.com writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below 8612724Snikos.nikoleris@arm.com tags(p->tags), 8713945Sodanrc@yahoo.com.br compressor(p->compressor), 8812724Snikos.nikoleris@arm.com prefetcher(p->prefetcher), 8913352Snikos.nikoleris@arm.com writeAllocator(p->write_allocator), 9012724Snikos.nikoleris@arm.com writebackClean(p->writeback_clean), 9112724Snikos.nikoleris@arm.com tempBlockWriteback(nullptr), 9212724Snikos.nikoleris@arm.com writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); }, 9312724Snikos.nikoleris@arm.com name(), false, 9412724Snikos.nikoleris@arm.com EventBase::Delayed_Writeback_Pri), 9511053Sandreas.hansson@arm.com blkSize(blk_size), 9611722Ssophiane.senni@gmail.com lookupLatency(p->tag_latency), 9711722Ssophiane.senni@gmail.com dataLatency(p->data_latency), 9811722Ssophiane.senni@gmail.com forwardLatency(p->tag_latency), 9911722Ssophiane.senni@gmail.com fillLatency(p->data_latency), 1009263Smrinmoy.ghosh@arm.com responseLatency(p->response_latency), 10113418Sodanrc@yahoo.com.br sequentialAccess(p->sequential_access), 1025034SN/A numTarget(p->tgts_per_mshr), 10311331Sandreas.hansson@arm.com forwardSnoops(true), 10412724Snikos.nikoleris@arm.com clusivity(p->clusivity), 10510884Sandreas.hansson@arm.com isReadOnly(p->is_read_only), 1064626SN/A blocked(0), 10710360Sandreas.hansson@arm.com order(0), 10811484Snikos.nikoleris@arm.com noTargetMSHR(nullptr), 1095034SN/A missCount(p->max_miss_count), 1108883SAli.Saidi@ARM.com addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 1118833Sdam.sunwoo@arm.com system(p->system) 1124458SN/A{ 11311377Sandreas.hansson@arm.com // the MSHR queue has no reserve entries as we check the MSHR 11411377Sandreas.hansson@arm.com // queue on every single allocation, whereas the write queue has 11511377Sandreas.hansson@arm.com // as many reserve entries as we have MSHRs, since every MSHR may 11611377Sandreas.hansson@arm.com // eventually require a writeback, and we do not check the write 11711377Sandreas.hansson@arm.com // buffer before committing to an MSHR 11811377Sandreas.hansson@arm.com 11911331Sandreas.hansson@arm.com // forward snoops is overridden in init() once we can query 12011331Sandreas.hansson@arm.com // whether the connected master is actually snooping or not 12112724Snikos.nikoleris@arm.com 12212843Srmk35@cl.cam.ac.uk tempBlock = new TempCacheBlk(blkSize); 12312724Snikos.nikoleris@arm.com 12413419Sodanrc@yahoo.com.br tags->tagsInit(); 12512724Snikos.nikoleris@arm.com if (prefetcher) 12612724Snikos.nikoleris@arm.com prefetcher->setCache(this); 12712724Snikos.nikoleris@arm.com} 12812724Snikos.nikoleris@arm.com 12912724Snikos.nikoleris@arm.comBaseCache::~BaseCache() 13012724Snikos.nikoleris@arm.com{ 13112724Snikos.nikoleris@arm.com delete tempBlock; 1322810SN/A} 1332810SN/A 1343013SN/Avoid 1358856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::setBlocked() 1362810SN/A{ 1373013SN/A assert(!blocked); 13810714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is blocking new requests\n"); 1392810SN/A blocked = true; 1409614Srene.dejong@arm.com // if we already scheduled a retry in this cycle, but it has not yet 1419614Srene.dejong@arm.com // happened, cancel it 1429614Srene.dejong@arm.com if (sendRetryEvent.scheduled()) { 14310345SCurtis.Dunham@arm.com owner.deschedule(sendRetryEvent); 14410714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port descheduled retry\n"); 14510345SCurtis.Dunham@arm.com mustSendRetry = true; 1469614Srene.dejong@arm.com } 1472810SN/A} 1482810SN/A 1492810SN/Avoid 1508856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::clearBlocked() 1512810SN/A{ 1523013SN/A assert(blocked); 15310714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is accepting new requests\n"); 1543013SN/A blocked = false; 1558856Sandreas.hansson@arm.com if (mustSendRetry) { 15610714Sandreas.hansson@arm.com // @TODO: need to find a better time (next cycle?) 1578922Swilliam.wang@arm.com owner.schedule(sendRetryEvent, curTick() + 1); 1582897SN/A } 1592810SN/A} 1602810SN/A 16110344Sandreas.hansson@arm.comvoid 16210344Sandreas.hansson@arm.comBaseCache::CacheSlavePort::processSendRetry() 16310344Sandreas.hansson@arm.com{ 16410714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is sending retry\n"); 16510344Sandreas.hansson@arm.com 16610344Sandreas.hansson@arm.com // reset the flag and call retry 16710344Sandreas.hansson@arm.com mustSendRetry = false; 16810713Sandreas.hansson@arm.com sendRetryReq(); 16910344Sandreas.hansson@arm.com} 1702844SN/A 17112730Sodanrc@yahoo.com.brAddr 17212730Sodanrc@yahoo.com.brBaseCache::regenerateBlkAddr(CacheBlk* blk) 17312730Sodanrc@yahoo.com.br{ 17412730Sodanrc@yahoo.com.br if (blk != tempBlock) { 17512730Sodanrc@yahoo.com.br return tags->regenerateBlkAddr(blk); 17612730Sodanrc@yahoo.com.br } else { 17712730Sodanrc@yahoo.com.br return tempBlock->getAddr(); 17812730Sodanrc@yahoo.com.br } 17912730Sodanrc@yahoo.com.br} 18012730Sodanrc@yahoo.com.br 1812810SN/Avoid 1822858SN/ABaseCache::init() 1832858SN/A{ 18412724Snikos.nikoleris@arm.com if (!cpuSidePort.isConnected() || !memSidePort.isConnected()) 1858922Swilliam.wang@arm.com fatal("Cache ports on %s are not connected\n", name()); 18612724Snikos.nikoleris@arm.com cpuSidePort.sendRangeChange(); 18712724Snikos.nikoleris@arm.com forwardSnoops = cpuSidePort.isSnooping(); 1882858SN/A} 1892858SN/A 19013784Sgabeblack@google.comPort & 19113784Sgabeblack@google.comBaseCache::getPort(const std::string &if_name, PortID idx) 1928922Swilliam.wang@arm.com{ 1938922Swilliam.wang@arm.com if (if_name == "mem_side") { 19412724Snikos.nikoleris@arm.com return memSidePort; 19513784Sgabeblack@google.com } else if (if_name == "cpu_side") { 19613784Sgabeblack@google.com return cpuSidePort; 1978922Swilliam.wang@arm.com } else { 19813892Sgabeblack@google.com return ClockedObject::getPort(if_name, idx); 1998922Swilliam.wang@arm.com } 2008922Swilliam.wang@arm.com} 2014628SN/A 20210821Sandreas.hansson@arm.combool 20310821Sandreas.hansson@arm.comBaseCache::inRange(Addr addr) const 20410821Sandreas.hansson@arm.com{ 20510821Sandreas.hansson@arm.com for (const auto& r : addrRanges) { 20610821Sandreas.hansson@arm.com if (r.contains(addr)) { 20710821Sandreas.hansson@arm.com return true; 20810821Sandreas.hansson@arm.com } 20910821Sandreas.hansson@arm.com } 21010821Sandreas.hansson@arm.com return false; 21110821Sandreas.hansson@arm.com} 21210821Sandreas.hansson@arm.com 2132858SN/Avoid 21412724Snikos.nikoleris@arm.comBaseCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) 21512724Snikos.nikoleris@arm.com{ 21612724Snikos.nikoleris@arm.com if (pkt->needsResponse()) { 21713745Sodanrc@yahoo.com.br // These delays should have been consumed by now 21813745Sodanrc@yahoo.com.br assert(pkt->headerDelay == 0); 21913745Sodanrc@yahoo.com.br assert(pkt->payloadDelay == 0); 22013745Sodanrc@yahoo.com.br 22112724Snikos.nikoleris@arm.com pkt->makeTimingResponse(); 22212724Snikos.nikoleris@arm.com 22312724Snikos.nikoleris@arm.com // In this case we are considering request_time that takes 22412724Snikos.nikoleris@arm.com // into account the delay of the xbar, if any, and just 22512724Snikos.nikoleris@arm.com // lat, neglecting responseLatency, modelling hit latency 22613418Sodanrc@yahoo.com.br // just as the value of lat overriden by access(), which calls 22713418Sodanrc@yahoo.com.br // the calculateAccessLatency() function. 22813564Snikos.nikoleris@arm.com cpuSidePort.schedTimingResp(pkt, request_time); 22912724Snikos.nikoleris@arm.com } else { 23012724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, 23112724Snikos.nikoleris@arm.com pkt->print()); 23212724Snikos.nikoleris@arm.com 23312724Snikos.nikoleris@arm.com // queue the packet for deletion, as the sending cache is 23412724Snikos.nikoleris@arm.com // still relying on it; if the block is found in access(), 23512724Snikos.nikoleris@arm.com // CleanEvict and Writeback messages will be deleted 23612724Snikos.nikoleris@arm.com // here as well 23712724Snikos.nikoleris@arm.com pendingDelete.reset(pkt); 23812724Snikos.nikoleris@arm.com } 23912724Snikos.nikoleris@arm.com} 24012724Snikos.nikoleris@arm.com 24112724Snikos.nikoleris@arm.comvoid 24212724Snikos.nikoleris@arm.comBaseCache::handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk, 24312724Snikos.nikoleris@arm.com Tick forward_time, Tick request_time) 24412724Snikos.nikoleris@arm.com{ 24513352Snikos.nikoleris@arm.com if (writeAllocator && 24613352Snikos.nikoleris@arm.com pkt && pkt->isWrite() && !pkt->req->isUncacheable()) { 24713352Snikos.nikoleris@arm.com writeAllocator->updateMode(pkt->getAddr(), pkt->getSize(), 24813352Snikos.nikoleris@arm.com pkt->getBlockAddr(blkSize)); 24913352Snikos.nikoleris@arm.com } 25013352Snikos.nikoleris@arm.com 25112724Snikos.nikoleris@arm.com if (mshr) { 25212724Snikos.nikoleris@arm.com /// MSHR hit 25312724Snikos.nikoleris@arm.com /// @note writebacks will be checked in getNextMSHR() 25412724Snikos.nikoleris@arm.com /// for any conflicting requests to the same block 25512724Snikos.nikoleris@arm.com 25612724Snikos.nikoleris@arm.com //@todo remove hw_pf here 25712724Snikos.nikoleris@arm.com 25812724Snikos.nikoleris@arm.com // Coalesce unless it was a software prefetch (see above). 25912724Snikos.nikoleris@arm.com if (pkt) { 26012724Snikos.nikoleris@arm.com assert(!pkt->isWriteback()); 26112724Snikos.nikoleris@arm.com // CleanEvicts corresponding to blocks which have 26212724Snikos.nikoleris@arm.com // outstanding requests in MSHRs are simply sunk here 26312724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 26412724Snikos.nikoleris@arm.com pendingDelete.reset(pkt); 26512724Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 26612724Snikos.nikoleris@arm.com // A WriteClean should never coalesce with any 26712724Snikos.nikoleris@arm.com // outstanding cache maintenance requests. 26812724Snikos.nikoleris@arm.com 26912724Snikos.nikoleris@arm.com // We use forward_time here because there is an 27012724Snikos.nikoleris@arm.com // uncached memory write, forwarded to WriteBuffer. 27112724Snikos.nikoleris@arm.com allocateWriteBuffer(pkt, forward_time); 27212724Snikos.nikoleris@arm.com } else { 27312724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__, 27412724Snikos.nikoleris@arm.com pkt->print()); 27512724Snikos.nikoleris@arm.com 27612724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 27712724Snikos.nikoleris@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 27812724Snikos.nikoleris@arm.com 27912724Snikos.nikoleris@arm.com // We use forward_time here because it is the same 28012724Snikos.nikoleris@arm.com // considering new targets. We have multiple 28112724Snikos.nikoleris@arm.com // requests for the same address here. It 28212724Snikos.nikoleris@arm.com // specifies the latency to allocate an internal 28312724Snikos.nikoleris@arm.com // buffer and to schedule an event to the queued 28412724Snikos.nikoleris@arm.com // port and also takes into account the additional 28512724Snikos.nikoleris@arm.com // delay of the xbar. 28612724Snikos.nikoleris@arm.com mshr->allocateTarget(pkt, forward_time, order++, 28712724Snikos.nikoleris@arm.com allocOnFill(pkt->cmd)); 28812724Snikos.nikoleris@arm.com if (mshr->getNumTargets() == numTarget) { 28912724Snikos.nikoleris@arm.com noTargetMSHR = mshr; 29012724Snikos.nikoleris@arm.com setBlocked(Blocked_NoTargets); 29112724Snikos.nikoleris@arm.com // need to be careful with this... if this mshr isn't 29212724Snikos.nikoleris@arm.com // ready yet (i.e. time > curTick()), we don't want to 29312724Snikos.nikoleris@arm.com // move it ahead of mshrs that are ready 29412724Snikos.nikoleris@arm.com // mshrQueue.moveToFront(mshr); 29512724Snikos.nikoleris@arm.com } 29612724Snikos.nikoleris@arm.com } 29712724Snikos.nikoleris@arm.com } 29812724Snikos.nikoleris@arm.com } else { 29912724Snikos.nikoleris@arm.com // no MSHR 30012724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 30112724Snikos.nikoleris@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 30212724Snikos.nikoleris@arm.com 30312724Snikos.nikoleris@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean) { 30412724Snikos.nikoleris@arm.com // We use forward_time here because there is an 30512724Snikos.nikoleris@arm.com // writeback or writeclean, forwarded to WriteBuffer. 30612724Snikos.nikoleris@arm.com allocateWriteBuffer(pkt, forward_time); 30712724Snikos.nikoleris@arm.com } else { 30812724Snikos.nikoleris@arm.com if (blk && blk->isValid()) { 30912724Snikos.nikoleris@arm.com // If we have a write miss to a valid block, we 31012724Snikos.nikoleris@arm.com // need to mark the block non-readable. Otherwise 31112724Snikos.nikoleris@arm.com // if we allow reads while there's an outstanding 31212724Snikos.nikoleris@arm.com // write miss, the read could return stale data 31312724Snikos.nikoleris@arm.com // out of the cache block... a more aggressive 31412724Snikos.nikoleris@arm.com // system could detect the overlap (if any) and 31512724Snikos.nikoleris@arm.com // forward data out of the MSHRs, but we don't do 31612724Snikos.nikoleris@arm.com // that yet. Note that we do need to leave the 31712724Snikos.nikoleris@arm.com // block valid so that it stays in the cache, in 31812724Snikos.nikoleris@arm.com // case we get an upgrade response (and hence no 31912724Snikos.nikoleris@arm.com // new data) when the write miss completes. 32012724Snikos.nikoleris@arm.com // As long as CPUs do proper store/load forwarding 32112724Snikos.nikoleris@arm.com // internally, and have a sufficiently weak memory 32212724Snikos.nikoleris@arm.com // model, this is probably unnecessary, but at some 32312724Snikos.nikoleris@arm.com // point it must have seemed like we needed it... 32412724Snikos.nikoleris@arm.com assert((pkt->needsWritable() && !blk->isWritable()) || 32512724Snikos.nikoleris@arm.com pkt->req->isCacheMaintenance()); 32612724Snikos.nikoleris@arm.com blk->status &= ~BlkReadable; 32712724Snikos.nikoleris@arm.com } 32812724Snikos.nikoleris@arm.com // Here we are using forward_time, modelling the latency of 32912724Snikos.nikoleris@arm.com // a miss (outbound) just as forwardLatency, neglecting the 33012724Snikos.nikoleris@arm.com // lookupLatency component. 33112724Snikos.nikoleris@arm.com allocateMissBuffer(pkt, forward_time); 33212724Snikos.nikoleris@arm.com } 33312724Snikos.nikoleris@arm.com } 33412724Snikos.nikoleris@arm.com} 33512724Snikos.nikoleris@arm.com 33612724Snikos.nikoleris@arm.comvoid 33712724Snikos.nikoleris@arm.comBaseCache::recvTimingReq(PacketPtr pkt) 33812724Snikos.nikoleris@arm.com{ 33912724Snikos.nikoleris@arm.com // anything that is merely forwarded pays for the forward latency and 34012724Snikos.nikoleris@arm.com // the delay provided by the crossbar 34112724Snikos.nikoleris@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 34212724Snikos.nikoleris@arm.com 34313418Sodanrc@yahoo.com.br Cycles lat; 34412724Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 34512724Snikos.nikoleris@arm.com bool satisfied = false; 34612724Snikos.nikoleris@arm.com { 34712724Snikos.nikoleris@arm.com PacketList writebacks; 34812724Snikos.nikoleris@arm.com // Note that lat is passed by reference here. The function 34913418Sodanrc@yahoo.com.br // access() will set the lat value. 35012724Snikos.nikoleris@arm.com satisfied = access(pkt, blk, lat, writebacks); 35112724Snikos.nikoleris@arm.com 35213747Sodanrc@yahoo.com.br // After the evicted blocks are selected, they must be forwarded 35313747Sodanrc@yahoo.com.br // to the write buffer to ensure they logically precede anything 35413747Sodanrc@yahoo.com.br // happening below 35513747Sodanrc@yahoo.com.br doWritebacks(writebacks, clockEdge(lat + forwardLatency)); 35612724Snikos.nikoleris@arm.com } 35712724Snikos.nikoleris@arm.com 35812724Snikos.nikoleris@arm.com // Here we charge the headerDelay that takes into account the latencies 35912724Snikos.nikoleris@arm.com // of the bus, if the packet comes from it. 36013418Sodanrc@yahoo.com.br // The latency charged is just the value set by the access() function. 36112724Snikos.nikoleris@arm.com // In case of a hit we are neglecting response latency. 36212724Snikos.nikoleris@arm.com // In case of a miss we are neglecting forward latency. 36313746Sodanrc@yahoo.com.br Tick request_time = clockEdge(lat); 36412724Snikos.nikoleris@arm.com // Here we reset the timing of the packet. 36512724Snikos.nikoleris@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 36612724Snikos.nikoleris@arm.com 36712724Snikos.nikoleris@arm.com if (satisfied) { 36813416Sjavier.bueno@metempsy.com // notify before anything else as later handleTimingReqHit might turn 36913416Sjavier.bueno@metempsy.com // the packet in a response 37013416Sjavier.bueno@metempsy.com ppHit->notify(pkt); 37112724Snikos.nikoleris@arm.com 37213416Sjavier.bueno@metempsy.com if (prefetcher && blk && blk->wasPrefetched()) { 37313416Sjavier.bueno@metempsy.com blk->status &= ~BlkHWPrefetched; 37412724Snikos.nikoleris@arm.com } 37512724Snikos.nikoleris@arm.com 37612724Snikos.nikoleris@arm.com handleTimingReqHit(pkt, blk, request_time); 37712724Snikos.nikoleris@arm.com } else { 37812724Snikos.nikoleris@arm.com handleTimingReqMiss(pkt, blk, forward_time, request_time); 37912724Snikos.nikoleris@arm.com 38013416Sjavier.bueno@metempsy.com ppMiss->notify(pkt); 38112724Snikos.nikoleris@arm.com } 38212724Snikos.nikoleris@arm.com 38313416Sjavier.bueno@metempsy.com if (prefetcher) { 38413416Sjavier.bueno@metempsy.com // track time of availability of next prefetch, if any 38513416Sjavier.bueno@metempsy.com Tick next_pf_time = prefetcher->nextPrefetchReadyTime(); 38613416Sjavier.bueno@metempsy.com if (next_pf_time != MaxTick) { 38713416Sjavier.bueno@metempsy.com schedMemSideSendEvent(next_pf_time); 38813416Sjavier.bueno@metempsy.com } 38912724Snikos.nikoleris@arm.com } 39012724Snikos.nikoleris@arm.com} 39112724Snikos.nikoleris@arm.com 39212724Snikos.nikoleris@arm.comvoid 39312724Snikos.nikoleris@arm.comBaseCache::handleUncacheableWriteResp(PacketPtr pkt) 39412724Snikos.nikoleris@arm.com{ 39512724Snikos.nikoleris@arm.com Tick completion_time = clockEdge(responseLatency) + 39612724Snikos.nikoleris@arm.com pkt->headerDelay + pkt->payloadDelay; 39712724Snikos.nikoleris@arm.com 39812724Snikos.nikoleris@arm.com // Reset the bus additional time as it is now accounted for 39912724Snikos.nikoleris@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 40012724Snikos.nikoleris@arm.com 40113564Snikos.nikoleris@arm.com cpuSidePort.schedTimingResp(pkt, completion_time); 40212724Snikos.nikoleris@arm.com} 40312724Snikos.nikoleris@arm.com 40412724Snikos.nikoleris@arm.comvoid 40512724Snikos.nikoleris@arm.comBaseCache::recvTimingResp(PacketPtr pkt) 40612724Snikos.nikoleris@arm.com{ 40712724Snikos.nikoleris@arm.com assert(pkt->isResponse()); 40812724Snikos.nikoleris@arm.com 40912724Snikos.nikoleris@arm.com // all header delay should be paid for by the crossbar, unless 41012724Snikos.nikoleris@arm.com // this is a prefetch response from above 41112724Snikos.nikoleris@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 41212724Snikos.nikoleris@arm.com "%s saw a non-zero packet delay\n", name()); 41312724Snikos.nikoleris@arm.com 41412724Snikos.nikoleris@arm.com const bool is_error = pkt->isError(); 41512724Snikos.nikoleris@arm.com 41612724Snikos.nikoleris@arm.com if (is_error) { 41712724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Cache received %s with error\n", __func__, 41812724Snikos.nikoleris@arm.com pkt->print()); 41912724Snikos.nikoleris@arm.com } 42012724Snikos.nikoleris@arm.com 42112724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Handling response %s\n", __func__, 42212724Snikos.nikoleris@arm.com pkt->print()); 42312724Snikos.nikoleris@arm.com 42412724Snikos.nikoleris@arm.com // if this is a write, we should be looking at an uncacheable 42512724Snikos.nikoleris@arm.com // write 42612724Snikos.nikoleris@arm.com if (pkt->isWrite()) { 42712724Snikos.nikoleris@arm.com assert(pkt->req->isUncacheable()); 42812724Snikos.nikoleris@arm.com handleUncacheableWriteResp(pkt); 42912724Snikos.nikoleris@arm.com return; 43012724Snikos.nikoleris@arm.com } 43112724Snikos.nikoleris@arm.com 43212724Snikos.nikoleris@arm.com // we have dealt with any (uncacheable) writes above, from here on 43312724Snikos.nikoleris@arm.com // we know we are dealing with an MSHR due to a miss or a prefetch 43412724Snikos.nikoleris@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState()); 43512724Snikos.nikoleris@arm.com assert(mshr); 43612724Snikos.nikoleris@arm.com 43712724Snikos.nikoleris@arm.com if (mshr == noTargetMSHR) { 43812724Snikos.nikoleris@arm.com // we always clear at least one target 43912724Snikos.nikoleris@arm.com clearBlocked(Blocked_NoTargets); 44012724Snikos.nikoleris@arm.com noTargetMSHR = nullptr; 44112724Snikos.nikoleris@arm.com } 44212724Snikos.nikoleris@arm.com 44312724Snikos.nikoleris@arm.com // Initial target is used just for stats 44413859Sodanrc@yahoo.com.br QueueEntry::Target *initial_tgt = mshr->getTarget(); 44512724Snikos.nikoleris@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 44612724Snikos.nikoleris@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 44712724Snikos.nikoleris@arm.com 44812724Snikos.nikoleris@arm.com if (pkt->req->isUncacheable()) { 44912724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 45012724Snikos.nikoleris@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 45112724Snikos.nikoleris@arm.com miss_latency; 45212724Snikos.nikoleris@arm.com } else { 45312724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 45412724Snikos.nikoleris@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 45512724Snikos.nikoleris@arm.com miss_latency; 45612724Snikos.nikoleris@arm.com } 45712724Snikos.nikoleris@arm.com 45812724Snikos.nikoleris@arm.com PacketList writebacks; 45912724Snikos.nikoleris@arm.com 46012724Snikos.nikoleris@arm.com bool is_fill = !mshr->isForward && 46113350Snikos.nikoleris@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp || 46213350Snikos.nikoleris@arm.com mshr->wasWholeLineWrite); 46313350Snikos.nikoleris@arm.com 46413350Snikos.nikoleris@arm.com // make sure that if the mshr was due to a whole line write then 46513350Snikos.nikoleris@arm.com // the response is an invalidation 46613350Snikos.nikoleris@arm.com assert(!mshr->wasWholeLineWrite || pkt->isInvalidate()); 46712724Snikos.nikoleris@arm.com 46812724Snikos.nikoleris@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 46912724Snikos.nikoleris@arm.com 47012724Snikos.nikoleris@arm.com if (is_fill && !is_error) { 47112724Snikos.nikoleris@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 47212724Snikos.nikoleris@arm.com pkt->getAddr()); 47312724Snikos.nikoleris@arm.com 47413352Snikos.nikoleris@arm.com const bool allocate = (writeAllocator && mshr->wasWholeLineWrite) ? 47513352Snikos.nikoleris@arm.com writeAllocator->allocate() : mshr->allocOnFill(); 47613352Snikos.nikoleris@arm.com blk = handleFill(pkt, blk, writebacks, allocate); 47712724Snikos.nikoleris@arm.com assert(blk != nullptr); 47813717Sivan.pizarro@metempsy.com ppFill->notify(pkt); 47912724Snikos.nikoleris@arm.com } 48012724Snikos.nikoleris@arm.com 48112724Snikos.nikoleris@arm.com if (blk && blk->isValid() && pkt->isClean() && !pkt->isInvalidate()) { 48212724Snikos.nikoleris@arm.com // The block was marked not readable while there was a pending 48312724Snikos.nikoleris@arm.com // cache maintenance operation, restore its flag. 48412724Snikos.nikoleris@arm.com blk->status |= BlkReadable; 48512794Snikos.nikoleris@arm.com 48612794Snikos.nikoleris@arm.com // This was a cache clean operation (without invalidate) 48712794Snikos.nikoleris@arm.com // and we have a copy of the block already. Since there 48812794Snikos.nikoleris@arm.com // is no invalidation, we can promote targets that don't 48912794Snikos.nikoleris@arm.com // require a writable copy 49012794Snikos.nikoleris@arm.com mshr->promoteReadable(); 49112724Snikos.nikoleris@arm.com } 49212724Snikos.nikoleris@arm.com 49312724Snikos.nikoleris@arm.com if (blk && blk->isWritable() && !pkt->req->isCacheInvalidate()) { 49412724Snikos.nikoleris@arm.com // If at this point the referenced block is writable and the 49512724Snikos.nikoleris@arm.com // response is not a cache invalidate, we promote targets that 49612724Snikos.nikoleris@arm.com // were deferred as we couldn't guarrantee a writable copy 49712724Snikos.nikoleris@arm.com mshr->promoteWritable(); 49812724Snikos.nikoleris@arm.com } 49912724Snikos.nikoleris@arm.com 50013478Sodanrc@yahoo.com.br serviceMSHRTargets(mshr, pkt, blk); 50112724Snikos.nikoleris@arm.com 50212724Snikos.nikoleris@arm.com if (mshr->promoteDeferredTargets()) { 50312724Snikos.nikoleris@arm.com // avoid later read getting stale data while write miss is 50412724Snikos.nikoleris@arm.com // outstanding.. see comment in timingAccess() 50512724Snikos.nikoleris@arm.com if (blk) { 50612724Snikos.nikoleris@arm.com blk->status &= ~BlkReadable; 50712724Snikos.nikoleris@arm.com } 50812724Snikos.nikoleris@arm.com mshrQueue.markPending(mshr); 50912724Snikos.nikoleris@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 51012724Snikos.nikoleris@arm.com } else { 51112724Snikos.nikoleris@arm.com // while we deallocate an mshr from the queue we still have to 51212724Snikos.nikoleris@arm.com // check the isFull condition before and after as we might 51312724Snikos.nikoleris@arm.com // have been using the reserved entries already 51412724Snikos.nikoleris@arm.com const bool was_full = mshrQueue.isFull(); 51512724Snikos.nikoleris@arm.com mshrQueue.deallocate(mshr); 51612724Snikos.nikoleris@arm.com if (was_full && !mshrQueue.isFull()) { 51712724Snikos.nikoleris@arm.com clearBlocked(Blocked_NoMSHRs); 51812724Snikos.nikoleris@arm.com } 51912724Snikos.nikoleris@arm.com 52012724Snikos.nikoleris@arm.com // Request the bus for a prefetch if this deallocation freed enough 52112724Snikos.nikoleris@arm.com // MSHRs for a prefetch to take place 52212724Snikos.nikoleris@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 52312724Snikos.nikoleris@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 52412724Snikos.nikoleris@arm.com clockEdge()); 52512724Snikos.nikoleris@arm.com if (next_pf_time != MaxTick) 52612724Snikos.nikoleris@arm.com schedMemSideSendEvent(next_pf_time); 52712724Snikos.nikoleris@arm.com } 52812724Snikos.nikoleris@arm.com } 52912724Snikos.nikoleris@arm.com 53012724Snikos.nikoleris@arm.com // if we used temp block, check to see if its valid and then clear it out 53112724Snikos.nikoleris@arm.com if (blk == tempBlock && tempBlock->isValid()) { 53212724Snikos.nikoleris@arm.com evictBlock(blk, writebacks); 53312724Snikos.nikoleris@arm.com } 53412724Snikos.nikoleris@arm.com 53512724Snikos.nikoleris@arm.com const Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 53612724Snikos.nikoleris@arm.com // copy writebacks to write buffer 53712724Snikos.nikoleris@arm.com doWritebacks(writebacks, forward_time); 53812724Snikos.nikoleris@arm.com 53912724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print()); 54012724Snikos.nikoleris@arm.com delete pkt; 54112724Snikos.nikoleris@arm.com} 54212724Snikos.nikoleris@arm.com 54312724Snikos.nikoleris@arm.com 54412724Snikos.nikoleris@arm.comTick 54512724Snikos.nikoleris@arm.comBaseCache::recvAtomic(PacketPtr pkt) 54612724Snikos.nikoleris@arm.com{ 54712724Snikos.nikoleris@arm.com // should assert here that there are no outstanding MSHRs or 54812724Snikos.nikoleris@arm.com // writebacks... that would mean that someone used an atomic 54912724Snikos.nikoleris@arm.com // access in timing mode 55012724Snikos.nikoleris@arm.com 55113412Snikos.nikoleris@arm.com // We use lookupLatency here because it is used to specify the latency 55213412Snikos.nikoleris@arm.com // to access. 55313412Snikos.nikoleris@arm.com Cycles lat = lookupLatency; 55413412Snikos.nikoleris@arm.com 55512724Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 55612724Snikos.nikoleris@arm.com PacketList writebacks; 55712724Snikos.nikoleris@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 55812724Snikos.nikoleris@arm.com 55912724Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 56012724Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty 56112724Snikos.nikoleris@arm.com // block. If a dirty block is encountered a WriteClean 56212724Snikos.nikoleris@arm.com // will update any copies to the path to the memory 56312724Snikos.nikoleris@arm.com // until the point of reference. 56412724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 56512724Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 56612724Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 56712724Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 56812724Snikos.nikoleris@arm.com pkt->setSatisfied(); 56912724Snikos.nikoleris@arm.com } 57012724Snikos.nikoleris@arm.com 57112724Snikos.nikoleris@arm.com // handle writebacks resulting from the access here to ensure they 57212820Srmk35@cl.cam.ac.uk // logically precede anything happening below 57312724Snikos.nikoleris@arm.com doWritebacksAtomic(writebacks); 57412724Snikos.nikoleris@arm.com assert(writebacks.empty()); 57512724Snikos.nikoleris@arm.com 57612724Snikos.nikoleris@arm.com if (!satisfied) { 57712724Snikos.nikoleris@arm.com lat += handleAtomicReqMiss(pkt, blk, writebacks); 57812724Snikos.nikoleris@arm.com } 57912724Snikos.nikoleris@arm.com 58012724Snikos.nikoleris@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 58112724Snikos.nikoleris@arm.com // It's not clear how to do it properly, particularly for 58212724Snikos.nikoleris@arm.com // prefetchers that aggressively generate prefetch candidates and 58312724Snikos.nikoleris@arm.com // rely on bandwidth contention to throttle them; these will tend 58412724Snikos.nikoleris@arm.com // to pollute the cache in atomic mode since there is no bandwidth 58512724Snikos.nikoleris@arm.com // contention. If we ever do want to enable prefetching in atomic 58612724Snikos.nikoleris@arm.com // mode, though, this is the place to do it... see timingAccess() 58712724Snikos.nikoleris@arm.com // for an example (though we'd want to issue the prefetch(es) 58812724Snikos.nikoleris@arm.com // immediately rather than calling requestMemSideBus() as we do 58912724Snikos.nikoleris@arm.com // there). 59012724Snikos.nikoleris@arm.com 59112724Snikos.nikoleris@arm.com // do any writebacks resulting from the response handling 59212724Snikos.nikoleris@arm.com doWritebacksAtomic(writebacks); 59312724Snikos.nikoleris@arm.com 59412724Snikos.nikoleris@arm.com // if we used temp block, check to see if its valid and if so 59512724Snikos.nikoleris@arm.com // clear it out, but only do so after the call to recvAtomic is 59612724Snikos.nikoleris@arm.com // finished so that any downstream observers (such as a snoop 59712724Snikos.nikoleris@arm.com // filter), first see the fill, and only then see the eviction 59812724Snikos.nikoleris@arm.com if (blk == tempBlock && tempBlock->isValid()) { 59912724Snikos.nikoleris@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 60012724Snikos.nikoleris@arm.com // sequentuially, and we may already have a tempBlock 60112724Snikos.nikoleris@arm.com // writeback from the fetch that we have not yet sent 60212724Snikos.nikoleris@arm.com if (tempBlockWriteback) { 60312724Snikos.nikoleris@arm.com // if that is the case, write the prevoius one back, and 60412724Snikos.nikoleris@arm.com // do not schedule any new event 60512724Snikos.nikoleris@arm.com writebackTempBlockAtomic(); 60612724Snikos.nikoleris@arm.com } else { 60712724Snikos.nikoleris@arm.com // the writeback/clean eviction happens after the call to 60812724Snikos.nikoleris@arm.com // recvAtomic has finished (but before any successive 60912724Snikos.nikoleris@arm.com // calls), so that the response handling from the fill is 61012724Snikos.nikoleris@arm.com // allowed to happen first 61112724Snikos.nikoleris@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 61212724Snikos.nikoleris@arm.com } 61312724Snikos.nikoleris@arm.com 61412724Snikos.nikoleris@arm.com tempBlockWriteback = evictBlock(blk); 61512724Snikos.nikoleris@arm.com } 61612724Snikos.nikoleris@arm.com 61712724Snikos.nikoleris@arm.com if (pkt->needsResponse()) { 61812724Snikos.nikoleris@arm.com pkt->makeAtomicResponse(); 61912724Snikos.nikoleris@arm.com } 62012724Snikos.nikoleris@arm.com 62112724Snikos.nikoleris@arm.com return lat * clockPeriod(); 62212724Snikos.nikoleris@arm.com} 62312724Snikos.nikoleris@arm.com 62412724Snikos.nikoleris@arm.comvoid 62512724Snikos.nikoleris@arm.comBaseCache::functionalAccess(PacketPtr pkt, bool from_cpu_side) 62612724Snikos.nikoleris@arm.com{ 62712724Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 62812724Snikos.nikoleris@arm.com bool is_secure = pkt->isSecure(); 62912724Snikos.nikoleris@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 63012724Snikos.nikoleris@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 63112724Snikos.nikoleris@arm.com 63212724Snikos.nikoleris@arm.com pkt->pushLabel(name()); 63312724Snikos.nikoleris@arm.com 63412724Snikos.nikoleris@arm.com CacheBlkPrintWrapper cbpw(blk); 63512724Snikos.nikoleris@arm.com 63612724Snikos.nikoleris@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 63712724Snikos.nikoleris@arm.com // L1 doesn't have a more up-to-date modified copy that still 63812724Snikos.nikoleris@arm.com // needs to be found. As a result we always update the request if 63912724Snikos.nikoleris@arm.com // we have it, but only declare it satisfied if we are the owner. 64012724Snikos.nikoleris@arm.com 64112724Snikos.nikoleris@arm.com // see if we have data at all (owned or otherwise) 64212724Snikos.nikoleris@arm.com bool have_data = blk && blk->isValid() 64312823Srmk35@cl.cam.ac.uk && pkt->trySatisfyFunctional(&cbpw, blk_addr, is_secure, blkSize, 64412823Srmk35@cl.cam.ac.uk blk->data); 64512724Snikos.nikoleris@arm.com 64612724Snikos.nikoleris@arm.com // data we have is dirty if marked as such or if we have an 64712724Snikos.nikoleris@arm.com // in-service MSHR that is pending a modified line 64812724Snikos.nikoleris@arm.com bool have_dirty = 64912724Snikos.nikoleris@arm.com have_data && (blk->isDirty() || 65012724Snikos.nikoleris@arm.com (mshr && mshr->inService && mshr->isPendingModified())); 65112724Snikos.nikoleris@arm.com 65212724Snikos.nikoleris@arm.com bool done = have_dirty || 65312823Srmk35@cl.cam.ac.uk cpuSidePort.trySatisfyFunctional(pkt) || 65413862Sodanrc@yahoo.com.br mshrQueue.trySatisfyFunctional(pkt) || 65513862Sodanrc@yahoo.com.br writeBuffer.trySatisfyFunctional(pkt) || 65612823Srmk35@cl.cam.ac.uk memSidePort.trySatisfyFunctional(pkt); 65712724Snikos.nikoleris@arm.com 65812724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(), 65912724Snikos.nikoleris@arm.com (blk && blk->isValid()) ? "valid " : "", 66012724Snikos.nikoleris@arm.com have_data ? "data " : "", done ? "done " : ""); 66112724Snikos.nikoleris@arm.com 66212724Snikos.nikoleris@arm.com // We're leaving the cache, so pop cache->name() label 66312724Snikos.nikoleris@arm.com pkt->popLabel(); 66412724Snikos.nikoleris@arm.com 66512724Snikos.nikoleris@arm.com if (done) { 66612724Snikos.nikoleris@arm.com pkt->makeResponse(); 66712724Snikos.nikoleris@arm.com } else { 66812724Snikos.nikoleris@arm.com // if it came as a request from the CPU side then make sure it 66912724Snikos.nikoleris@arm.com // continues towards the memory side 67012724Snikos.nikoleris@arm.com if (from_cpu_side) { 67112724Snikos.nikoleris@arm.com memSidePort.sendFunctional(pkt); 67212724Snikos.nikoleris@arm.com } else if (cpuSidePort.isSnooping()) { 67312724Snikos.nikoleris@arm.com // if it came from the memory side, it must be a snoop request 67412724Snikos.nikoleris@arm.com // and we should only forward it if we are forwarding snoops 67512724Snikos.nikoleris@arm.com cpuSidePort.sendFunctionalSnoop(pkt); 67612724Snikos.nikoleris@arm.com } 67712724Snikos.nikoleris@arm.com } 67812724Snikos.nikoleris@arm.com} 67912724Snikos.nikoleris@arm.com 68012724Snikos.nikoleris@arm.com 68112724Snikos.nikoleris@arm.comvoid 68212724Snikos.nikoleris@arm.comBaseCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 68312724Snikos.nikoleris@arm.com{ 68412724Snikos.nikoleris@arm.com assert(pkt->isRequest()); 68512724Snikos.nikoleris@arm.com 68612724Snikos.nikoleris@arm.com uint64_t overwrite_val; 68712724Snikos.nikoleris@arm.com bool overwrite_mem; 68812724Snikos.nikoleris@arm.com uint64_t condition_val64; 68912724Snikos.nikoleris@arm.com uint32_t condition_val32; 69012724Snikos.nikoleris@arm.com 69112724Snikos.nikoleris@arm.com int offset = pkt->getOffset(blkSize); 69212724Snikos.nikoleris@arm.com uint8_t *blk_data = blk->data + offset; 69312724Snikos.nikoleris@arm.com 69412724Snikos.nikoleris@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 69512724Snikos.nikoleris@arm.com 69612724Snikos.nikoleris@arm.com overwrite_mem = true; 69712724Snikos.nikoleris@arm.com // keep a copy of our possible write value, and copy what is at the 69812724Snikos.nikoleris@arm.com // memory address into the packet 69912724Snikos.nikoleris@arm.com pkt->writeData((uint8_t *)&overwrite_val); 70012724Snikos.nikoleris@arm.com pkt->setData(blk_data); 70112724Snikos.nikoleris@arm.com 70212724Snikos.nikoleris@arm.com if (pkt->req->isCondSwap()) { 70312724Snikos.nikoleris@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 70412724Snikos.nikoleris@arm.com condition_val64 = pkt->req->getExtraData(); 70512724Snikos.nikoleris@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 70612724Snikos.nikoleris@arm.com sizeof(uint64_t)); 70712724Snikos.nikoleris@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 70812724Snikos.nikoleris@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 70912724Snikos.nikoleris@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 71012724Snikos.nikoleris@arm.com sizeof(uint32_t)); 71112724Snikos.nikoleris@arm.com } else 71212724Snikos.nikoleris@arm.com panic("Invalid size for conditional read/write\n"); 71312724Snikos.nikoleris@arm.com } 71412724Snikos.nikoleris@arm.com 71512724Snikos.nikoleris@arm.com if (overwrite_mem) { 71612724Snikos.nikoleris@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 71712724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 71812724Snikos.nikoleris@arm.com } 71912724Snikos.nikoleris@arm.com} 72012724Snikos.nikoleris@arm.com 72112724Snikos.nikoleris@arm.comQueueEntry* 72212724Snikos.nikoleris@arm.comBaseCache::getNextQueueEntry() 72312724Snikos.nikoleris@arm.com{ 72412724Snikos.nikoleris@arm.com // Check both MSHR queue and write buffer for potential requests, 72512724Snikos.nikoleris@arm.com // note that null does not mean there is no request, it could 72612724Snikos.nikoleris@arm.com // simply be that it is not ready 72712724Snikos.nikoleris@arm.com MSHR *miss_mshr = mshrQueue.getNext(); 72812724Snikos.nikoleris@arm.com WriteQueueEntry *wq_entry = writeBuffer.getNext(); 72912724Snikos.nikoleris@arm.com 73012724Snikos.nikoleris@arm.com // If we got a write buffer request ready, first priority is a 73112724Snikos.nikoleris@arm.com // full write buffer, otherwise we favour the miss requests 73212724Snikos.nikoleris@arm.com if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) { 73312724Snikos.nikoleris@arm.com // need to search MSHR queue for conflicting earlier miss. 73413861Sodanrc@yahoo.com.br MSHR *conflict_mshr = mshrQueue.findPending(wq_entry); 73512724Snikos.nikoleris@arm.com 73612724Snikos.nikoleris@arm.com if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 73712724Snikos.nikoleris@arm.com // Service misses in order until conflict is cleared. 73812724Snikos.nikoleris@arm.com return conflict_mshr; 73912724Snikos.nikoleris@arm.com 74012724Snikos.nikoleris@arm.com // @todo Note that we ignore the ready time of the conflict here 74112724Snikos.nikoleris@arm.com } 74212724Snikos.nikoleris@arm.com 74312724Snikos.nikoleris@arm.com // No conflicts; issue write 74412724Snikos.nikoleris@arm.com return wq_entry; 74512724Snikos.nikoleris@arm.com } else if (miss_mshr) { 74612724Snikos.nikoleris@arm.com // need to check for conflicting earlier writeback 74713861Sodanrc@yahoo.com.br WriteQueueEntry *conflict_mshr = writeBuffer.findPending(miss_mshr); 74812724Snikos.nikoleris@arm.com if (conflict_mshr) { 74912724Snikos.nikoleris@arm.com // not sure why we don't check order here... it was in the 75012724Snikos.nikoleris@arm.com // original code but commented out. 75112724Snikos.nikoleris@arm.com 75212724Snikos.nikoleris@arm.com // The only way this happens is if we are 75312724Snikos.nikoleris@arm.com // doing a write and we didn't have permissions 75412724Snikos.nikoleris@arm.com // then subsequently saw a writeback (owned got evicted) 75512724Snikos.nikoleris@arm.com // We need to make sure to perform the writeback first 75612724Snikos.nikoleris@arm.com // To preserve the dirty data, then we can issue the write 75712724Snikos.nikoleris@arm.com 75812724Snikos.nikoleris@arm.com // should we return wq_entry here instead? I.e. do we 75912724Snikos.nikoleris@arm.com // have to flush writes in order? I don't think so... not 76012724Snikos.nikoleris@arm.com // for Alpha anyway. Maybe for x86? 76112724Snikos.nikoleris@arm.com return conflict_mshr; 76212724Snikos.nikoleris@arm.com 76312724Snikos.nikoleris@arm.com // @todo Note that we ignore the ready time of the conflict here 76412724Snikos.nikoleris@arm.com } 76512724Snikos.nikoleris@arm.com 76612724Snikos.nikoleris@arm.com // No conflicts; issue read 76712724Snikos.nikoleris@arm.com return miss_mshr; 76812724Snikos.nikoleris@arm.com } 76912724Snikos.nikoleris@arm.com 77012724Snikos.nikoleris@arm.com // fall through... no pending requests. Try a prefetch. 77112724Snikos.nikoleris@arm.com assert(!miss_mshr && !wq_entry); 77212724Snikos.nikoleris@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 77312724Snikos.nikoleris@arm.com // If we have a miss queue slot, we can try a prefetch 77412724Snikos.nikoleris@arm.com PacketPtr pkt = prefetcher->getPacket(); 77512724Snikos.nikoleris@arm.com if (pkt) { 77612724Snikos.nikoleris@arm.com Addr pf_addr = pkt->getBlockAddr(blkSize); 77712724Snikos.nikoleris@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 77812724Snikos.nikoleris@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 77912724Snikos.nikoleris@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 78012724Snikos.nikoleris@arm.com // Update statistic on number of prefetches issued 78112724Snikos.nikoleris@arm.com // (hwpf_mshr_misses) 78212724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 78312724Snikos.nikoleris@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 78412724Snikos.nikoleris@arm.com 78512724Snikos.nikoleris@arm.com // allocate an MSHR and return it, note 78612724Snikos.nikoleris@arm.com // that we send the packet straight away, so do not 78712724Snikos.nikoleris@arm.com // schedule the send 78812724Snikos.nikoleris@arm.com return allocateMissBuffer(pkt, curTick(), false); 78912724Snikos.nikoleris@arm.com } else { 79012724Snikos.nikoleris@arm.com // free the request and packet 79112724Snikos.nikoleris@arm.com delete pkt; 79212724Snikos.nikoleris@arm.com } 79312724Snikos.nikoleris@arm.com } 79412724Snikos.nikoleris@arm.com } 79512724Snikos.nikoleris@arm.com 79612724Snikos.nikoleris@arm.com return nullptr; 79712724Snikos.nikoleris@arm.com} 79812724Snikos.nikoleris@arm.com 79912724Snikos.nikoleris@arm.comvoid 80012724Snikos.nikoleris@arm.comBaseCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool, bool) 80112724Snikos.nikoleris@arm.com{ 80212724Snikos.nikoleris@arm.com assert(pkt->isRequest()); 80312724Snikos.nikoleris@arm.com 80412724Snikos.nikoleris@arm.com assert(blk && blk->isValid()); 80512724Snikos.nikoleris@arm.com // Occasionally this is not true... if we are a lower-level cache 80612724Snikos.nikoleris@arm.com // satisfying a string of Read and ReadEx requests from 80712724Snikos.nikoleris@arm.com // upper-level caches, a Read will mark the block as shared but we 80812724Snikos.nikoleris@arm.com // can satisfy a following ReadEx anyway since we can rely on the 80912724Snikos.nikoleris@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 81012724Snikos.nikoleris@arm.com // invalidate their blocks after receiving them. 81112724Snikos.nikoleris@arm.com // assert(!pkt->needsWritable() || blk->isWritable()); 81212724Snikos.nikoleris@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 81312724Snikos.nikoleris@arm.com 81412724Snikos.nikoleris@arm.com // Check RMW operations first since both isRead() and 81512724Snikos.nikoleris@arm.com // isWrite() will be true for them 81612724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::SwapReq) { 81712766Sqtt2@cornell.edu if (pkt->isAtomicOp()) { 81812766Sqtt2@cornell.edu // extract data from cache and save it into the data field in 81912766Sqtt2@cornell.edu // the packet as a return value from this atomic op 82012766Sqtt2@cornell.edu int offset = tags->extractBlkOffset(pkt->getAddr()); 82112766Sqtt2@cornell.edu uint8_t *blk_data = blk->data + offset; 82213377Sodanrc@yahoo.com.br pkt->setData(blk_data); 82312766Sqtt2@cornell.edu 82412766Sqtt2@cornell.edu // execute AMO operation 82512766Sqtt2@cornell.edu (*(pkt->getAtomicOp()))(blk_data); 82612766Sqtt2@cornell.edu 82712766Sqtt2@cornell.edu // set block status to dirty 82812766Sqtt2@cornell.edu blk->status |= BlkDirty; 82912766Sqtt2@cornell.edu } else { 83012766Sqtt2@cornell.edu cmpAndSwap(blk, pkt); 83112766Sqtt2@cornell.edu } 83212724Snikos.nikoleris@arm.com } else if (pkt->isWrite()) { 83312724Snikos.nikoleris@arm.com // we have the block in a writable state and can go ahead, 83412724Snikos.nikoleris@arm.com // note that the line may be also be considered writable in 83512724Snikos.nikoleris@arm.com // downstream caches along the path to memory, but always 83612724Snikos.nikoleris@arm.com // Exclusive, and never Modified 83712724Snikos.nikoleris@arm.com assert(blk->isWritable()); 83812724Snikos.nikoleris@arm.com // Write or WriteLine at the first cache with block in writable state 83912724Snikos.nikoleris@arm.com if (blk->checkWrite(pkt)) { 84012724Snikos.nikoleris@arm.com pkt->writeDataToBlock(blk->data, blkSize); 84112724Snikos.nikoleris@arm.com } 84212724Snikos.nikoleris@arm.com // Always mark the line as dirty (and thus transition to the 84312724Snikos.nikoleris@arm.com // Modified state) even if we are a failed StoreCond so we 84412724Snikos.nikoleris@arm.com // supply data to any snoops that have appended themselves to 84512724Snikos.nikoleris@arm.com // this cache before knowing the store will fail. 84612724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 84712724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print()); 84812724Snikos.nikoleris@arm.com } else if (pkt->isRead()) { 84912724Snikos.nikoleris@arm.com if (pkt->isLLSC()) { 85012724Snikos.nikoleris@arm.com blk->trackLoadLocked(pkt); 85112724Snikos.nikoleris@arm.com } 85212724Snikos.nikoleris@arm.com 85312724Snikos.nikoleris@arm.com // all read responses have a data payload 85412724Snikos.nikoleris@arm.com assert(pkt->hasRespData()); 85512724Snikos.nikoleris@arm.com pkt->setDataFromBlock(blk->data, blkSize); 85612724Snikos.nikoleris@arm.com } else if (pkt->isUpgrade()) { 85712724Snikos.nikoleris@arm.com // sanity check 85812724Snikos.nikoleris@arm.com assert(!pkt->hasSharers()); 85912724Snikos.nikoleris@arm.com 86012724Snikos.nikoleris@arm.com if (blk->isDirty()) { 86112724Snikos.nikoleris@arm.com // we were in the Owned state, and a cache above us that 86212724Snikos.nikoleris@arm.com // has the line in Shared state needs to be made aware 86312724Snikos.nikoleris@arm.com // that the data it already has is in fact dirty 86412724Snikos.nikoleris@arm.com pkt->setCacheResponding(); 86512724Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 86612724Snikos.nikoleris@arm.com } 86712794Snikos.nikoleris@arm.com } else if (pkt->isClean()) { 86812794Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 86912724Snikos.nikoleris@arm.com } else { 87012724Snikos.nikoleris@arm.com assert(pkt->isInvalidate()); 87112724Snikos.nikoleris@arm.com invalidateBlock(blk); 87212724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__, 87312724Snikos.nikoleris@arm.com pkt->print()); 87412724Snikos.nikoleris@arm.com } 87512724Snikos.nikoleris@arm.com} 87612724Snikos.nikoleris@arm.com 87712724Snikos.nikoleris@arm.com///////////////////////////////////////////////////// 87812724Snikos.nikoleris@arm.com// 87912724Snikos.nikoleris@arm.com// Access path: requests coming in from the CPU side 88012724Snikos.nikoleris@arm.com// 88112724Snikos.nikoleris@arm.com///////////////////////////////////////////////////// 88213418Sodanrc@yahoo.com.brCycles 88313749Sodanrc@yahoo.com.brBaseCache::calculateTagOnlyLatency(const uint32_t delay, 88413749Sodanrc@yahoo.com.br const Cycles lookup_lat) const 88513749Sodanrc@yahoo.com.br{ 88613749Sodanrc@yahoo.com.br // A tag-only access has to wait for the packet to arrive in order to 88713749Sodanrc@yahoo.com.br // perform the tag lookup. 88813749Sodanrc@yahoo.com.br return ticksToCycles(delay) + lookup_lat; 88913749Sodanrc@yahoo.com.br} 89013749Sodanrc@yahoo.com.br 89113749Sodanrc@yahoo.com.brCycles 89213746Sodanrc@yahoo.com.brBaseCache::calculateAccessLatency(const CacheBlk* blk, const uint32_t delay, 89313418Sodanrc@yahoo.com.br const Cycles lookup_lat) const 89413418Sodanrc@yahoo.com.br{ 89513746Sodanrc@yahoo.com.br Cycles lat(0); 89613418Sodanrc@yahoo.com.br 89713418Sodanrc@yahoo.com.br if (blk != nullptr) { 89813746Sodanrc@yahoo.com.br // As soon as the access arrives, for sequential accesses first access 89913746Sodanrc@yahoo.com.br // tags, then the data entry. In the case of parallel accesses the 90013746Sodanrc@yahoo.com.br // latency is dictated by the slowest of tag and data latencies. 90113418Sodanrc@yahoo.com.br if (sequentialAccess) { 90213746Sodanrc@yahoo.com.br lat = ticksToCycles(delay) + lookup_lat + dataLatency; 90313418Sodanrc@yahoo.com.br } else { 90413746Sodanrc@yahoo.com.br lat = ticksToCycles(delay) + std::max(lookup_lat, dataLatency); 90513418Sodanrc@yahoo.com.br } 90613418Sodanrc@yahoo.com.br 90713418Sodanrc@yahoo.com.br // Check if the block to be accessed is available. If not, apply the 90813477Sodanrc@yahoo.com.br // access latency on top of when the block is ready to be accessed. 90913746Sodanrc@yahoo.com.br const Tick tick = curTick() + delay; 91013477Sodanrc@yahoo.com.br const Tick when_ready = blk->getWhenReady(); 91113746Sodanrc@yahoo.com.br if (when_ready > tick && 91213746Sodanrc@yahoo.com.br ticksToCycles(when_ready - tick) > lat) { 91313746Sodanrc@yahoo.com.br lat += ticksToCycles(when_ready - tick); 91413418Sodanrc@yahoo.com.br } 91513746Sodanrc@yahoo.com.br } else { 91613749Sodanrc@yahoo.com.br // In case of a miss, we neglect the data access in a parallel 91713749Sodanrc@yahoo.com.br // configuration (i.e., the data access will be stopped as soon as 91813749Sodanrc@yahoo.com.br // we find out it is a miss), and use the tag-only latency. 91913749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(delay, lookup_lat); 92013418Sodanrc@yahoo.com.br } 92113418Sodanrc@yahoo.com.br 92213418Sodanrc@yahoo.com.br return lat; 92313418Sodanrc@yahoo.com.br} 92412724Snikos.nikoleris@arm.com 92512724Snikos.nikoleris@arm.combool 92612724Snikos.nikoleris@arm.comBaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 92712724Snikos.nikoleris@arm.com PacketList &writebacks) 92812724Snikos.nikoleris@arm.com{ 92912724Snikos.nikoleris@arm.com // sanity check 93012724Snikos.nikoleris@arm.com assert(pkt->isRequest()); 93112724Snikos.nikoleris@arm.com 93212724Snikos.nikoleris@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 93312724Snikos.nikoleris@arm.com "Should never see a write in a read-only cache %s\n", 93412724Snikos.nikoleris@arm.com name()); 93512724Snikos.nikoleris@arm.com 93613418Sodanrc@yahoo.com.br // Access block in the tags 93713418Sodanrc@yahoo.com.br Cycles tag_latency(0); 93813418Sodanrc@yahoo.com.br blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), tag_latency); 93913418Sodanrc@yahoo.com.br 94012724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(), 94112724Snikos.nikoleris@arm.com blk ? "hit " + blk->print() : "miss"); 94212724Snikos.nikoleris@arm.com 94312724Snikos.nikoleris@arm.com if (pkt->req->isCacheMaintenance()) { 94412724Snikos.nikoleris@arm.com // A cache maintenance operation is always forwarded to the 94512724Snikos.nikoleris@arm.com // memory below even if the block is found in dirty state. 94612724Snikos.nikoleris@arm.com 94712724Snikos.nikoleris@arm.com // We defer any changes to the state of the block until we 94812724Snikos.nikoleris@arm.com // create and mark as in service the mshr for the downstream 94912724Snikos.nikoleris@arm.com // packet. 95013749Sodanrc@yahoo.com.br 95113749Sodanrc@yahoo.com.br // Calculate access latency on top of when the packet arrives. This 95213749Sodanrc@yahoo.com.br // takes into account the bus delay. 95313749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency); 95413749Sodanrc@yahoo.com.br 95512724Snikos.nikoleris@arm.com return false; 95612724Snikos.nikoleris@arm.com } 95712724Snikos.nikoleris@arm.com 95812724Snikos.nikoleris@arm.com if (pkt->isEviction()) { 95912724Snikos.nikoleris@arm.com // We check for presence of block in above caches before issuing 96012724Snikos.nikoleris@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 96112724Snikos.nikoleris@arm.com // possible cases can be of a CleanEvict packet coming from above 96212724Snikos.nikoleris@arm.com // encountering a Writeback generated in this cache peer cache and 96312724Snikos.nikoleris@arm.com // waiting in the write buffer. Cases of upper level peer caches 96412724Snikos.nikoleris@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 96512724Snikos.nikoleris@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 96612724Snikos.nikoleris@arm.com // by crossbar. 96712724Snikos.nikoleris@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 96812724Snikos.nikoleris@arm.com pkt->isSecure()); 96912724Snikos.nikoleris@arm.com if (wb_entry) { 97012724Snikos.nikoleris@arm.com assert(wb_entry->getNumTargets() == 1); 97112724Snikos.nikoleris@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 97212724Snikos.nikoleris@arm.com assert(wbPkt->isWriteback()); 97312724Snikos.nikoleris@arm.com 97412724Snikos.nikoleris@arm.com if (pkt->isCleanEviction()) { 97512724Snikos.nikoleris@arm.com // The CleanEvict and WritebackClean snoops into other 97612724Snikos.nikoleris@arm.com // peer caches of the same level while traversing the 97712724Snikos.nikoleris@arm.com // crossbar. If a copy of the block is found, the 97812724Snikos.nikoleris@arm.com // packet is deleted in the crossbar. Hence, none of 97912724Snikos.nikoleris@arm.com // the other upper level caches connected to this 98012724Snikos.nikoleris@arm.com // cache have the block, so we can clear the 98112724Snikos.nikoleris@arm.com // BLOCK_CACHED flag in the Writeback if set and 98212724Snikos.nikoleris@arm.com // discard the CleanEvict by returning true. 98312724Snikos.nikoleris@arm.com wbPkt->clearBlockCached(); 98413749Sodanrc@yahoo.com.br 98513749Sodanrc@yahoo.com.br // A clean evict does not need to access the data array 98613749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency); 98713749Sodanrc@yahoo.com.br 98812724Snikos.nikoleris@arm.com return true; 98912724Snikos.nikoleris@arm.com } else { 99012724Snikos.nikoleris@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 99112724Snikos.nikoleris@arm.com // Dirty writeback from above trumps our clean 99212724Snikos.nikoleris@arm.com // writeback... discard here 99312724Snikos.nikoleris@arm.com // Note: markInService will remove entry from writeback buffer. 99412724Snikos.nikoleris@arm.com markInService(wb_entry); 99512724Snikos.nikoleris@arm.com delete wbPkt; 99612724Snikos.nikoleris@arm.com } 99712724Snikos.nikoleris@arm.com } 99812724Snikos.nikoleris@arm.com } 99912724Snikos.nikoleris@arm.com 100012724Snikos.nikoleris@arm.com // Writeback handling is special case. We can write the block into 100112724Snikos.nikoleris@arm.com // the cache without having a writeable copy (or any copy at all). 100212724Snikos.nikoleris@arm.com if (pkt->isWriteback()) { 100312724Snikos.nikoleris@arm.com assert(blkSize == pkt->getSize()); 100412724Snikos.nikoleris@arm.com 100512724Snikos.nikoleris@arm.com // we could get a clean writeback while we are having 100612724Snikos.nikoleris@arm.com // outstanding accesses to a block, do the simple thing for 100712724Snikos.nikoleris@arm.com // now and drop the clean writeback so that we do not upset 100812724Snikos.nikoleris@arm.com // any ordering/decisions about ownership already taken 100912724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::WritebackClean && 101012724Snikos.nikoleris@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 101112724Snikos.nikoleris@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 101212724Snikos.nikoleris@arm.com "dropping\n", pkt->getAddr()); 101313749Sodanrc@yahoo.com.br 101413749Sodanrc@yahoo.com.br // A writeback searches for the block, then writes the data. 101513749Sodanrc@yahoo.com.br // As the writeback is being dropped, the data is not touched, 101613749Sodanrc@yahoo.com.br // and we just had to wait for the time to find a match in the 101713749Sodanrc@yahoo.com.br // MSHR. As of now assume a mshr queue search takes as long as 101813749Sodanrc@yahoo.com.br // a tag lookup for simplicity. 101913749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency); 102013749Sodanrc@yahoo.com.br 102112724Snikos.nikoleris@arm.com return true; 102212724Snikos.nikoleris@arm.com } 102312724Snikos.nikoleris@arm.com 102412724Snikos.nikoleris@arm.com if (!blk) { 102512724Snikos.nikoleris@arm.com // need to do a replacement 102612754Sodanrc@yahoo.com.br blk = allocateBlock(pkt, writebacks); 102712724Snikos.nikoleris@arm.com if (!blk) { 102812724Snikos.nikoleris@arm.com // no replaceable block available: give up, fwd to next level. 102912724Snikos.nikoleris@arm.com incMissCount(pkt); 103013749Sodanrc@yahoo.com.br 103113749Sodanrc@yahoo.com.br // A writeback searches for the block, then writes the data. 103213749Sodanrc@yahoo.com.br // As the block could not be found, it was a tag-only access. 103313749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency); 103413749Sodanrc@yahoo.com.br 103512724Snikos.nikoleris@arm.com return false; 103612724Snikos.nikoleris@arm.com } 103712724Snikos.nikoleris@arm.com 103813445Sodanrc@yahoo.com.br blk->status |= BlkReadable; 103913945Sodanrc@yahoo.com.br } else { 104013945Sodanrc@yahoo.com.br if (compressor) { 104113945Sodanrc@yahoo.com.br // This is an overwrite to an existing block, therefore we need 104213945Sodanrc@yahoo.com.br // to check for data expansion (i.e., block was compressed with 104313945Sodanrc@yahoo.com.br // a smaller size, and now it doesn't fit the entry anymore). 104413945Sodanrc@yahoo.com.br // If that is the case we might need to evict blocks. 104513945Sodanrc@yahoo.com.br // @todo Update compression data 104613945Sodanrc@yahoo.com.br } 104712724Snikos.nikoleris@arm.com } 104813945Sodanrc@yahoo.com.br 104912724Snikos.nikoleris@arm.com // only mark the block dirty if we got a writeback command, 105012724Snikos.nikoleris@arm.com // and leave it as is for a clean writeback 105112724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::WritebackDirty) { 105212724Snikos.nikoleris@arm.com // TODO: the coherent cache can assert(!blk->isDirty()); 105312724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 105412724Snikos.nikoleris@arm.com } 105512724Snikos.nikoleris@arm.com // if the packet does not have sharers, it is passing 105612724Snikos.nikoleris@arm.com // writable, and we got the writeback in Modified or Exclusive 105712724Snikos.nikoleris@arm.com // state, if not we are in the Owned or Shared state 105812724Snikos.nikoleris@arm.com if (!pkt->hasSharers()) { 105912724Snikos.nikoleris@arm.com blk->status |= BlkWritable; 106012724Snikos.nikoleris@arm.com } 106112724Snikos.nikoleris@arm.com // nothing else to do; writeback doesn't expect response 106212724Snikos.nikoleris@arm.com assert(!pkt->needsResponse()); 106312724Snikos.nikoleris@arm.com pkt->writeDataToBlock(blk->data, blkSize); 106412724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 106512724Snikos.nikoleris@arm.com incHitCount(pkt); 106613748Sodanrc@yahoo.com.br 106713765Sodanrc@yahoo.com.br // A writeback searches for the block, then writes the data 106813765Sodanrc@yahoo.com.br lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency); 106913765Sodanrc@yahoo.com.br 107013748Sodanrc@yahoo.com.br // When the packet metadata arrives, the tag lookup will be done while 107113748Sodanrc@yahoo.com.br // the payload is arriving. Then the block will be ready to access as 107213748Sodanrc@yahoo.com.br // soon as the fill is done 107313477Sodanrc@yahoo.com.br blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay + 107413748Sodanrc@yahoo.com.br std::max(cyclesToTicks(tag_latency), (uint64_t)pkt->payloadDelay)); 107513749Sodanrc@yahoo.com.br 107612724Snikos.nikoleris@arm.com return true; 107712724Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 107813749Sodanrc@yahoo.com.br // A CleanEvict does not need to access the data array 107913749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency); 108013749Sodanrc@yahoo.com.br 108112724Snikos.nikoleris@arm.com if (blk) { 108212724Snikos.nikoleris@arm.com // Found the block in the tags, need to stop CleanEvict from 108312724Snikos.nikoleris@arm.com // propagating further down the hierarchy. Returning true will 108412724Snikos.nikoleris@arm.com // treat the CleanEvict like a satisfied write request and delete 108512724Snikos.nikoleris@arm.com // it. 108612724Snikos.nikoleris@arm.com return true; 108712724Snikos.nikoleris@arm.com } 108812724Snikos.nikoleris@arm.com // We didn't find the block here, propagate the CleanEvict further 108912724Snikos.nikoleris@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 109012724Snikos.nikoleris@arm.com // like a Writeback which could not find a replaceable block so has to 109112724Snikos.nikoleris@arm.com // go to next level. 109212724Snikos.nikoleris@arm.com return false; 109312724Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 109412724Snikos.nikoleris@arm.com // WriteClean handling is a special case. We can allocate a 109512724Snikos.nikoleris@arm.com // block directly if it doesn't exist and we can update the 109612724Snikos.nikoleris@arm.com // block immediately. The WriteClean transfers the ownership 109712724Snikos.nikoleris@arm.com // of the block as well. 109812724Snikos.nikoleris@arm.com assert(blkSize == pkt->getSize()); 109912724Snikos.nikoleris@arm.com 110012724Snikos.nikoleris@arm.com if (!blk) { 110112724Snikos.nikoleris@arm.com if (pkt->writeThrough()) { 110213749Sodanrc@yahoo.com.br // A writeback searches for the block, then writes the data. 110313749Sodanrc@yahoo.com.br // As the block could not be found, it was a tag-only access. 110413749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency); 110513749Sodanrc@yahoo.com.br 110612724Snikos.nikoleris@arm.com // if this is a write through packet, we don't try to 110712724Snikos.nikoleris@arm.com // allocate if the block is not present 110812724Snikos.nikoleris@arm.com return false; 110912724Snikos.nikoleris@arm.com } else { 111012724Snikos.nikoleris@arm.com // a writeback that misses needs to allocate a new block 111112754Sodanrc@yahoo.com.br blk = allocateBlock(pkt, writebacks); 111212724Snikos.nikoleris@arm.com if (!blk) { 111312724Snikos.nikoleris@arm.com // no replaceable block available: give up, fwd to 111412724Snikos.nikoleris@arm.com // next level. 111512724Snikos.nikoleris@arm.com incMissCount(pkt); 111613749Sodanrc@yahoo.com.br 111713749Sodanrc@yahoo.com.br // A writeback searches for the block, then writes the 111813749Sodanrc@yahoo.com.br // data. As the block could not be found, it was a tag-only 111913749Sodanrc@yahoo.com.br // access. 112013749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(pkt->headerDelay, 112113749Sodanrc@yahoo.com.br tag_latency); 112213749Sodanrc@yahoo.com.br 112312724Snikos.nikoleris@arm.com return false; 112412724Snikos.nikoleris@arm.com } 112512724Snikos.nikoleris@arm.com 112613445Sodanrc@yahoo.com.br blk->status |= BlkReadable; 112712724Snikos.nikoleris@arm.com } 112813945Sodanrc@yahoo.com.br } else { 112913945Sodanrc@yahoo.com.br if (compressor) { 113013945Sodanrc@yahoo.com.br // @todo Update compression data 113113945Sodanrc@yahoo.com.br } 113212724Snikos.nikoleris@arm.com } 113312724Snikos.nikoleris@arm.com 113412724Snikos.nikoleris@arm.com // at this point either this is a writeback or a write-through 113512724Snikos.nikoleris@arm.com // write clean operation and the block is already in this 113612724Snikos.nikoleris@arm.com // cache, we need to update the data and the block flags 113712724Snikos.nikoleris@arm.com assert(blk); 113812724Snikos.nikoleris@arm.com // TODO: the coherent cache can assert(!blk->isDirty()); 113912724Snikos.nikoleris@arm.com if (!pkt->writeThrough()) { 114012724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 114112724Snikos.nikoleris@arm.com } 114212724Snikos.nikoleris@arm.com // nothing else to do; writeback doesn't expect response 114312724Snikos.nikoleris@arm.com assert(!pkt->needsResponse()); 114412724Snikos.nikoleris@arm.com pkt->writeDataToBlock(blk->data, blkSize); 114512724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 114612724Snikos.nikoleris@arm.com 114712724Snikos.nikoleris@arm.com incHitCount(pkt); 114813748Sodanrc@yahoo.com.br 114913765Sodanrc@yahoo.com.br // A writeback searches for the block, then writes the data 115013765Sodanrc@yahoo.com.br lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency); 115113765Sodanrc@yahoo.com.br 115213748Sodanrc@yahoo.com.br // When the packet metadata arrives, the tag lookup will be done while 115313748Sodanrc@yahoo.com.br // the payload is arriving. Then the block will be ready to access as 115413748Sodanrc@yahoo.com.br // soon as the fill is done 115513477Sodanrc@yahoo.com.br blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay + 115613748Sodanrc@yahoo.com.br std::max(cyclesToTicks(tag_latency), (uint64_t)pkt->payloadDelay)); 115713748Sodanrc@yahoo.com.br 115812724Snikos.nikoleris@arm.com // if this a write-through packet it will be sent to cache 115912724Snikos.nikoleris@arm.com // below 116012724Snikos.nikoleris@arm.com return !pkt->writeThrough(); 116112724Snikos.nikoleris@arm.com } else if (blk && (pkt->needsWritable() ? blk->isWritable() : 116212724Snikos.nikoleris@arm.com blk->isReadable())) { 116312724Snikos.nikoleris@arm.com // OK to satisfy access 116412724Snikos.nikoleris@arm.com incHitCount(pkt); 116512724Snikos.nikoleris@arm.com 116613749Sodanrc@yahoo.com.br // Calculate access latency based on the need to access the data array 116713749Sodanrc@yahoo.com.br if (pkt->isRead() || pkt->isWrite()) { 116813749Sodanrc@yahoo.com.br lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency); 116913945Sodanrc@yahoo.com.br 117013945Sodanrc@yahoo.com.br // When a block is compressed, it must first be decompressed 117113945Sodanrc@yahoo.com.br // before being read. This adds to the access latency. 117213945Sodanrc@yahoo.com.br if (compressor && pkt->isRead()) { 117313945Sodanrc@yahoo.com.br lat += compressor->getDecompressionLatency(blk); 117413945Sodanrc@yahoo.com.br } 117513749Sodanrc@yahoo.com.br } else { 117613749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency); 117713749Sodanrc@yahoo.com.br } 117813749Sodanrc@yahoo.com.br 117913765Sodanrc@yahoo.com.br satisfyRequest(pkt, blk); 118013765Sodanrc@yahoo.com.br maintainClusivity(pkt->fromCache(), blk); 118113765Sodanrc@yahoo.com.br 118212724Snikos.nikoleris@arm.com return true; 118312724Snikos.nikoleris@arm.com } 118412724Snikos.nikoleris@arm.com 118512724Snikos.nikoleris@arm.com // Can't satisfy access normally... either no block (blk == nullptr) 118612724Snikos.nikoleris@arm.com // or have block but need writable 118712724Snikos.nikoleris@arm.com 118812724Snikos.nikoleris@arm.com incMissCount(pkt); 118912724Snikos.nikoleris@arm.com 119013749Sodanrc@yahoo.com.br lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency); 119113749Sodanrc@yahoo.com.br 119212724Snikos.nikoleris@arm.com if (!blk && pkt->isLLSC() && pkt->isWrite()) { 119312724Snikos.nikoleris@arm.com // complete miss on store conditional... just give up now 119412724Snikos.nikoleris@arm.com pkt->req->setExtraData(0); 119512724Snikos.nikoleris@arm.com return true; 119612724Snikos.nikoleris@arm.com } 119712724Snikos.nikoleris@arm.com 119812724Snikos.nikoleris@arm.com return false; 119912724Snikos.nikoleris@arm.com} 120012724Snikos.nikoleris@arm.com 120112724Snikos.nikoleris@arm.comvoid 120212724Snikos.nikoleris@arm.comBaseCache::maintainClusivity(bool from_cache, CacheBlk *blk) 120312724Snikos.nikoleris@arm.com{ 120412724Snikos.nikoleris@arm.com if (from_cache && blk && blk->isValid() && !blk->isDirty() && 120512724Snikos.nikoleris@arm.com clusivity == Enums::mostly_excl) { 120612724Snikos.nikoleris@arm.com // if we have responded to a cache, and our block is still 120712724Snikos.nikoleris@arm.com // valid, but not dirty, and this cache is mostly exclusive 120812724Snikos.nikoleris@arm.com // with respect to the cache above, drop the block 120912724Snikos.nikoleris@arm.com invalidateBlock(blk); 121012724Snikos.nikoleris@arm.com } 121112724Snikos.nikoleris@arm.com} 121212724Snikos.nikoleris@arm.com 121312724Snikos.nikoleris@arm.comCacheBlk* 121412724Snikos.nikoleris@arm.comBaseCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 121512724Snikos.nikoleris@arm.com bool allocate) 121612724Snikos.nikoleris@arm.com{ 121713350Snikos.nikoleris@arm.com assert(pkt->isResponse()); 121812724Snikos.nikoleris@arm.com Addr addr = pkt->getAddr(); 121912724Snikos.nikoleris@arm.com bool is_secure = pkt->isSecure(); 122012724Snikos.nikoleris@arm.com#if TRACING_ON 122112724Snikos.nikoleris@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 122212724Snikos.nikoleris@arm.com#endif 122312724Snikos.nikoleris@arm.com 122412724Snikos.nikoleris@arm.com // When handling a fill, we should have no writes to this line. 122512724Snikos.nikoleris@arm.com assert(addr == pkt->getBlockAddr(blkSize)); 122612724Snikos.nikoleris@arm.com assert(!writeBuffer.findMatch(addr, is_secure)); 122712724Snikos.nikoleris@arm.com 122812724Snikos.nikoleris@arm.com if (!blk) { 122912724Snikos.nikoleris@arm.com // better have read new data... 123013350Snikos.nikoleris@arm.com assert(pkt->hasData() || pkt->cmd == MemCmd::InvalidateResp); 123112724Snikos.nikoleris@arm.com 123212724Snikos.nikoleris@arm.com // need to do a replacement if allocating, otherwise we stick 123312724Snikos.nikoleris@arm.com // with the temporary storage 123412754Sodanrc@yahoo.com.br blk = allocate ? allocateBlock(pkt, writebacks) : nullptr; 123512724Snikos.nikoleris@arm.com 123612724Snikos.nikoleris@arm.com if (!blk) { 123712724Snikos.nikoleris@arm.com // No replaceable block or a mostly exclusive 123812724Snikos.nikoleris@arm.com // cache... just use temporary storage to complete the 123912724Snikos.nikoleris@arm.com // current request and then get rid of it 124012724Snikos.nikoleris@arm.com blk = tempBlock; 124112730Sodanrc@yahoo.com.br tempBlock->insert(addr, is_secure); 124212724Snikos.nikoleris@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 124312724Snikos.nikoleris@arm.com is_secure ? "s" : "ns"); 124412724Snikos.nikoleris@arm.com } 124512724Snikos.nikoleris@arm.com } else { 124612724Snikos.nikoleris@arm.com // existing block... probably an upgrade 124712724Snikos.nikoleris@arm.com // don't clear block status... if block is already dirty we 124812724Snikos.nikoleris@arm.com // don't want to lose that 124912724Snikos.nikoleris@arm.com } 125012724Snikos.nikoleris@arm.com 125113445Sodanrc@yahoo.com.br // Block is guaranteed to be valid at this point 125213445Sodanrc@yahoo.com.br assert(blk->isValid()); 125313445Sodanrc@yahoo.com.br assert(blk->isSecure() == is_secure); 125413445Sodanrc@yahoo.com.br assert(regenerateBlkAddr(blk) == addr); 125513445Sodanrc@yahoo.com.br 125613445Sodanrc@yahoo.com.br blk->status |= BlkReadable; 125712724Snikos.nikoleris@arm.com 125812724Snikos.nikoleris@arm.com // sanity check for whole-line writes, which should always be 125912724Snikos.nikoleris@arm.com // marked as writable as part of the fill, and then later marked 126012724Snikos.nikoleris@arm.com // dirty as part of satisfyRequest 126113350Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::InvalidateResp) { 126212724Snikos.nikoleris@arm.com assert(!pkt->hasSharers()); 126312724Snikos.nikoleris@arm.com } 126412724Snikos.nikoleris@arm.com 126512724Snikos.nikoleris@arm.com // here we deal with setting the appropriate state of the line, 126612724Snikos.nikoleris@arm.com // and we start by looking at the hasSharers flag, and ignore the 126712724Snikos.nikoleris@arm.com // cacheResponding flag (normally signalling dirty data) if the 126812724Snikos.nikoleris@arm.com // packet has sharers, thus the line is never allocated as Owned 126912724Snikos.nikoleris@arm.com // (dirty but not writable), and always ends up being either 127012724Snikos.nikoleris@arm.com // Shared, Exclusive or Modified, see Packet::setCacheResponding 127112724Snikos.nikoleris@arm.com // for more details 127212724Snikos.nikoleris@arm.com if (!pkt->hasSharers()) { 127312724Snikos.nikoleris@arm.com // we could get a writable line from memory (rather than a 127412724Snikos.nikoleris@arm.com // cache) even in a read-only cache, note that we set this bit 127512724Snikos.nikoleris@arm.com // even for a read-only cache, possibly revisit this decision 127612724Snikos.nikoleris@arm.com blk->status |= BlkWritable; 127712724Snikos.nikoleris@arm.com 127812724Snikos.nikoleris@arm.com // check if we got this via cache-to-cache transfer (i.e., from a 127912724Snikos.nikoleris@arm.com // cache that had the block in Modified or Owned state) 128012724Snikos.nikoleris@arm.com if (pkt->cacheResponding()) { 128112724Snikos.nikoleris@arm.com // we got the block in Modified state, and invalidated the 128212724Snikos.nikoleris@arm.com // owners copy 128312724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 128412724Snikos.nikoleris@arm.com 128512724Snikos.nikoleris@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 128612724Snikos.nikoleris@arm.com "in read-only cache %s\n", name()); 128713932Snikos.nikoleris@arm.com 128813932Snikos.nikoleris@arm.com } else if (pkt->cmd.isSWPrefetch() && pkt->needsWritable()) { 128913932Snikos.nikoleris@arm.com // All other copies of the block were invalidated and we 129013932Snikos.nikoleris@arm.com // have an exclusive copy. 129113932Snikos.nikoleris@arm.com 129213932Snikos.nikoleris@arm.com // The coherence protocol assumes that if we fetched an 129313932Snikos.nikoleris@arm.com // exclusive copy of the block, we have the intention to 129413932Snikos.nikoleris@arm.com // modify it. Therefore the MSHR for the PrefetchExReq has 129513932Snikos.nikoleris@arm.com // been the point of ordering and this cache has commited 129613932Snikos.nikoleris@arm.com // to respond to snoops for the block. 129713932Snikos.nikoleris@arm.com // 129813932Snikos.nikoleris@arm.com // In most cases this is true anyway - a PrefetchExReq 129913932Snikos.nikoleris@arm.com // will be followed by a WriteReq. However, if that 130013932Snikos.nikoleris@arm.com // doesn't happen, the block is not marked as dirty and 130113932Snikos.nikoleris@arm.com // the cache doesn't respond to snoops that has committed 130213932Snikos.nikoleris@arm.com // to do so. 130313932Snikos.nikoleris@arm.com // 130413932Snikos.nikoleris@arm.com // To avoid deadlocks in cases where there is a snoop 130513932Snikos.nikoleris@arm.com // between the PrefetchExReq and the expected WriteReq, we 130613932Snikos.nikoleris@arm.com // proactively mark the block as Dirty. 130713932Snikos.nikoleris@arm.com 130813932Snikos.nikoleris@arm.com blk->status |= BlkDirty; 130913932Snikos.nikoleris@arm.com 131013932Snikos.nikoleris@arm.com panic_if(!isReadOnly, "Prefetch exclusive requests from read-only " 131113932Snikos.nikoleris@arm.com "cache %s\n", name()); 131212724Snikos.nikoleris@arm.com } 131312724Snikos.nikoleris@arm.com } 131412724Snikos.nikoleris@arm.com 131512724Snikos.nikoleris@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 131612724Snikos.nikoleris@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 131712724Snikos.nikoleris@arm.com 131812724Snikos.nikoleris@arm.com // if we got new data, copy it in (checking for a read response 131912724Snikos.nikoleris@arm.com // and a response that has data is the same in the end) 132012724Snikos.nikoleris@arm.com if (pkt->isRead()) { 132112724Snikos.nikoleris@arm.com // sanity checks 132212724Snikos.nikoleris@arm.com assert(pkt->hasData()); 132312724Snikos.nikoleris@arm.com assert(pkt->getSize() == blkSize); 132412724Snikos.nikoleris@arm.com 132512724Snikos.nikoleris@arm.com pkt->writeDataToBlock(blk->data, blkSize); 132612724Snikos.nikoleris@arm.com } 132713750Sodanrc@yahoo.com.br // The block will be ready when the payload arrives and the fill is done 132813750Sodanrc@yahoo.com.br blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay + 132913750Sodanrc@yahoo.com.br pkt->payloadDelay); 133012724Snikos.nikoleris@arm.com 133112724Snikos.nikoleris@arm.com return blk; 133212724Snikos.nikoleris@arm.com} 133312724Snikos.nikoleris@arm.com 133412724Snikos.nikoleris@arm.comCacheBlk* 133512754Sodanrc@yahoo.com.brBaseCache::allocateBlock(const PacketPtr pkt, PacketList &writebacks) 133612724Snikos.nikoleris@arm.com{ 133712754Sodanrc@yahoo.com.br // Get address 133812754Sodanrc@yahoo.com.br const Addr addr = pkt->getAddr(); 133912754Sodanrc@yahoo.com.br 134012754Sodanrc@yahoo.com.br // Get secure bit 134112754Sodanrc@yahoo.com.br const bool is_secure = pkt->isSecure(); 134212754Sodanrc@yahoo.com.br 134313945Sodanrc@yahoo.com.br // Block size and compression related access latency. Only relevant if 134413945Sodanrc@yahoo.com.br // using a compressor, otherwise there is no extra delay, and the block 134513945Sodanrc@yahoo.com.br // is fully sized 134613941Sodanrc@yahoo.com.br std::size_t blk_size_bits = blkSize*8; 134713945Sodanrc@yahoo.com.br Cycles compression_lat = Cycles(0); 134813945Sodanrc@yahoo.com.br Cycles decompression_lat = Cycles(0); 134913945Sodanrc@yahoo.com.br 135013945Sodanrc@yahoo.com.br // If a compressor is being used, it is called to compress data before 135113945Sodanrc@yahoo.com.br // insertion. Although in Gem5 the data is stored uncompressed, even if a 135213945Sodanrc@yahoo.com.br // compressor is used, the compression/decompression methods are called to 135313945Sodanrc@yahoo.com.br // calculate the amount of extra cycles needed to read or write compressed 135413945Sodanrc@yahoo.com.br // blocks. 135513945Sodanrc@yahoo.com.br if (compressor) { 135613945Sodanrc@yahoo.com.br compressor->compress(pkt->getConstPtr<uint64_t>(), compression_lat, 135713945Sodanrc@yahoo.com.br decompression_lat, blk_size_bits); 135813945Sodanrc@yahoo.com.br } 135913941Sodanrc@yahoo.com.br 136012724Snikos.nikoleris@arm.com // Find replacement victim 136112744Sodanrc@yahoo.com.br std::vector<CacheBlk*> evict_blks; 136213941Sodanrc@yahoo.com.br CacheBlk *victim = tags->findVictim(addr, is_secure, blk_size_bits, 136313941Sodanrc@yahoo.com.br evict_blks); 136412724Snikos.nikoleris@arm.com 136512724Snikos.nikoleris@arm.com // It is valid to return nullptr if there is no victim 136612744Sodanrc@yahoo.com.br if (!victim) 136712724Snikos.nikoleris@arm.com return nullptr; 136812724Snikos.nikoleris@arm.com 136913222Sodanrc@yahoo.com.br // Print victim block's information 137013222Sodanrc@yahoo.com.br DPRINTF(CacheRepl, "Replacement victim: %s\n", victim->print()); 137113222Sodanrc@yahoo.com.br 137212744Sodanrc@yahoo.com.br // Check for transient state allocations. If any of the entries listed 137312744Sodanrc@yahoo.com.br // for eviction has a transient state, the allocation fails 137413866Sodanrc@yahoo.com.br bool replacement = false; 137512744Sodanrc@yahoo.com.br for (const auto& blk : evict_blks) { 137612744Sodanrc@yahoo.com.br if (blk->isValid()) { 137713866Sodanrc@yahoo.com.br replacement = true; 137813866Sodanrc@yahoo.com.br 137912744Sodanrc@yahoo.com.br Addr repl_addr = regenerateBlkAddr(blk); 138012744Sodanrc@yahoo.com.br MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 138112744Sodanrc@yahoo.com.br if (repl_mshr) { 138212744Sodanrc@yahoo.com.br // must be an outstanding upgrade or clean request 138312744Sodanrc@yahoo.com.br // on a block we're about to replace... 138412744Sodanrc@yahoo.com.br assert((!blk->isWritable() && repl_mshr->needsWritable()) || 138512744Sodanrc@yahoo.com.br repl_mshr->isCleaning()); 138612724Snikos.nikoleris@arm.com 138712744Sodanrc@yahoo.com.br // too hard to replace block with transient state 138812744Sodanrc@yahoo.com.br // allocation failed, block not inserted 138912744Sodanrc@yahoo.com.br return nullptr; 139012744Sodanrc@yahoo.com.br } 139112744Sodanrc@yahoo.com.br } 139212744Sodanrc@yahoo.com.br } 139312744Sodanrc@yahoo.com.br 139412744Sodanrc@yahoo.com.br // The victim will be replaced by a new entry, so increase the replacement 139512744Sodanrc@yahoo.com.br // counter if a valid block is being replaced 139613866Sodanrc@yahoo.com.br if (replacement) { 139713866Sodanrc@yahoo.com.br // Evict valid blocks associated to this victim block 139813863Sodanrc@yahoo.com.br for (const auto& blk : evict_blks) { 139913863Sodanrc@yahoo.com.br if (blk->isValid()) { 140013863Sodanrc@yahoo.com.br DPRINTF(CacheRepl, "Evicting %s (%#llx) to make room for " \ 140113863Sodanrc@yahoo.com.br "%#llx (%s)\n", blk->print(), regenerateBlkAddr(blk), 140213863Sodanrc@yahoo.com.br addr, is_secure); 140313866Sodanrc@yahoo.com.br 140413866Sodanrc@yahoo.com.br if (blk->wasPrefetched()) { 140513866Sodanrc@yahoo.com.br unusedPrefetches++; 140613866Sodanrc@yahoo.com.br } 140713866Sodanrc@yahoo.com.br 140813866Sodanrc@yahoo.com.br evictBlock(blk, writebacks); 140913863Sodanrc@yahoo.com.br } 141013863Sodanrc@yahoo.com.br } 141112744Sodanrc@yahoo.com.br 141212744Sodanrc@yahoo.com.br replacements++; 141312744Sodanrc@yahoo.com.br } 141412744Sodanrc@yahoo.com.br 141513945Sodanrc@yahoo.com.br // If using a compressor, set compression data. This must be done before 141613945Sodanrc@yahoo.com.br // block insertion, as compressed tags use this information. 141713945Sodanrc@yahoo.com.br if (compressor) { 141813945Sodanrc@yahoo.com.br compressor->setSizeBits(victim, blk_size_bits); 141913945Sodanrc@yahoo.com.br compressor->setDecompressionLatency(victim, decompression_lat); 142013945Sodanrc@yahoo.com.br } 142113945Sodanrc@yahoo.com.br 142212754Sodanrc@yahoo.com.br // Insert new block at victimized entry 142313752Sodanrc@yahoo.com.br tags->insertBlock(pkt, victim); 142412754Sodanrc@yahoo.com.br 142512744Sodanrc@yahoo.com.br return victim; 142612724Snikos.nikoleris@arm.com} 142712724Snikos.nikoleris@arm.com 142812724Snikos.nikoleris@arm.comvoid 142912724Snikos.nikoleris@arm.comBaseCache::invalidateBlock(CacheBlk *blk) 143012724Snikos.nikoleris@arm.com{ 143113376Sodanrc@yahoo.com.br // If handling a block present in the Tags, let it do its invalidation 143213376Sodanrc@yahoo.com.br // process, which will update stats and invalidate the block itself 143313376Sodanrc@yahoo.com.br if (blk != tempBlock) { 143412724Snikos.nikoleris@arm.com tags->invalidate(blk); 143513376Sodanrc@yahoo.com.br } else { 143613376Sodanrc@yahoo.com.br tempBlock->invalidate(); 143713376Sodanrc@yahoo.com.br } 143812724Snikos.nikoleris@arm.com} 143912724Snikos.nikoleris@arm.com 144013358Sodanrc@yahoo.com.brvoid 144113358Sodanrc@yahoo.com.brBaseCache::evictBlock(CacheBlk *blk, PacketList &writebacks) 144213358Sodanrc@yahoo.com.br{ 144313358Sodanrc@yahoo.com.br PacketPtr pkt = evictBlock(blk); 144413358Sodanrc@yahoo.com.br if (pkt) { 144513358Sodanrc@yahoo.com.br writebacks.push_back(pkt); 144613358Sodanrc@yahoo.com.br } 144713358Sodanrc@yahoo.com.br} 144813358Sodanrc@yahoo.com.br 144912724Snikos.nikoleris@arm.comPacketPtr 145012724Snikos.nikoleris@arm.comBaseCache::writebackBlk(CacheBlk *blk) 145112724Snikos.nikoleris@arm.com{ 145212724Snikos.nikoleris@arm.com chatty_assert(!isReadOnly || writebackClean, 145312724Snikos.nikoleris@arm.com "Writeback from read-only cache"); 145412724Snikos.nikoleris@arm.com assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 145512724Snikos.nikoleris@arm.com 145612724Snikos.nikoleris@arm.com writebacks[Request::wbMasterId]++; 145712724Snikos.nikoleris@arm.com 145812749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 145912749Sgiacomo.travaglini@arm.com regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 146012749Sgiacomo.travaglini@arm.com 146112724Snikos.nikoleris@arm.com if (blk->isSecure()) 146212724Snikos.nikoleris@arm.com req->setFlags(Request::SECURE); 146312724Snikos.nikoleris@arm.com 146412724Snikos.nikoleris@arm.com req->taskId(blk->task_id); 146512724Snikos.nikoleris@arm.com 146612724Snikos.nikoleris@arm.com PacketPtr pkt = 146712724Snikos.nikoleris@arm.com new Packet(req, blk->isDirty() ? 146812724Snikos.nikoleris@arm.com MemCmd::WritebackDirty : MemCmd::WritebackClean); 146912724Snikos.nikoleris@arm.com 147012724Snikos.nikoleris@arm.com DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n", 147112724Snikos.nikoleris@arm.com pkt->print(), blk->isWritable(), blk->isDirty()); 147212724Snikos.nikoleris@arm.com 147312724Snikos.nikoleris@arm.com if (blk->isWritable()) { 147412724Snikos.nikoleris@arm.com // not asserting shared means we pass the block in modified 147512724Snikos.nikoleris@arm.com // state, mark our own block non-writeable 147612724Snikos.nikoleris@arm.com blk->status &= ~BlkWritable; 147712724Snikos.nikoleris@arm.com } else { 147812724Snikos.nikoleris@arm.com // we are in the Owned state, tell the receiver 147912724Snikos.nikoleris@arm.com pkt->setHasSharers(); 148012724Snikos.nikoleris@arm.com } 148112724Snikos.nikoleris@arm.com 148212724Snikos.nikoleris@arm.com // make sure the block is not marked dirty 148312724Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 148412724Snikos.nikoleris@arm.com 148512724Snikos.nikoleris@arm.com pkt->allocate(); 148612724Snikos.nikoleris@arm.com pkt->setDataFromBlock(blk->data, blkSize); 148712724Snikos.nikoleris@arm.com 148813945Sodanrc@yahoo.com.br // When a block is compressed, it must first be decompressed before being 148913945Sodanrc@yahoo.com.br // sent for writeback. 149013945Sodanrc@yahoo.com.br if (compressor) { 149113945Sodanrc@yahoo.com.br pkt->payloadDelay = compressor->getDecompressionLatency(blk); 149213945Sodanrc@yahoo.com.br } 149313945Sodanrc@yahoo.com.br 149412724Snikos.nikoleris@arm.com return pkt; 149512724Snikos.nikoleris@arm.com} 149612724Snikos.nikoleris@arm.com 149712724Snikos.nikoleris@arm.comPacketPtr 149812724Snikos.nikoleris@arm.comBaseCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id) 149912724Snikos.nikoleris@arm.com{ 150012749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 150112749Sgiacomo.travaglini@arm.com regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 150212749Sgiacomo.travaglini@arm.com 150312724Snikos.nikoleris@arm.com if (blk->isSecure()) { 150412724Snikos.nikoleris@arm.com req->setFlags(Request::SECURE); 150512724Snikos.nikoleris@arm.com } 150612724Snikos.nikoleris@arm.com req->taskId(blk->task_id); 150712724Snikos.nikoleris@arm.com 150812724Snikos.nikoleris@arm.com PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id); 150912724Snikos.nikoleris@arm.com 151012724Snikos.nikoleris@arm.com if (dest) { 151112724Snikos.nikoleris@arm.com req->setFlags(dest); 151212724Snikos.nikoleris@arm.com pkt->setWriteThrough(); 151312724Snikos.nikoleris@arm.com } 151412724Snikos.nikoleris@arm.com 151512724Snikos.nikoleris@arm.com DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(), 151612724Snikos.nikoleris@arm.com blk->isWritable(), blk->isDirty()); 151712724Snikos.nikoleris@arm.com 151812724Snikos.nikoleris@arm.com if (blk->isWritable()) { 151912724Snikos.nikoleris@arm.com // not asserting shared means we pass the block in modified 152012724Snikos.nikoleris@arm.com // state, mark our own block non-writeable 152112724Snikos.nikoleris@arm.com blk->status &= ~BlkWritable; 152212724Snikos.nikoleris@arm.com } else { 152312724Snikos.nikoleris@arm.com // we are in the Owned state, tell the receiver 152412724Snikos.nikoleris@arm.com pkt->setHasSharers(); 152512724Snikos.nikoleris@arm.com } 152612724Snikos.nikoleris@arm.com 152712724Snikos.nikoleris@arm.com // make sure the block is not marked dirty 152812724Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 152912724Snikos.nikoleris@arm.com 153012724Snikos.nikoleris@arm.com pkt->allocate(); 153112724Snikos.nikoleris@arm.com pkt->setDataFromBlock(blk->data, blkSize); 153212724Snikos.nikoleris@arm.com 153313945Sodanrc@yahoo.com.br // When a block is compressed, it must first be decompressed before being 153413945Sodanrc@yahoo.com.br // sent for writeback. 153513945Sodanrc@yahoo.com.br if (compressor) { 153613945Sodanrc@yahoo.com.br pkt->payloadDelay = compressor->getDecompressionLatency(blk); 153713945Sodanrc@yahoo.com.br } 153813945Sodanrc@yahoo.com.br 153912724Snikos.nikoleris@arm.com return pkt; 154012724Snikos.nikoleris@arm.com} 154112724Snikos.nikoleris@arm.com 154212724Snikos.nikoleris@arm.com 154312724Snikos.nikoleris@arm.comvoid 154412724Snikos.nikoleris@arm.comBaseCache::memWriteback() 154512724Snikos.nikoleris@arm.com{ 154612728Snikos.nikoleris@arm.com tags->forEachBlk([this](CacheBlk &blk) { writebackVisitor(blk); }); 154712724Snikos.nikoleris@arm.com} 154812724Snikos.nikoleris@arm.com 154912724Snikos.nikoleris@arm.comvoid 155012724Snikos.nikoleris@arm.comBaseCache::memInvalidate() 155112724Snikos.nikoleris@arm.com{ 155212728Snikos.nikoleris@arm.com tags->forEachBlk([this](CacheBlk &blk) { invalidateVisitor(blk); }); 155312724Snikos.nikoleris@arm.com} 155412724Snikos.nikoleris@arm.com 155512724Snikos.nikoleris@arm.combool 155612724Snikos.nikoleris@arm.comBaseCache::isDirty() const 155712724Snikos.nikoleris@arm.com{ 155812728Snikos.nikoleris@arm.com return tags->anyBlk([](CacheBlk &blk) { return blk.isDirty(); }); 155912724Snikos.nikoleris@arm.com} 156012724Snikos.nikoleris@arm.com 156113416Sjavier.bueno@metempsy.combool 156213416Sjavier.bueno@metempsy.comBaseCache::coalesce() const 156313416Sjavier.bueno@metempsy.com{ 156413416Sjavier.bueno@metempsy.com return writeAllocator && writeAllocator->coalesce(); 156513416Sjavier.bueno@metempsy.com} 156613416Sjavier.bueno@metempsy.com 156712728Snikos.nikoleris@arm.comvoid 156812724Snikos.nikoleris@arm.comBaseCache::writebackVisitor(CacheBlk &blk) 156912724Snikos.nikoleris@arm.com{ 157012724Snikos.nikoleris@arm.com if (blk.isDirty()) { 157112724Snikos.nikoleris@arm.com assert(blk.isValid()); 157212724Snikos.nikoleris@arm.com 157312749Sgiacomo.travaglini@arm.com RequestPtr request = std::make_shared<Request>( 157412749Sgiacomo.travaglini@arm.com regenerateBlkAddr(&blk), blkSize, 0, Request::funcMasterId); 157512749Sgiacomo.travaglini@arm.com 157612749Sgiacomo.travaglini@arm.com request->taskId(blk.task_id); 157712724Snikos.nikoleris@arm.com if (blk.isSecure()) { 157812749Sgiacomo.travaglini@arm.com request->setFlags(Request::SECURE); 157912724Snikos.nikoleris@arm.com } 158012724Snikos.nikoleris@arm.com 158112749Sgiacomo.travaglini@arm.com Packet packet(request, MemCmd::WriteReq); 158212724Snikos.nikoleris@arm.com packet.dataStatic(blk.data); 158312724Snikos.nikoleris@arm.com 158412724Snikos.nikoleris@arm.com memSidePort.sendFunctional(&packet); 158512724Snikos.nikoleris@arm.com 158612724Snikos.nikoleris@arm.com blk.status &= ~BlkDirty; 158712724Snikos.nikoleris@arm.com } 158812724Snikos.nikoleris@arm.com} 158912724Snikos.nikoleris@arm.com 159012728Snikos.nikoleris@arm.comvoid 159112724Snikos.nikoleris@arm.comBaseCache::invalidateVisitor(CacheBlk &blk) 159212724Snikos.nikoleris@arm.com{ 159312724Snikos.nikoleris@arm.com if (blk.isDirty()) 159412724Snikos.nikoleris@arm.com warn_once("Invalidating dirty cache lines. " \ 159512724Snikos.nikoleris@arm.com "Expect things to break.\n"); 159612724Snikos.nikoleris@arm.com 159712724Snikos.nikoleris@arm.com if (blk.isValid()) { 159812724Snikos.nikoleris@arm.com assert(!blk.isDirty()); 159912724Snikos.nikoleris@arm.com invalidateBlock(&blk); 160012724Snikos.nikoleris@arm.com } 160112724Snikos.nikoleris@arm.com} 160212724Snikos.nikoleris@arm.com 160312724Snikos.nikoleris@arm.comTick 160412724Snikos.nikoleris@arm.comBaseCache::nextQueueReadyTime() const 160512724Snikos.nikoleris@arm.com{ 160612724Snikos.nikoleris@arm.com Tick nextReady = std::min(mshrQueue.nextReadyTime(), 160712724Snikos.nikoleris@arm.com writeBuffer.nextReadyTime()); 160812724Snikos.nikoleris@arm.com 160912724Snikos.nikoleris@arm.com // Don't signal prefetch ready time if no MSHRs available 161012724Snikos.nikoleris@arm.com // Will signal once enoguh MSHRs are deallocated 161112724Snikos.nikoleris@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 161212724Snikos.nikoleris@arm.com nextReady = std::min(nextReady, 161312724Snikos.nikoleris@arm.com prefetcher->nextPrefetchReadyTime()); 161412724Snikos.nikoleris@arm.com } 161512724Snikos.nikoleris@arm.com 161612724Snikos.nikoleris@arm.com return nextReady; 161712724Snikos.nikoleris@arm.com} 161812724Snikos.nikoleris@arm.com 161912724Snikos.nikoleris@arm.com 162012724Snikos.nikoleris@arm.combool 162112724Snikos.nikoleris@arm.comBaseCache::sendMSHRQueuePacket(MSHR* mshr) 162212724Snikos.nikoleris@arm.com{ 162312724Snikos.nikoleris@arm.com assert(mshr); 162412724Snikos.nikoleris@arm.com 162512724Snikos.nikoleris@arm.com // use request from 1st target 162612724Snikos.nikoleris@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 162712724Snikos.nikoleris@arm.com 162812724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 162912724Snikos.nikoleris@arm.com 163013352Snikos.nikoleris@arm.com // if the cache is in write coalescing mode or (additionally) in 163113352Snikos.nikoleris@arm.com // no allocation mode, and we have a write packet with an MSHR 163213352Snikos.nikoleris@arm.com // that is not a whole-line write (due to incompatible flags etc), 163313352Snikos.nikoleris@arm.com // then reset the write mode 163413352Snikos.nikoleris@arm.com if (writeAllocator && writeAllocator->coalesce() && tgt_pkt->isWrite()) { 163513352Snikos.nikoleris@arm.com if (!mshr->isWholeLineWrite()) { 163613352Snikos.nikoleris@arm.com // if we are currently write coalescing, hold on the 163713352Snikos.nikoleris@arm.com // MSHR as many cycles extra as we need to completely 163813352Snikos.nikoleris@arm.com // write a cache line 163913352Snikos.nikoleris@arm.com if (writeAllocator->delay(mshr->blkAddr)) { 164013352Snikos.nikoleris@arm.com Tick delay = blkSize / tgt_pkt->getSize() * clockPeriod(); 164113352Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "Delaying pkt %s %llu ticks to allow " 164213352Snikos.nikoleris@arm.com "for write coalescing\n", tgt_pkt->print(), delay); 164313352Snikos.nikoleris@arm.com mshrQueue.delay(mshr, delay); 164413352Snikos.nikoleris@arm.com return false; 164513352Snikos.nikoleris@arm.com } else { 164613352Snikos.nikoleris@arm.com writeAllocator->reset(); 164713352Snikos.nikoleris@arm.com } 164813352Snikos.nikoleris@arm.com } else { 164913352Snikos.nikoleris@arm.com writeAllocator->resetDelay(mshr->blkAddr); 165013352Snikos.nikoleris@arm.com } 165113352Snikos.nikoleris@arm.com } 165213352Snikos.nikoleris@arm.com 165312724Snikos.nikoleris@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 165412724Snikos.nikoleris@arm.com 165512724Snikos.nikoleris@arm.com // either a prefetch that is not present upstream, or a normal 165612724Snikos.nikoleris@arm.com // MSHR request, proceed to get the packet to send downstream 165713350Snikos.nikoleris@arm.com PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable(), 165813350Snikos.nikoleris@arm.com mshr->isWholeLineWrite()); 165912724Snikos.nikoleris@arm.com 166012724Snikos.nikoleris@arm.com mshr->isForward = (pkt == nullptr); 166112724Snikos.nikoleris@arm.com 166212724Snikos.nikoleris@arm.com if (mshr->isForward) { 166312724Snikos.nikoleris@arm.com // not a cache block request, but a response is expected 166412724Snikos.nikoleris@arm.com // make copy of current packet to forward, keep current 166512724Snikos.nikoleris@arm.com // copy for response handling 166612724Snikos.nikoleris@arm.com pkt = new Packet(tgt_pkt, false, true); 166712724Snikos.nikoleris@arm.com assert(!pkt->isWrite()); 166812724Snikos.nikoleris@arm.com } 166912724Snikos.nikoleris@arm.com 167012724Snikos.nikoleris@arm.com // play it safe and append (rather than set) the sender state, 167112724Snikos.nikoleris@arm.com // as forwarded packets may already have existing state 167212724Snikos.nikoleris@arm.com pkt->pushSenderState(mshr); 167312724Snikos.nikoleris@arm.com 167412724Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 167512724Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty block. Mark 167612724Snikos.nikoleris@arm.com // the packet so that the destination xbar can determine that 167712724Snikos.nikoleris@arm.com // there will be a follow-up write packet as well. 167812724Snikos.nikoleris@arm.com pkt->setSatisfied(); 167912724Snikos.nikoleris@arm.com } 168012724Snikos.nikoleris@arm.com 168112724Snikos.nikoleris@arm.com if (!memSidePort.sendTimingReq(pkt)) { 168212724Snikos.nikoleris@arm.com // we are awaiting a retry, but we 168312724Snikos.nikoleris@arm.com // delete the packet and will be creating a new packet 168412724Snikos.nikoleris@arm.com // when we get the opportunity 168512724Snikos.nikoleris@arm.com delete pkt; 168612724Snikos.nikoleris@arm.com 168712724Snikos.nikoleris@arm.com // note that we have now masked any requestBus and 168812724Snikos.nikoleris@arm.com // schedSendEvent (we will wait for a retry before 168912724Snikos.nikoleris@arm.com // doing anything), and this is so even if we do not 169012724Snikos.nikoleris@arm.com // care about this packet and might override it before 169112724Snikos.nikoleris@arm.com // it gets retried 169212724Snikos.nikoleris@arm.com return true; 169312724Snikos.nikoleris@arm.com } else { 169412724Snikos.nikoleris@arm.com // As part of the call to sendTimingReq the packet is 169512724Snikos.nikoleris@arm.com // forwarded to all neighbouring caches (and any caches 169612724Snikos.nikoleris@arm.com // above them) as a snoop. Thus at this point we know if 169712724Snikos.nikoleris@arm.com // any of the neighbouring caches are responding, and if 169812724Snikos.nikoleris@arm.com // so, we know it is dirty, and we can determine if it is 169912724Snikos.nikoleris@arm.com // being passed as Modified, making our MSHR the ordering 170012724Snikos.nikoleris@arm.com // point 170112724Snikos.nikoleris@arm.com bool pending_modified_resp = !pkt->hasSharers() && 170212724Snikos.nikoleris@arm.com pkt->cacheResponding(); 170312724Snikos.nikoleris@arm.com markInService(mshr, pending_modified_resp); 170412724Snikos.nikoleris@arm.com 170512724Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 170612724Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty 170712724Snikos.nikoleris@arm.com // block. If a dirty block is encountered a WriteClean 170812724Snikos.nikoleris@arm.com // will update any copies to the path to the memory 170912724Snikos.nikoleris@arm.com // until the point of reference. 171012724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 171112724Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 171212724Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), 171312724Snikos.nikoleris@arm.com pkt->id); 171412724Snikos.nikoleris@arm.com PacketList writebacks; 171512724Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 171612724Snikos.nikoleris@arm.com doWritebacks(writebacks, 0); 171712724Snikos.nikoleris@arm.com } 171812724Snikos.nikoleris@arm.com 171912724Snikos.nikoleris@arm.com return false; 172012724Snikos.nikoleris@arm.com } 172112724Snikos.nikoleris@arm.com} 172212724Snikos.nikoleris@arm.com 172312724Snikos.nikoleris@arm.combool 172412724Snikos.nikoleris@arm.comBaseCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 172512724Snikos.nikoleris@arm.com{ 172612724Snikos.nikoleris@arm.com assert(wq_entry); 172712724Snikos.nikoleris@arm.com 172812724Snikos.nikoleris@arm.com // always a single target for write queue entries 172912724Snikos.nikoleris@arm.com PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 173012724Snikos.nikoleris@arm.com 173112724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print()); 173212724Snikos.nikoleris@arm.com 173312724Snikos.nikoleris@arm.com // forward as is, both for evictions and uncacheable writes 173412724Snikos.nikoleris@arm.com if (!memSidePort.sendTimingReq(tgt_pkt)) { 173512724Snikos.nikoleris@arm.com // note that we have now masked any requestBus and 173612724Snikos.nikoleris@arm.com // schedSendEvent (we will wait for a retry before 173712724Snikos.nikoleris@arm.com // doing anything), and this is so even if we do not 173812724Snikos.nikoleris@arm.com // care about this packet and might override it before 173912724Snikos.nikoleris@arm.com // it gets retried 174012724Snikos.nikoleris@arm.com return true; 174112724Snikos.nikoleris@arm.com } else { 174212724Snikos.nikoleris@arm.com markInService(wq_entry); 174312724Snikos.nikoleris@arm.com return false; 174412724Snikos.nikoleris@arm.com } 174512724Snikos.nikoleris@arm.com} 174612724Snikos.nikoleris@arm.com 174712724Snikos.nikoleris@arm.comvoid 174812724Snikos.nikoleris@arm.comBaseCache::serialize(CheckpointOut &cp) const 174912724Snikos.nikoleris@arm.com{ 175012724Snikos.nikoleris@arm.com bool dirty(isDirty()); 175112724Snikos.nikoleris@arm.com 175212724Snikos.nikoleris@arm.com if (dirty) { 175312724Snikos.nikoleris@arm.com warn("*** The cache still contains dirty data. ***\n"); 175412724Snikos.nikoleris@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 175512724Snikos.nikoleris@arm.com warn(" This checkpoint will not restore correctly " \ 175612724Snikos.nikoleris@arm.com "and dirty data in the cache will be lost!\n"); 175712724Snikos.nikoleris@arm.com } 175812724Snikos.nikoleris@arm.com 175912724Snikos.nikoleris@arm.com // Since we don't checkpoint the data in the cache, any dirty data 176012724Snikos.nikoleris@arm.com // will be lost when restoring from a checkpoint of a system that 176112724Snikos.nikoleris@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 176212724Snikos.nikoleris@arm.com // cache contains dirty data. 176312724Snikos.nikoleris@arm.com bool bad_checkpoint(dirty); 176412724Snikos.nikoleris@arm.com SERIALIZE_SCALAR(bad_checkpoint); 176512724Snikos.nikoleris@arm.com} 176612724Snikos.nikoleris@arm.com 176712724Snikos.nikoleris@arm.comvoid 176812724Snikos.nikoleris@arm.comBaseCache::unserialize(CheckpointIn &cp) 176912724Snikos.nikoleris@arm.com{ 177012724Snikos.nikoleris@arm.com bool bad_checkpoint; 177112724Snikos.nikoleris@arm.com UNSERIALIZE_SCALAR(bad_checkpoint); 177212724Snikos.nikoleris@arm.com if (bad_checkpoint) { 177312724Snikos.nikoleris@arm.com fatal("Restoring from checkpoints with dirty caches is not " 177412724Snikos.nikoleris@arm.com "supported in the classic memory system. Please remove any " 177512724Snikos.nikoleris@arm.com "caches or drain them properly before taking checkpoints.\n"); 177612724Snikos.nikoleris@arm.com } 177712724Snikos.nikoleris@arm.com} 177812724Snikos.nikoleris@arm.com 177912724Snikos.nikoleris@arm.comvoid 17802810SN/ABaseCache::regStats() 17812810SN/A{ 178213892Sgabeblack@google.com ClockedObject::regStats(); 178311522Sstephan.diestelhorst@arm.com 17842810SN/A using namespace Stats; 17852810SN/A 17862810SN/A // Hit statistics 17874022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 17884022SN/A MemCmd cmd(access_idx); 17894022SN/A const string &cstr = cmd.toString(); 17902810SN/A 17912810SN/A hits[access_idx] 17928833Sdam.sunwoo@arm.com .init(system->maxMasters()) 17932810SN/A .name(name() + "." + cstr + "_hits") 17942810SN/A .desc("number of " + cstr + " hits") 17952810SN/A .flags(total | nozero | nonan) 17962810SN/A ; 17978833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17988833Sdam.sunwoo@arm.com hits[access_idx].subname(i, system->getMasterName(i)); 17998833Sdam.sunwoo@arm.com } 18002810SN/A } 18012810SN/A 18024871SN/A// These macros make it easier to sum the right subset of commands and 18034871SN/A// to change the subset of commands that are considered "demand" vs 18044871SN/A// "non-demand" 18054871SN/A#define SUM_DEMAND(s) \ 180611455Sandreas.hansson@arm.com (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \ 180710885Sandreas.hansson@arm.com s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq]) 18084871SN/A 18094871SN/A// should writebacks be included here? prior code was inconsistent... 18104871SN/A#define SUM_NON_DEMAND(s) \ 181113367Syuetsu.kodama@riken.jp (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq] + s[MemCmd::SoftPFExReq]) 18124871SN/A 18132810SN/A demandHits 18142810SN/A .name(name() + ".demand_hits") 18152810SN/A .desc("number of demand (read+write) hits") 18168833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 18172810SN/A ; 18184871SN/A demandHits = SUM_DEMAND(hits); 18198833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18208833Sdam.sunwoo@arm.com demandHits.subname(i, system->getMasterName(i)); 18218833Sdam.sunwoo@arm.com } 18222810SN/A 18232810SN/A overallHits 18242810SN/A .name(name() + ".overall_hits") 18252810SN/A .desc("number of overall hits") 18268833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 18272810SN/A ; 18284871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 18298833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18308833Sdam.sunwoo@arm.com overallHits.subname(i, system->getMasterName(i)); 18318833Sdam.sunwoo@arm.com } 18322810SN/A 18332810SN/A // Miss statistics 18344022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 18354022SN/A MemCmd cmd(access_idx); 18364022SN/A const string &cstr = cmd.toString(); 18372810SN/A 18382810SN/A misses[access_idx] 18398833Sdam.sunwoo@arm.com .init(system->maxMasters()) 18402810SN/A .name(name() + "." + cstr + "_misses") 18412810SN/A .desc("number of " + cstr + " misses") 18422810SN/A .flags(total | nozero | nonan) 18432810SN/A ; 18448833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18458833Sdam.sunwoo@arm.com misses[access_idx].subname(i, system->getMasterName(i)); 18468833Sdam.sunwoo@arm.com } 18472810SN/A } 18482810SN/A 18492810SN/A demandMisses 18502810SN/A .name(name() + ".demand_misses") 18512810SN/A .desc("number of demand (read+write) misses") 18528833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 18532810SN/A ; 18544871SN/A demandMisses = SUM_DEMAND(misses); 18558833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18568833Sdam.sunwoo@arm.com demandMisses.subname(i, system->getMasterName(i)); 18578833Sdam.sunwoo@arm.com } 18582810SN/A 18592810SN/A overallMisses 18602810SN/A .name(name() + ".overall_misses") 18612810SN/A .desc("number of overall misses") 18628833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 18632810SN/A ; 18644871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 18658833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18668833Sdam.sunwoo@arm.com overallMisses.subname(i, system->getMasterName(i)); 18678833Sdam.sunwoo@arm.com } 18682810SN/A 18692810SN/A // Miss latency statistics 18704022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 18714022SN/A MemCmd cmd(access_idx); 18724022SN/A const string &cstr = cmd.toString(); 18732810SN/A 18742810SN/A missLatency[access_idx] 18758833Sdam.sunwoo@arm.com .init(system->maxMasters()) 18762810SN/A .name(name() + "." + cstr + "_miss_latency") 18772810SN/A .desc("number of " + cstr + " miss cycles") 18782810SN/A .flags(total | nozero | nonan) 18792810SN/A ; 18808833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18818833Sdam.sunwoo@arm.com missLatency[access_idx].subname(i, system->getMasterName(i)); 18828833Sdam.sunwoo@arm.com } 18832810SN/A } 18842810SN/A 18852810SN/A demandMissLatency 18862810SN/A .name(name() + ".demand_miss_latency") 18872810SN/A .desc("number of demand (read+write) miss cycles") 18888833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 18892810SN/A ; 18904871SN/A demandMissLatency = SUM_DEMAND(missLatency); 18918833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18928833Sdam.sunwoo@arm.com demandMissLatency.subname(i, system->getMasterName(i)); 18938833Sdam.sunwoo@arm.com } 18942810SN/A 18952810SN/A overallMissLatency 18962810SN/A .name(name() + ".overall_miss_latency") 18972810SN/A .desc("number of overall miss cycles") 18988833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 18992810SN/A ; 19004871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 19018833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19028833Sdam.sunwoo@arm.com overallMissLatency.subname(i, system->getMasterName(i)); 19038833Sdam.sunwoo@arm.com } 19042810SN/A 19052810SN/A // access formulas 19064022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 19074022SN/A MemCmd cmd(access_idx); 19084022SN/A const string &cstr = cmd.toString(); 19092810SN/A 19102810SN/A accesses[access_idx] 19112810SN/A .name(name() + "." + cstr + "_accesses") 19122810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 19132810SN/A .flags(total | nozero | nonan) 19142810SN/A ; 19158833Sdam.sunwoo@arm.com accesses[access_idx] = hits[access_idx] + misses[access_idx]; 19162810SN/A 19178833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19188833Sdam.sunwoo@arm.com accesses[access_idx].subname(i, system->getMasterName(i)); 19198833Sdam.sunwoo@arm.com } 19202810SN/A } 19212810SN/A 19222810SN/A demandAccesses 19232810SN/A .name(name() + ".demand_accesses") 19242810SN/A .desc("number of demand (read+write) accesses") 19258833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19262810SN/A ; 19272810SN/A demandAccesses = demandHits + demandMisses; 19288833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19298833Sdam.sunwoo@arm.com demandAccesses.subname(i, system->getMasterName(i)); 19308833Sdam.sunwoo@arm.com } 19312810SN/A 19322810SN/A overallAccesses 19332810SN/A .name(name() + ".overall_accesses") 19342810SN/A .desc("number of overall (read+write) accesses") 19358833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19362810SN/A ; 19372810SN/A overallAccesses = overallHits + overallMisses; 19388833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19398833Sdam.sunwoo@arm.com overallAccesses.subname(i, system->getMasterName(i)); 19408833Sdam.sunwoo@arm.com } 19412810SN/A 19422810SN/A // miss rate formulas 19434022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 19444022SN/A MemCmd cmd(access_idx); 19454022SN/A const string &cstr = cmd.toString(); 19462810SN/A 19472810SN/A missRate[access_idx] 19482810SN/A .name(name() + "." + cstr + "_miss_rate") 19492810SN/A .desc("miss rate for " + cstr + " accesses") 19502810SN/A .flags(total | nozero | nonan) 19512810SN/A ; 19528833Sdam.sunwoo@arm.com missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 19532810SN/A 19548833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19558833Sdam.sunwoo@arm.com missRate[access_idx].subname(i, system->getMasterName(i)); 19568833Sdam.sunwoo@arm.com } 19572810SN/A } 19582810SN/A 19592810SN/A demandMissRate 19602810SN/A .name(name() + ".demand_miss_rate") 19612810SN/A .desc("miss rate for demand accesses") 19628833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19632810SN/A ; 19642810SN/A demandMissRate = demandMisses / demandAccesses; 19658833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19668833Sdam.sunwoo@arm.com demandMissRate.subname(i, system->getMasterName(i)); 19678833Sdam.sunwoo@arm.com } 19682810SN/A 19692810SN/A overallMissRate 19702810SN/A .name(name() + ".overall_miss_rate") 19712810SN/A .desc("miss rate for overall accesses") 19728833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19732810SN/A ; 19742810SN/A overallMissRate = overallMisses / overallAccesses; 19758833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19768833Sdam.sunwoo@arm.com overallMissRate.subname(i, system->getMasterName(i)); 19778833Sdam.sunwoo@arm.com } 19782810SN/A 19792810SN/A // miss latency formulas 19804022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 19814022SN/A MemCmd cmd(access_idx); 19824022SN/A const string &cstr = cmd.toString(); 19832810SN/A 19842810SN/A avgMissLatency[access_idx] 19852810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 19862810SN/A .desc("average " + cstr + " miss latency") 19872810SN/A .flags(total | nozero | nonan) 19882810SN/A ; 19892810SN/A avgMissLatency[access_idx] = 19902810SN/A missLatency[access_idx] / misses[access_idx]; 19918833Sdam.sunwoo@arm.com 19928833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19938833Sdam.sunwoo@arm.com avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 19948833Sdam.sunwoo@arm.com } 19952810SN/A } 19962810SN/A 19972810SN/A demandAvgMissLatency 19982810SN/A .name(name() + ".demand_avg_miss_latency") 19992810SN/A .desc("average overall miss latency") 20008833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 20012810SN/A ; 20022810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 20038833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20048833Sdam.sunwoo@arm.com demandAvgMissLatency.subname(i, system->getMasterName(i)); 20058833Sdam.sunwoo@arm.com } 20062810SN/A 20072810SN/A overallAvgMissLatency 20082810SN/A .name(name() + ".overall_avg_miss_latency") 20092810SN/A .desc("average overall miss latency") 20108833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 20112810SN/A ; 20122810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 20138833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20148833Sdam.sunwoo@arm.com overallAvgMissLatency.subname(i, system->getMasterName(i)); 20158833Sdam.sunwoo@arm.com } 20162810SN/A 20172810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 20182810SN/A blocked_cycles 20192810SN/A .name(name() + ".blocked_cycles") 20202810SN/A .desc("number of cycles access was blocked") 20212810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 20222810SN/A .subname(Blocked_NoTargets, "no_targets") 20232810SN/A ; 20242810SN/A 20252810SN/A 20262810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 20272810SN/A blocked_causes 20282810SN/A .name(name() + ".blocked") 20292810SN/A .desc("number of cycles access was blocked") 20302810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 20312810SN/A .subname(Blocked_NoTargets, "no_targets") 20322810SN/A ; 20332810SN/A 20342810SN/A avg_blocked 20352810SN/A .name(name() + ".avg_blocked_cycles") 20362810SN/A .desc("average number of cycles each access was blocked") 20372810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 20382810SN/A .subname(Blocked_NoTargets, "no_targets") 20392810SN/A ; 20402810SN/A 20412810SN/A avg_blocked = blocked_cycles / blocked_causes; 20422810SN/A 204311436SRekai.GonzalezAlberquilla@arm.com unusedPrefetches 204411436SRekai.GonzalezAlberquilla@arm.com .name(name() + ".unused_prefetches") 204511436SRekai.GonzalezAlberquilla@arm.com .desc("number of HardPF blocks evicted w/o reference") 204611436SRekai.GonzalezAlberquilla@arm.com .flags(nozero) 204711436SRekai.GonzalezAlberquilla@arm.com ; 204811436SRekai.GonzalezAlberquilla@arm.com 20494626SN/A writebacks 20508833Sdam.sunwoo@arm.com .init(system->maxMasters()) 20514626SN/A .name(name() + ".writebacks") 20524626SN/A .desc("number of writebacks") 20538833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 20544626SN/A ; 20558833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20568833Sdam.sunwoo@arm.com writebacks.subname(i, system->getMasterName(i)); 20578833Sdam.sunwoo@arm.com } 20584626SN/A 20594626SN/A // MSHR statistics 20604626SN/A // MSHR hit statistics 20614626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 20624626SN/A MemCmd cmd(access_idx); 20634626SN/A const string &cstr = cmd.toString(); 20644626SN/A 20654626SN/A mshr_hits[access_idx] 20668833Sdam.sunwoo@arm.com .init(system->maxMasters()) 20674626SN/A .name(name() + "." + cstr + "_mshr_hits") 20684626SN/A .desc("number of " + cstr + " MSHR hits") 20694626SN/A .flags(total | nozero | nonan) 20704626SN/A ; 20718833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20728833Sdam.sunwoo@arm.com mshr_hits[access_idx].subname(i, system->getMasterName(i)); 20738833Sdam.sunwoo@arm.com } 20744626SN/A } 20754626SN/A 20764626SN/A demandMshrHits 20774626SN/A .name(name() + ".demand_mshr_hits") 20784626SN/A .desc("number of demand (read+write) MSHR hits") 20798833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 20804626SN/A ; 20814871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 20828833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20838833Sdam.sunwoo@arm.com demandMshrHits.subname(i, system->getMasterName(i)); 20848833Sdam.sunwoo@arm.com } 20854626SN/A 20864626SN/A overallMshrHits 20874626SN/A .name(name() + ".overall_mshr_hits") 20884626SN/A .desc("number of overall MSHR hits") 20898833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 20904626SN/A ; 20914871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 20928833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20938833Sdam.sunwoo@arm.com overallMshrHits.subname(i, system->getMasterName(i)); 20948833Sdam.sunwoo@arm.com } 20954626SN/A 20964626SN/A // MSHR miss statistics 20974626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 20984626SN/A MemCmd cmd(access_idx); 20994626SN/A const string &cstr = cmd.toString(); 21004626SN/A 21014626SN/A mshr_misses[access_idx] 21028833Sdam.sunwoo@arm.com .init(system->maxMasters()) 21034626SN/A .name(name() + "." + cstr + "_mshr_misses") 21044626SN/A .desc("number of " + cstr + " MSHR misses") 21054626SN/A .flags(total | nozero | nonan) 21064626SN/A ; 21078833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21088833Sdam.sunwoo@arm.com mshr_misses[access_idx].subname(i, system->getMasterName(i)); 21098833Sdam.sunwoo@arm.com } 21104626SN/A } 21114626SN/A 21124626SN/A demandMshrMisses 21134626SN/A .name(name() + ".demand_mshr_misses") 21144626SN/A .desc("number of demand (read+write) MSHR misses") 21158833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21164626SN/A ; 21174871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 21188833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21198833Sdam.sunwoo@arm.com demandMshrMisses.subname(i, system->getMasterName(i)); 21208833Sdam.sunwoo@arm.com } 21214626SN/A 21224626SN/A overallMshrMisses 21234626SN/A .name(name() + ".overall_mshr_misses") 21244626SN/A .desc("number of overall MSHR misses") 21258833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21264626SN/A ; 21274871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 21288833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21298833Sdam.sunwoo@arm.com overallMshrMisses.subname(i, system->getMasterName(i)); 21308833Sdam.sunwoo@arm.com } 21314626SN/A 21324626SN/A // MSHR miss latency statistics 21334626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 21344626SN/A MemCmd cmd(access_idx); 21354626SN/A const string &cstr = cmd.toString(); 21364626SN/A 21374626SN/A mshr_miss_latency[access_idx] 21388833Sdam.sunwoo@arm.com .init(system->maxMasters()) 21394626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 21404626SN/A .desc("number of " + cstr + " MSHR miss cycles") 21414626SN/A .flags(total | nozero | nonan) 21424626SN/A ; 21438833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21448833Sdam.sunwoo@arm.com mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 21458833Sdam.sunwoo@arm.com } 21464626SN/A } 21474626SN/A 21484626SN/A demandMshrMissLatency 21494626SN/A .name(name() + ".demand_mshr_miss_latency") 21504626SN/A .desc("number of demand (read+write) MSHR miss cycles") 21518833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21524626SN/A ; 21534871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 21548833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21558833Sdam.sunwoo@arm.com demandMshrMissLatency.subname(i, system->getMasterName(i)); 21568833Sdam.sunwoo@arm.com } 21574626SN/A 21584626SN/A overallMshrMissLatency 21594626SN/A .name(name() + ".overall_mshr_miss_latency") 21604626SN/A .desc("number of overall MSHR miss cycles") 21618833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21624626SN/A ; 21634871SN/A overallMshrMissLatency = 21644871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 21658833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21668833Sdam.sunwoo@arm.com overallMshrMissLatency.subname(i, system->getMasterName(i)); 21678833Sdam.sunwoo@arm.com } 21684626SN/A 21694626SN/A // MSHR uncacheable statistics 21704626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 21714626SN/A MemCmd cmd(access_idx); 21724626SN/A const string &cstr = cmd.toString(); 21734626SN/A 21744626SN/A mshr_uncacheable[access_idx] 21758833Sdam.sunwoo@arm.com .init(system->maxMasters()) 21764626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 21774626SN/A .desc("number of " + cstr + " MSHR uncacheable") 21784626SN/A .flags(total | nozero | nonan) 21794626SN/A ; 21808833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21818833Sdam.sunwoo@arm.com mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 21828833Sdam.sunwoo@arm.com } 21834626SN/A } 21844626SN/A 21854626SN/A overallMshrUncacheable 21864626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 21874626SN/A .desc("number of overall MSHR uncacheable misses") 21888833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21894626SN/A ; 21904871SN/A overallMshrUncacheable = 21914871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 21928833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21938833Sdam.sunwoo@arm.com overallMshrUncacheable.subname(i, system->getMasterName(i)); 21948833Sdam.sunwoo@arm.com } 21954626SN/A 21964626SN/A // MSHR miss latency statistics 21974626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 21984626SN/A MemCmd cmd(access_idx); 21994626SN/A const string &cstr = cmd.toString(); 22004626SN/A 22014626SN/A mshr_uncacheable_lat[access_idx] 22028833Sdam.sunwoo@arm.com .init(system->maxMasters()) 22034626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 22044626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 22054626SN/A .flags(total | nozero | nonan) 22064626SN/A ; 22078833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 220811483Snikos.nikoleris@arm.com mshr_uncacheable_lat[access_idx].subname( 220911483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 22108833Sdam.sunwoo@arm.com } 22114626SN/A } 22124626SN/A 22134626SN/A overallMshrUncacheableLatency 22144626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 22154626SN/A .desc("number of overall MSHR uncacheable cycles") 22168833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 22174626SN/A ; 22184871SN/A overallMshrUncacheableLatency = 22194871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 22204871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 22218833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 22228833Sdam.sunwoo@arm.com overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 22238833Sdam.sunwoo@arm.com } 22244626SN/A 22254626SN/A#if 0 22264626SN/A // MSHR access formulas 22274626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 22284626SN/A MemCmd cmd(access_idx); 22294626SN/A const string &cstr = cmd.toString(); 22304626SN/A 22314626SN/A mshrAccesses[access_idx] 22324626SN/A .name(name() + "." + cstr + "_mshr_accesses") 22334626SN/A .desc("number of " + cstr + " mshr accesses(hits+misses)") 22344626SN/A .flags(total | nozero | nonan) 22354626SN/A ; 22364626SN/A mshrAccesses[access_idx] = 22374626SN/A mshr_hits[access_idx] + mshr_misses[access_idx] 22384626SN/A + mshr_uncacheable[access_idx]; 22394626SN/A } 22404626SN/A 22414626SN/A demandMshrAccesses 22424626SN/A .name(name() + ".demand_mshr_accesses") 22434626SN/A .desc("number of demand (read+write) mshr accesses") 22444626SN/A .flags(total | nozero | nonan) 22454626SN/A ; 22464626SN/A demandMshrAccesses = demandMshrHits + demandMshrMisses; 22474626SN/A 22484626SN/A overallMshrAccesses 22494626SN/A .name(name() + ".overall_mshr_accesses") 22504626SN/A .desc("number of overall (read+write) mshr accesses") 22514626SN/A .flags(total | nozero | nonan) 22524626SN/A ; 22534626SN/A overallMshrAccesses = overallMshrHits + overallMshrMisses 22544626SN/A + overallMshrUncacheable; 22554626SN/A#endif 22564626SN/A 22574626SN/A // MSHR miss rate formulas 22584626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 22594626SN/A MemCmd cmd(access_idx); 22604626SN/A const string &cstr = cmd.toString(); 22614626SN/A 22624626SN/A mshrMissRate[access_idx] 22634626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 22644626SN/A .desc("mshr miss rate for " + cstr + " accesses") 22654626SN/A .flags(total | nozero | nonan) 22664626SN/A ; 22674626SN/A mshrMissRate[access_idx] = 22684626SN/A mshr_misses[access_idx] / accesses[access_idx]; 22698833Sdam.sunwoo@arm.com 22708833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 22718833Sdam.sunwoo@arm.com mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 22728833Sdam.sunwoo@arm.com } 22734626SN/A } 22744626SN/A 22754626SN/A demandMshrMissRate 22764626SN/A .name(name() + ".demand_mshr_miss_rate") 22774626SN/A .desc("mshr miss rate for demand accesses") 22788833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 22794626SN/A ; 22804626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 22818833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 22828833Sdam.sunwoo@arm.com demandMshrMissRate.subname(i, system->getMasterName(i)); 22838833Sdam.sunwoo@arm.com } 22844626SN/A 22854626SN/A overallMshrMissRate 22864626SN/A .name(name() + ".overall_mshr_miss_rate") 22874626SN/A .desc("mshr miss rate for overall accesses") 22888833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 22894626SN/A ; 22904626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 22918833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 22928833Sdam.sunwoo@arm.com overallMshrMissRate.subname(i, system->getMasterName(i)); 22938833Sdam.sunwoo@arm.com } 22944626SN/A 22954626SN/A // mshrMiss latency formulas 22964626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 22974626SN/A MemCmd cmd(access_idx); 22984626SN/A const string &cstr = cmd.toString(); 22994626SN/A 23004626SN/A avgMshrMissLatency[access_idx] 23014626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 23024626SN/A .desc("average " + cstr + " mshr miss latency") 23034626SN/A .flags(total | nozero | nonan) 23044626SN/A ; 23054626SN/A avgMshrMissLatency[access_idx] = 23064626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 23078833Sdam.sunwoo@arm.com 23088833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 230911483Snikos.nikoleris@arm.com avgMshrMissLatency[access_idx].subname( 231011483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 23118833Sdam.sunwoo@arm.com } 23124626SN/A } 23134626SN/A 23144626SN/A demandAvgMshrMissLatency 23154626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 23164626SN/A .desc("average overall mshr miss latency") 23178833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 23184626SN/A ; 23194626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 23208833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 23218833Sdam.sunwoo@arm.com demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 23228833Sdam.sunwoo@arm.com } 23234626SN/A 23244626SN/A overallAvgMshrMissLatency 23254626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 23264626SN/A .desc("average overall mshr miss latency") 23278833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 23284626SN/A ; 23294626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 23308833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 23318833Sdam.sunwoo@arm.com overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 23328833Sdam.sunwoo@arm.com } 23334626SN/A 23344626SN/A // mshrUncacheable latency formulas 23354626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 23364626SN/A MemCmd cmd(access_idx); 23374626SN/A const string &cstr = cmd.toString(); 23384626SN/A 23394626SN/A avgMshrUncacheableLatency[access_idx] 23404626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 23414626SN/A .desc("average " + cstr + " mshr uncacheable latency") 23424626SN/A .flags(total | nozero | nonan) 23434626SN/A ; 23444626SN/A avgMshrUncacheableLatency[access_idx] = 23454626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 23468833Sdam.sunwoo@arm.com 23478833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 234811483Snikos.nikoleris@arm.com avgMshrUncacheableLatency[access_idx].subname( 234911483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 23508833Sdam.sunwoo@arm.com } 23514626SN/A } 23524626SN/A 23534626SN/A overallAvgMshrUncacheableLatency 23544626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 23554626SN/A .desc("average overall mshr uncacheable latency") 23568833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 23574626SN/A ; 235811483Snikos.nikoleris@arm.com overallAvgMshrUncacheableLatency = 235911483Snikos.nikoleris@arm.com overallMshrUncacheableLatency / overallMshrUncacheable; 23608833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 23618833Sdam.sunwoo@arm.com overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 23628833Sdam.sunwoo@arm.com } 23634626SN/A 236412702Snikos.nikoleris@arm.com replacements 236512702Snikos.nikoleris@arm.com .name(name() + ".replacements") 236612702Snikos.nikoleris@arm.com .desc("number of replacements") 236712702Snikos.nikoleris@arm.com ; 23682810SN/A} 236912724Snikos.nikoleris@arm.com 237013416Sjavier.bueno@metempsy.comvoid 237113416Sjavier.bueno@metempsy.comBaseCache::regProbePoints() 237213416Sjavier.bueno@metempsy.com{ 237313416Sjavier.bueno@metempsy.com ppHit = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Hit"); 237413416Sjavier.bueno@metempsy.com ppMiss = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Miss"); 237513717Sivan.pizarro@metempsy.com ppFill = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Fill"); 237613416Sjavier.bueno@metempsy.com} 237713416Sjavier.bueno@metempsy.com 237812724Snikos.nikoleris@arm.com/////////////// 237912724Snikos.nikoleris@arm.com// 238012724Snikos.nikoleris@arm.com// CpuSidePort 238112724Snikos.nikoleris@arm.com// 238212724Snikos.nikoleris@arm.com/////////////// 238312724Snikos.nikoleris@arm.combool 238412724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 238512724Snikos.nikoleris@arm.com{ 238612725Snikos.nikoleris@arm.com // Snoops shouldn't happen when bypassing caches 238712725Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 238812725Snikos.nikoleris@arm.com 238912725Snikos.nikoleris@arm.com assert(pkt->isResponse()); 239012725Snikos.nikoleris@arm.com 239112724Snikos.nikoleris@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 239212724Snikos.nikoleris@arm.com cache->recvTimingSnoopResp(pkt); 239312724Snikos.nikoleris@arm.com return true; 239412724Snikos.nikoleris@arm.com} 239512724Snikos.nikoleris@arm.com 239612724Snikos.nikoleris@arm.com 239712724Snikos.nikoleris@arm.combool 239812724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::tryTiming(PacketPtr pkt) 239912724Snikos.nikoleris@arm.com{ 240012725Snikos.nikoleris@arm.com if (cache->system->bypassCaches() || pkt->isExpressSnoop()) { 240112724Snikos.nikoleris@arm.com // always let express snoop packets through even if blocked 240212724Snikos.nikoleris@arm.com return true; 240312724Snikos.nikoleris@arm.com } else if (blocked || mustSendRetry) { 240412724Snikos.nikoleris@arm.com // either already committed to send a retry, or blocked 240512724Snikos.nikoleris@arm.com mustSendRetry = true; 240612724Snikos.nikoleris@arm.com return false; 240712724Snikos.nikoleris@arm.com } 240812724Snikos.nikoleris@arm.com mustSendRetry = false; 240912724Snikos.nikoleris@arm.com return true; 241012724Snikos.nikoleris@arm.com} 241112724Snikos.nikoleris@arm.com 241212724Snikos.nikoleris@arm.combool 241312724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 241412724Snikos.nikoleris@arm.com{ 241512725Snikos.nikoleris@arm.com assert(pkt->isRequest()); 241612725Snikos.nikoleris@arm.com 241712725Snikos.nikoleris@arm.com if (cache->system->bypassCaches()) { 241812725Snikos.nikoleris@arm.com // Just forward the packet if caches are disabled. 241912725Snikos.nikoleris@arm.com // @todo This should really enqueue the packet rather 242012725Snikos.nikoleris@arm.com bool M5_VAR_USED success = cache->memSidePort.sendTimingReq(pkt); 242112725Snikos.nikoleris@arm.com assert(success); 242212725Snikos.nikoleris@arm.com return true; 242312725Snikos.nikoleris@arm.com } else if (tryTiming(pkt)) { 242412724Snikos.nikoleris@arm.com cache->recvTimingReq(pkt); 242512724Snikos.nikoleris@arm.com return true; 242612724Snikos.nikoleris@arm.com } 242712724Snikos.nikoleris@arm.com return false; 242812724Snikos.nikoleris@arm.com} 242912724Snikos.nikoleris@arm.com 243012724Snikos.nikoleris@arm.comTick 243112724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvAtomic(PacketPtr pkt) 243212724Snikos.nikoleris@arm.com{ 243312725Snikos.nikoleris@arm.com if (cache->system->bypassCaches()) { 243412725Snikos.nikoleris@arm.com // Forward the request if the system is in cache bypass mode. 243512725Snikos.nikoleris@arm.com return cache->memSidePort.sendAtomic(pkt); 243612725Snikos.nikoleris@arm.com } else { 243712725Snikos.nikoleris@arm.com return cache->recvAtomic(pkt); 243812725Snikos.nikoleris@arm.com } 243912724Snikos.nikoleris@arm.com} 244012724Snikos.nikoleris@arm.com 244112724Snikos.nikoleris@arm.comvoid 244212724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvFunctional(PacketPtr pkt) 244312724Snikos.nikoleris@arm.com{ 244412725Snikos.nikoleris@arm.com if (cache->system->bypassCaches()) { 244512725Snikos.nikoleris@arm.com // The cache should be flushed if we are in cache bypass mode, 244612725Snikos.nikoleris@arm.com // so we don't need to check if we need to update anything. 244712725Snikos.nikoleris@arm.com cache->memSidePort.sendFunctional(pkt); 244812725Snikos.nikoleris@arm.com return; 244912725Snikos.nikoleris@arm.com } 245012725Snikos.nikoleris@arm.com 245112724Snikos.nikoleris@arm.com // functional request 245212724Snikos.nikoleris@arm.com cache->functionalAccess(pkt, true); 245312724Snikos.nikoleris@arm.com} 245412724Snikos.nikoleris@arm.com 245512724Snikos.nikoleris@arm.comAddrRangeList 245612724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::getAddrRanges() const 245712724Snikos.nikoleris@arm.com{ 245812724Snikos.nikoleris@arm.com return cache->getAddrRanges(); 245912724Snikos.nikoleris@arm.com} 246012724Snikos.nikoleris@arm.com 246112724Snikos.nikoleris@arm.com 246212724Snikos.nikoleris@arm.comBaseCache:: 246312724Snikos.nikoleris@arm.comCpuSidePort::CpuSidePort(const std::string &_name, BaseCache *_cache, 246412724Snikos.nikoleris@arm.com const std::string &_label) 246512724Snikos.nikoleris@arm.com : CacheSlavePort(_name, _cache, _label), cache(_cache) 246612724Snikos.nikoleris@arm.com{ 246712724Snikos.nikoleris@arm.com} 246812724Snikos.nikoleris@arm.com 246912724Snikos.nikoleris@arm.com/////////////// 247012724Snikos.nikoleris@arm.com// 247112724Snikos.nikoleris@arm.com// MemSidePort 247212724Snikos.nikoleris@arm.com// 247312724Snikos.nikoleris@arm.com/////////////// 247412724Snikos.nikoleris@arm.combool 247512724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvTimingResp(PacketPtr pkt) 247612724Snikos.nikoleris@arm.com{ 247712724Snikos.nikoleris@arm.com cache->recvTimingResp(pkt); 247812724Snikos.nikoleris@arm.com return true; 247912724Snikos.nikoleris@arm.com} 248012724Snikos.nikoleris@arm.com 248112724Snikos.nikoleris@arm.com// Express snooping requests to memside port 248212724Snikos.nikoleris@arm.comvoid 248312724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 248412724Snikos.nikoleris@arm.com{ 248512725Snikos.nikoleris@arm.com // Snoops shouldn't happen when bypassing caches 248612725Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 248712725Snikos.nikoleris@arm.com 248812724Snikos.nikoleris@arm.com // handle snooping requests 248912724Snikos.nikoleris@arm.com cache->recvTimingSnoopReq(pkt); 249012724Snikos.nikoleris@arm.com} 249112724Snikos.nikoleris@arm.com 249212724Snikos.nikoleris@arm.comTick 249312724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 249412724Snikos.nikoleris@arm.com{ 249512725Snikos.nikoleris@arm.com // Snoops shouldn't happen when bypassing caches 249612725Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 249712725Snikos.nikoleris@arm.com 249812724Snikos.nikoleris@arm.com return cache->recvAtomicSnoop(pkt); 249912724Snikos.nikoleris@arm.com} 250012724Snikos.nikoleris@arm.com 250112724Snikos.nikoleris@arm.comvoid 250212724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 250312724Snikos.nikoleris@arm.com{ 250412725Snikos.nikoleris@arm.com // Snoops shouldn't happen when bypassing caches 250512725Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 250612725Snikos.nikoleris@arm.com 250712724Snikos.nikoleris@arm.com // functional snoop (note that in contrast to atomic we don't have 250812724Snikos.nikoleris@arm.com // a specific functionalSnoop method, as they have the same 250912724Snikos.nikoleris@arm.com // behaviour regardless) 251012724Snikos.nikoleris@arm.com cache->functionalAccess(pkt, false); 251112724Snikos.nikoleris@arm.com} 251212724Snikos.nikoleris@arm.com 251312724Snikos.nikoleris@arm.comvoid 251412724Snikos.nikoleris@arm.comBaseCache::CacheReqPacketQueue::sendDeferredPacket() 251512724Snikos.nikoleris@arm.com{ 251612724Snikos.nikoleris@arm.com // sanity check 251712724Snikos.nikoleris@arm.com assert(!waitingOnRetry); 251812724Snikos.nikoleris@arm.com 251912724Snikos.nikoleris@arm.com // there should never be any deferred request packets in the 252012724Snikos.nikoleris@arm.com // queue, instead we resly on the cache to provide the packets 252112724Snikos.nikoleris@arm.com // from the MSHR queue or write queue 252212724Snikos.nikoleris@arm.com assert(deferredPacketReadyTime() == MaxTick); 252312724Snikos.nikoleris@arm.com 252412724Snikos.nikoleris@arm.com // check for request packets (requests & writebacks) 252512724Snikos.nikoleris@arm.com QueueEntry* entry = cache.getNextQueueEntry(); 252612724Snikos.nikoleris@arm.com 252712724Snikos.nikoleris@arm.com if (!entry) { 252812724Snikos.nikoleris@arm.com // can happen if e.g. we attempt a writeback and fail, but 252912724Snikos.nikoleris@arm.com // before the retry, the writeback is eliminated because 253012724Snikos.nikoleris@arm.com // we snoop another cache's ReadEx. 253112724Snikos.nikoleris@arm.com } else { 253212724Snikos.nikoleris@arm.com // let our snoop responses go first if there are responses to 253312724Snikos.nikoleris@arm.com // the same addresses 253413860Sodanrc@yahoo.com.br if (checkConflictingSnoop(entry->getTarget()->pkt)) { 253512724Snikos.nikoleris@arm.com return; 253612724Snikos.nikoleris@arm.com } 253712724Snikos.nikoleris@arm.com waitingOnRetry = entry->sendPacket(cache); 253812724Snikos.nikoleris@arm.com } 253912724Snikos.nikoleris@arm.com 254012724Snikos.nikoleris@arm.com // if we succeeded and are not waiting for a retry, schedule the 254112724Snikos.nikoleris@arm.com // next send considering when the next queue is ready, note that 254212724Snikos.nikoleris@arm.com // snoop responses have their own packet queue and thus schedule 254312724Snikos.nikoleris@arm.com // their own events 254412724Snikos.nikoleris@arm.com if (!waitingOnRetry) { 254512724Snikos.nikoleris@arm.com schedSendEvent(cache.nextQueueReadyTime()); 254612724Snikos.nikoleris@arm.com } 254712724Snikos.nikoleris@arm.com} 254812724Snikos.nikoleris@arm.com 254912724Snikos.nikoleris@arm.comBaseCache::MemSidePort::MemSidePort(const std::string &_name, 255012724Snikos.nikoleris@arm.com BaseCache *_cache, 255112724Snikos.nikoleris@arm.com const std::string &_label) 255212724Snikos.nikoleris@arm.com : CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 255312724Snikos.nikoleris@arm.com _reqQueue(*_cache, *this, _snoopRespQueue, _label), 255413564Snikos.nikoleris@arm.com _snoopRespQueue(*_cache, *this, true, _label), cache(_cache) 255512724Snikos.nikoleris@arm.com{ 255612724Snikos.nikoleris@arm.com} 255713352Snikos.nikoleris@arm.com 255813352Snikos.nikoleris@arm.comvoid 255913352Snikos.nikoleris@arm.comWriteAllocator::updateMode(Addr write_addr, unsigned write_size, 256013352Snikos.nikoleris@arm.com Addr blk_addr) 256113352Snikos.nikoleris@arm.com{ 256213352Snikos.nikoleris@arm.com // check if we are continuing where the last write ended 256313352Snikos.nikoleris@arm.com if (nextAddr == write_addr) { 256413352Snikos.nikoleris@arm.com delayCtr[blk_addr] = delayThreshold; 256513352Snikos.nikoleris@arm.com // stop if we have already saturated 256613352Snikos.nikoleris@arm.com if (mode != WriteMode::NO_ALLOCATE) { 256713352Snikos.nikoleris@arm.com byteCount += write_size; 256813352Snikos.nikoleris@arm.com // switch to streaming mode if we have passed the lower 256913352Snikos.nikoleris@arm.com // threshold 257013352Snikos.nikoleris@arm.com if (mode == WriteMode::ALLOCATE && 257113352Snikos.nikoleris@arm.com byteCount > coalesceLimit) { 257213352Snikos.nikoleris@arm.com mode = WriteMode::COALESCE; 257313352Snikos.nikoleris@arm.com DPRINTF(Cache, "Switched to write coalescing\n"); 257413352Snikos.nikoleris@arm.com } else if (mode == WriteMode::COALESCE && 257513352Snikos.nikoleris@arm.com byteCount > noAllocateLimit) { 257613352Snikos.nikoleris@arm.com // and continue and switch to non-allocating mode if we 257713352Snikos.nikoleris@arm.com // pass the upper threshold 257813352Snikos.nikoleris@arm.com mode = WriteMode::NO_ALLOCATE; 257913352Snikos.nikoleris@arm.com DPRINTF(Cache, "Switched to write-no-allocate\n"); 258013352Snikos.nikoleris@arm.com } 258113352Snikos.nikoleris@arm.com } 258213352Snikos.nikoleris@arm.com } else { 258313352Snikos.nikoleris@arm.com // we did not see a write matching the previous one, start 258413352Snikos.nikoleris@arm.com // over again 258513352Snikos.nikoleris@arm.com byteCount = write_size; 258613352Snikos.nikoleris@arm.com mode = WriteMode::ALLOCATE; 258713352Snikos.nikoleris@arm.com resetDelay(blk_addr); 258813352Snikos.nikoleris@arm.com } 258913352Snikos.nikoleris@arm.com nextAddr = write_addr + write_size; 259013352Snikos.nikoleris@arm.com} 259113352Snikos.nikoleris@arm.com 259213352Snikos.nikoleris@arm.comWriteAllocator* 259313352Snikos.nikoleris@arm.comWriteAllocatorParams::create() 259413352Snikos.nikoleris@arm.com{ 259513352Snikos.nikoleris@arm.com return new WriteAllocator(this); 259613352Snikos.nikoleris@arm.com} 2597