base.cc revision 13419
12810SN/A/*
212724Snikos.nikoleris@arm.com * Copyright (c) 2012-2013, 2018 ARM Limited
38856Sandreas.hansson@arm.com * All rights reserved.
48856Sandreas.hansson@arm.com *
58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall
68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual
78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating
88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software
98856Sandreas.hansson@arm.com * licensed hereunder.  You may use the software subject to the license
108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated
118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software,
128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form.
138856Sandreas.hansson@arm.com *
142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
152810SN/A * All rights reserved.
162810SN/A *
172810SN/A * Redistribution and use in source and binary forms, with or without
182810SN/A * modification, are permitted provided that the following conditions are
192810SN/A * met: redistributions of source code must retain the above copyright
202810SN/A * notice, this list of conditions and the following disclaimer;
212810SN/A * redistributions in binary form must reproduce the above copyright
222810SN/A * notice, this list of conditions and the following disclaimer in the
232810SN/A * documentation and/or other materials provided with the distribution;
242810SN/A * neither the name of the copyright holders nor the names of its
252810SN/A * contributors may be used to endorse or promote products derived from
262810SN/A * this software without specific prior written permission.
272810SN/A *
282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392810SN/A *
402810SN/A * Authors: Erik Hallnor
4112724Snikos.nikoleris@arm.com *          Nikos Nikoleris
422810SN/A */
432810SN/A
442810SN/A/**
452810SN/A * @file
462810SN/A * Definition of BaseCache functions.
472810SN/A */
482810SN/A
4911486Snikos.nikoleris@arm.com#include "mem/cache/base.hh"
5011486Snikos.nikoleris@arm.com
5112724Snikos.nikoleris@arm.com#include "base/compiler.hh"
5212724Snikos.nikoleris@arm.com#include "base/logging.hh"
538232Snate@binkert.org#include "debug/Cache.hh"
5412724Snikos.nikoleris@arm.com#include "debug/CachePort.hh"
5513222Sodanrc@yahoo.com.br#include "debug/CacheRepl.hh"
5612724Snikos.nikoleris@arm.com#include "debug/CacheVerbose.hh"
5711486Snikos.nikoleris@arm.com#include "mem/cache/mshr.hh"
5812724Snikos.nikoleris@arm.com#include "mem/cache/prefetch/base.hh"
5912724Snikos.nikoleris@arm.com#include "mem/cache/queue_entry.hh"
6012724Snikos.nikoleris@arm.com#include "params/BaseCache.hh"
6113352Snikos.nikoleris@arm.com#include "params/WriteAllocator.hh"
6212724Snikos.nikoleris@arm.com#include "sim/core.hh"
6312724Snikos.nikoleris@arm.com
6412724Snikos.nikoleris@arm.comclass BaseMasterPort;
6512724Snikos.nikoleris@arm.comclass BaseSlavePort;
662810SN/A
672810SN/Ausing namespace std;
682810SN/A
698856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
708856Sandreas.hansson@arm.com                                          BaseCache *_cache,
718856Sandreas.hansson@arm.com                                          const std::string &_label)
728922Swilliam.wang@arm.com    : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label),
7312084Sspwilson2@wisc.edu      blocked(false), mustSendRetry(false),
7412084Sspwilson2@wisc.edu      sendRetryEvent([this]{ processSendRetry(); }, _name)
758856Sandreas.hansson@arm.com{
768856Sandreas.hansson@arm.com}
774475SN/A
7811053Sandreas.hansson@arm.comBaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
795034SN/A    : MemObject(p),
8012724Snikos.nikoleris@arm.com      cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"),
8112724Snikos.nikoleris@arm.com      memSidePort(p->name + ".mem_side", this, "MemSidePort"),
8211377Sandreas.hansson@arm.com      mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below
8311377Sandreas.hansson@arm.com      writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below
8412724Snikos.nikoleris@arm.com      tags(p->tags),
8512724Snikos.nikoleris@arm.com      prefetcher(p->prefetcher),
8613352Snikos.nikoleris@arm.com      writeAllocator(p->write_allocator),
8712724Snikos.nikoleris@arm.com      writebackClean(p->writeback_clean),
8812724Snikos.nikoleris@arm.com      tempBlockWriteback(nullptr),
8912724Snikos.nikoleris@arm.com      writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); },
9012724Snikos.nikoleris@arm.com                                    name(), false,
9112724Snikos.nikoleris@arm.com                                    EventBase::Delayed_Writeback_Pri),
9211053Sandreas.hansson@arm.com      blkSize(blk_size),
9311722Ssophiane.senni@gmail.com      lookupLatency(p->tag_latency),
9411722Ssophiane.senni@gmail.com      dataLatency(p->data_latency),
9511722Ssophiane.senni@gmail.com      forwardLatency(p->tag_latency),
9611722Ssophiane.senni@gmail.com      fillLatency(p->data_latency),
979263Smrinmoy.ghosh@arm.com      responseLatency(p->response_latency),
9813418Sodanrc@yahoo.com.br      sequentialAccess(p->sequential_access),
995034SN/A      numTarget(p->tgts_per_mshr),
10011331Sandreas.hansson@arm.com      forwardSnoops(true),
10112724Snikos.nikoleris@arm.com      clusivity(p->clusivity),
10210884Sandreas.hansson@arm.com      isReadOnly(p->is_read_only),
1034626SN/A      blocked(0),
10410360Sandreas.hansson@arm.com      order(0),
10511484Snikos.nikoleris@arm.com      noTargetMSHR(nullptr),
1065034SN/A      missCount(p->max_miss_count),
1078883SAli.Saidi@ARM.com      addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
1088833Sdam.sunwoo@arm.com      system(p->system)
1094458SN/A{
11011377Sandreas.hansson@arm.com    // the MSHR queue has no reserve entries as we check the MSHR
11111377Sandreas.hansson@arm.com    // queue on every single allocation, whereas the write queue has
11211377Sandreas.hansson@arm.com    // as many reserve entries as we have MSHRs, since every MSHR may
11311377Sandreas.hansson@arm.com    // eventually require a writeback, and we do not check the write
11411377Sandreas.hansson@arm.com    // buffer before committing to an MSHR
11511377Sandreas.hansson@arm.com
11611331Sandreas.hansson@arm.com    // forward snoops is overridden in init() once we can query
11711331Sandreas.hansson@arm.com    // whether the connected master is actually snooping or not
11812724Snikos.nikoleris@arm.com
11912843Srmk35@cl.cam.ac.uk    tempBlock = new TempCacheBlk(blkSize);
12012724Snikos.nikoleris@arm.com
12113419Sodanrc@yahoo.com.br    tags->tagsInit();
12212724Snikos.nikoleris@arm.com    if (prefetcher)
12312724Snikos.nikoleris@arm.com        prefetcher->setCache(this);
12412724Snikos.nikoleris@arm.com}
12512724Snikos.nikoleris@arm.com
12612724Snikos.nikoleris@arm.comBaseCache::~BaseCache()
12712724Snikos.nikoleris@arm.com{
12812724Snikos.nikoleris@arm.com    delete tempBlock;
1292810SN/A}
1302810SN/A
1313013SN/Avoid
1328856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::setBlocked()
1332810SN/A{
1343013SN/A    assert(!blocked);
13510714Sandreas.hansson@arm.com    DPRINTF(CachePort, "Port is blocking new requests\n");
1362810SN/A    blocked = true;
1379614Srene.dejong@arm.com    // if we already scheduled a retry in this cycle, but it has not yet
1389614Srene.dejong@arm.com    // happened, cancel it
1399614Srene.dejong@arm.com    if (sendRetryEvent.scheduled()) {
14010345SCurtis.Dunham@arm.com        owner.deschedule(sendRetryEvent);
14110714Sandreas.hansson@arm.com        DPRINTF(CachePort, "Port descheduled retry\n");
14210345SCurtis.Dunham@arm.com        mustSendRetry = true;
1439614Srene.dejong@arm.com    }
1442810SN/A}
1452810SN/A
1462810SN/Avoid
1478856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::clearBlocked()
1482810SN/A{
1493013SN/A    assert(blocked);
15010714Sandreas.hansson@arm.com    DPRINTF(CachePort, "Port is accepting new requests\n");
1513013SN/A    blocked = false;
1528856Sandreas.hansson@arm.com    if (mustSendRetry) {
15310714Sandreas.hansson@arm.com        // @TODO: need to find a better time (next cycle?)
1548922Swilliam.wang@arm.com        owner.schedule(sendRetryEvent, curTick() + 1);
1552897SN/A    }
1562810SN/A}
1572810SN/A
15810344Sandreas.hansson@arm.comvoid
15910344Sandreas.hansson@arm.comBaseCache::CacheSlavePort::processSendRetry()
16010344Sandreas.hansson@arm.com{
16110714Sandreas.hansson@arm.com    DPRINTF(CachePort, "Port is sending retry\n");
16210344Sandreas.hansson@arm.com
16310344Sandreas.hansson@arm.com    // reset the flag and call retry
16410344Sandreas.hansson@arm.com    mustSendRetry = false;
16510713Sandreas.hansson@arm.com    sendRetryReq();
16610344Sandreas.hansson@arm.com}
1672844SN/A
16812730Sodanrc@yahoo.com.brAddr
16912730Sodanrc@yahoo.com.brBaseCache::regenerateBlkAddr(CacheBlk* blk)
17012730Sodanrc@yahoo.com.br{
17112730Sodanrc@yahoo.com.br    if (blk != tempBlock) {
17212730Sodanrc@yahoo.com.br        return tags->regenerateBlkAddr(blk);
17312730Sodanrc@yahoo.com.br    } else {
17412730Sodanrc@yahoo.com.br        return tempBlock->getAddr();
17512730Sodanrc@yahoo.com.br    }
17612730Sodanrc@yahoo.com.br}
17712730Sodanrc@yahoo.com.br
1782810SN/Avoid
1792858SN/ABaseCache::init()
1802858SN/A{
18112724Snikos.nikoleris@arm.com    if (!cpuSidePort.isConnected() || !memSidePort.isConnected())
1828922Swilliam.wang@arm.com        fatal("Cache ports on %s are not connected\n", name());
18312724Snikos.nikoleris@arm.com    cpuSidePort.sendRangeChange();
18412724Snikos.nikoleris@arm.com    forwardSnoops = cpuSidePort.isSnooping();
1852858SN/A}
1862858SN/A
1879294Sandreas.hansson@arm.comBaseMasterPort &
1889294Sandreas.hansson@arm.comBaseCache::getMasterPort(const std::string &if_name, PortID idx)
1898922Swilliam.wang@arm.com{
1908922Swilliam.wang@arm.com    if (if_name == "mem_side") {
19112724Snikos.nikoleris@arm.com        return memSidePort;
1928922Swilliam.wang@arm.com    }  else {
1938922Swilliam.wang@arm.com        return MemObject::getMasterPort(if_name, idx);
1948922Swilliam.wang@arm.com    }
1958922Swilliam.wang@arm.com}
1968922Swilliam.wang@arm.com
1979294Sandreas.hansson@arm.comBaseSlavePort &
1989294Sandreas.hansson@arm.comBaseCache::getSlavePort(const std::string &if_name, PortID idx)
1998922Swilliam.wang@arm.com{
2008922Swilliam.wang@arm.com    if (if_name == "cpu_side") {
20112724Snikos.nikoleris@arm.com        return cpuSidePort;
2028922Swilliam.wang@arm.com    } else {
2038922Swilliam.wang@arm.com        return MemObject::getSlavePort(if_name, idx);
2048922Swilliam.wang@arm.com    }
2058922Swilliam.wang@arm.com}
2064628SN/A
20710821Sandreas.hansson@arm.combool
20810821Sandreas.hansson@arm.comBaseCache::inRange(Addr addr) const
20910821Sandreas.hansson@arm.com{
21010821Sandreas.hansson@arm.com    for (const auto& r : addrRanges) {
21110821Sandreas.hansson@arm.com        if (r.contains(addr)) {
21210821Sandreas.hansson@arm.com            return true;
21310821Sandreas.hansson@arm.com       }
21410821Sandreas.hansson@arm.com    }
21510821Sandreas.hansson@arm.com    return false;
21610821Sandreas.hansson@arm.com}
21710821Sandreas.hansson@arm.com
2182858SN/Avoid
21912724Snikos.nikoleris@arm.comBaseCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time)
22012724Snikos.nikoleris@arm.com{
22112724Snikos.nikoleris@arm.com    if (pkt->needsResponse()) {
22212724Snikos.nikoleris@arm.com        pkt->makeTimingResponse();
22312724Snikos.nikoleris@arm.com        // @todo: Make someone pay for this
22412724Snikos.nikoleris@arm.com        pkt->headerDelay = pkt->payloadDelay = 0;
22512724Snikos.nikoleris@arm.com
22612724Snikos.nikoleris@arm.com        // In this case we are considering request_time that takes
22712724Snikos.nikoleris@arm.com        // into account the delay of the xbar, if any, and just
22812724Snikos.nikoleris@arm.com        // lat, neglecting responseLatency, modelling hit latency
22913418Sodanrc@yahoo.com.br        // just as the value of lat overriden by access(), which calls
23013418Sodanrc@yahoo.com.br        // the calculateAccessLatency() function.
23112724Snikos.nikoleris@arm.com        cpuSidePort.schedTimingResp(pkt, request_time, true);
23212724Snikos.nikoleris@arm.com    } else {
23312724Snikos.nikoleris@arm.com        DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__,
23412724Snikos.nikoleris@arm.com                pkt->print());
23512724Snikos.nikoleris@arm.com
23612724Snikos.nikoleris@arm.com        // queue the packet for deletion, as the sending cache is
23712724Snikos.nikoleris@arm.com        // still relying on it; if the block is found in access(),
23812724Snikos.nikoleris@arm.com        // CleanEvict and Writeback messages will be deleted
23912724Snikos.nikoleris@arm.com        // here as well
24012724Snikos.nikoleris@arm.com        pendingDelete.reset(pkt);
24112724Snikos.nikoleris@arm.com    }
24212724Snikos.nikoleris@arm.com}
24312724Snikos.nikoleris@arm.com
24412724Snikos.nikoleris@arm.comvoid
24512724Snikos.nikoleris@arm.comBaseCache::handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk,
24612724Snikos.nikoleris@arm.com                               Tick forward_time, Tick request_time)
24712724Snikos.nikoleris@arm.com{
24813352Snikos.nikoleris@arm.com    if (writeAllocator &&
24913352Snikos.nikoleris@arm.com        pkt && pkt->isWrite() && !pkt->req->isUncacheable()) {
25013352Snikos.nikoleris@arm.com        writeAllocator->updateMode(pkt->getAddr(), pkt->getSize(),
25113352Snikos.nikoleris@arm.com                                   pkt->getBlockAddr(blkSize));
25213352Snikos.nikoleris@arm.com    }
25313352Snikos.nikoleris@arm.com
25412724Snikos.nikoleris@arm.com    if (mshr) {
25512724Snikos.nikoleris@arm.com        /// MSHR hit
25612724Snikos.nikoleris@arm.com        /// @note writebacks will be checked in getNextMSHR()
25712724Snikos.nikoleris@arm.com        /// for any conflicting requests to the same block
25812724Snikos.nikoleris@arm.com
25912724Snikos.nikoleris@arm.com        //@todo remove hw_pf here
26012724Snikos.nikoleris@arm.com
26112724Snikos.nikoleris@arm.com        // Coalesce unless it was a software prefetch (see above).
26212724Snikos.nikoleris@arm.com        if (pkt) {
26312724Snikos.nikoleris@arm.com            assert(!pkt->isWriteback());
26412724Snikos.nikoleris@arm.com            // CleanEvicts corresponding to blocks which have
26512724Snikos.nikoleris@arm.com            // outstanding requests in MSHRs are simply sunk here
26612724Snikos.nikoleris@arm.com            if (pkt->cmd == MemCmd::CleanEvict) {
26712724Snikos.nikoleris@arm.com                pendingDelete.reset(pkt);
26812724Snikos.nikoleris@arm.com            } else if (pkt->cmd == MemCmd::WriteClean) {
26912724Snikos.nikoleris@arm.com                // A WriteClean should never coalesce with any
27012724Snikos.nikoleris@arm.com                // outstanding cache maintenance requests.
27112724Snikos.nikoleris@arm.com
27212724Snikos.nikoleris@arm.com                // We use forward_time here because there is an
27312724Snikos.nikoleris@arm.com                // uncached memory write, forwarded to WriteBuffer.
27412724Snikos.nikoleris@arm.com                allocateWriteBuffer(pkt, forward_time);
27512724Snikos.nikoleris@arm.com            } else {
27612724Snikos.nikoleris@arm.com                DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__,
27712724Snikos.nikoleris@arm.com                        pkt->print());
27812724Snikos.nikoleris@arm.com
27912724Snikos.nikoleris@arm.com                assert(pkt->req->masterId() < system->maxMasters());
28012724Snikos.nikoleris@arm.com                mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
28112724Snikos.nikoleris@arm.com
28212724Snikos.nikoleris@arm.com                // We use forward_time here because it is the same
28312724Snikos.nikoleris@arm.com                // considering new targets. We have multiple
28412724Snikos.nikoleris@arm.com                // requests for the same address here. It
28512724Snikos.nikoleris@arm.com                // specifies the latency to allocate an internal
28612724Snikos.nikoleris@arm.com                // buffer and to schedule an event to the queued
28712724Snikos.nikoleris@arm.com                // port and also takes into account the additional
28812724Snikos.nikoleris@arm.com                // delay of the xbar.
28912724Snikos.nikoleris@arm.com                mshr->allocateTarget(pkt, forward_time, order++,
29012724Snikos.nikoleris@arm.com                                     allocOnFill(pkt->cmd));
29112724Snikos.nikoleris@arm.com                if (mshr->getNumTargets() == numTarget) {
29212724Snikos.nikoleris@arm.com                    noTargetMSHR = mshr;
29312724Snikos.nikoleris@arm.com                    setBlocked(Blocked_NoTargets);
29412724Snikos.nikoleris@arm.com                    // need to be careful with this... if this mshr isn't
29512724Snikos.nikoleris@arm.com                    // ready yet (i.e. time > curTick()), we don't want to
29612724Snikos.nikoleris@arm.com                    // move it ahead of mshrs that are ready
29712724Snikos.nikoleris@arm.com                    // mshrQueue.moveToFront(mshr);
29812724Snikos.nikoleris@arm.com                }
29912724Snikos.nikoleris@arm.com            }
30012724Snikos.nikoleris@arm.com        }
30112724Snikos.nikoleris@arm.com    } else {
30212724Snikos.nikoleris@arm.com        // no MSHR
30312724Snikos.nikoleris@arm.com        assert(pkt->req->masterId() < system->maxMasters());
30412724Snikos.nikoleris@arm.com        mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
30512724Snikos.nikoleris@arm.com
30612724Snikos.nikoleris@arm.com        if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean) {
30712724Snikos.nikoleris@arm.com            // We use forward_time here because there is an
30812724Snikos.nikoleris@arm.com            // writeback or writeclean, forwarded to WriteBuffer.
30912724Snikos.nikoleris@arm.com            allocateWriteBuffer(pkt, forward_time);
31012724Snikos.nikoleris@arm.com        } else {
31112724Snikos.nikoleris@arm.com            if (blk && blk->isValid()) {
31212724Snikos.nikoleris@arm.com                // If we have a write miss to a valid block, we
31312724Snikos.nikoleris@arm.com                // need to mark the block non-readable.  Otherwise
31412724Snikos.nikoleris@arm.com                // if we allow reads while there's an outstanding
31512724Snikos.nikoleris@arm.com                // write miss, the read could return stale data
31612724Snikos.nikoleris@arm.com                // out of the cache block... a more aggressive
31712724Snikos.nikoleris@arm.com                // system could detect the overlap (if any) and
31812724Snikos.nikoleris@arm.com                // forward data out of the MSHRs, but we don't do
31912724Snikos.nikoleris@arm.com                // that yet.  Note that we do need to leave the
32012724Snikos.nikoleris@arm.com                // block valid so that it stays in the cache, in
32112724Snikos.nikoleris@arm.com                // case we get an upgrade response (and hence no
32212724Snikos.nikoleris@arm.com                // new data) when the write miss completes.
32312724Snikos.nikoleris@arm.com                // As long as CPUs do proper store/load forwarding
32412724Snikos.nikoleris@arm.com                // internally, and have a sufficiently weak memory
32512724Snikos.nikoleris@arm.com                // model, this is probably unnecessary, but at some
32612724Snikos.nikoleris@arm.com                // point it must have seemed like we needed it...
32712724Snikos.nikoleris@arm.com                assert((pkt->needsWritable() && !blk->isWritable()) ||
32812724Snikos.nikoleris@arm.com                       pkt->req->isCacheMaintenance());
32912724Snikos.nikoleris@arm.com                blk->status &= ~BlkReadable;
33012724Snikos.nikoleris@arm.com            }
33112724Snikos.nikoleris@arm.com            // Here we are using forward_time, modelling the latency of
33212724Snikos.nikoleris@arm.com            // a miss (outbound) just as forwardLatency, neglecting the
33312724Snikos.nikoleris@arm.com            // lookupLatency component.
33412724Snikos.nikoleris@arm.com            allocateMissBuffer(pkt, forward_time);
33512724Snikos.nikoleris@arm.com        }
33612724Snikos.nikoleris@arm.com    }
33712724Snikos.nikoleris@arm.com}
33812724Snikos.nikoleris@arm.com
33912724Snikos.nikoleris@arm.comvoid
34012724Snikos.nikoleris@arm.comBaseCache::recvTimingReq(PacketPtr pkt)
34112724Snikos.nikoleris@arm.com{
34212724Snikos.nikoleris@arm.com    // anything that is merely forwarded pays for the forward latency and
34312724Snikos.nikoleris@arm.com    // the delay provided by the crossbar
34412724Snikos.nikoleris@arm.com    Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
34512724Snikos.nikoleris@arm.com
34613418Sodanrc@yahoo.com.br    Cycles lat;
34712724Snikos.nikoleris@arm.com    CacheBlk *blk = nullptr;
34812724Snikos.nikoleris@arm.com    bool satisfied = false;
34912724Snikos.nikoleris@arm.com    {
35012724Snikos.nikoleris@arm.com        PacketList writebacks;
35112724Snikos.nikoleris@arm.com        // Note that lat is passed by reference here. The function
35213418Sodanrc@yahoo.com.br        // access() will set the lat value.
35312724Snikos.nikoleris@arm.com        satisfied = access(pkt, blk, lat, writebacks);
35412724Snikos.nikoleris@arm.com
35512724Snikos.nikoleris@arm.com        // copy writebacks to write buffer here to ensure they logically
35612820Srmk35@cl.cam.ac.uk        // precede anything happening below
35712724Snikos.nikoleris@arm.com        doWritebacks(writebacks, forward_time);
35812724Snikos.nikoleris@arm.com    }
35912724Snikos.nikoleris@arm.com
36012724Snikos.nikoleris@arm.com    // Here we charge the headerDelay that takes into account the latencies
36112724Snikos.nikoleris@arm.com    // of the bus, if the packet comes from it.
36213418Sodanrc@yahoo.com.br    // The latency charged is just the value set by the access() function.
36312724Snikos.nikoleris@arm.com    // In case of a hit we are neglecting response latency.
36412724Snikos.nikoleris@arm.com    // In case of a miss we are neglecting forward latency.
36512724Snikos.nikoleris@arm.com    Tick request_time = clockEdge(lat) + pkt->headerDelay;
36612724Snikos.nikoleris@arm.com    // Here we reset the timing of the packet.
36712724Snikos.nikoleris@arm.com    pkt->headerDelay = pkt->payloadDelay = 0;
36812724Snikos.nikoleris@arm.com
36912724Snikos.nikoleris@arm.com    if (satisfied) {
37013416Sjavier.bueno@metempsy.com        // notify before anything else as later handleTimingReqHit might turn
37113416Sjavier.bueno@metempsy.com        // the packet in a response
37213416Sjavier.bueno@metempsy.com        ppHit->notify(pkt);
37312724Snikos.nikoleris@arm.com
37413416Sjavier.bueno@metempsy.com        if (prefetcher && blk && blk->wasPrefetched()) {
37513416Sjavier.bueno@metempsy.com            blk->status &= ~BlkHWPrefetched;
37612724Snikos.nikoleris@arm.com        }
37712724Snikos.nikoleris@arm.com
37812724Snikos.nikoleris@arm.com        handleTimingReqHit(pkt, blk, request_time);
37912724Snikos.nikoleris@arm.com    } else {
38012724Snikos.nikoleris@arm.com        handleTimingReqMiss(pkt, blk, forward_time, request_time);
38112724Snikos.nikoleris@arm.com
38213416Sjavier.bueno@metempsy.com        ppMiss->notify(pkt);
38312724Snikos.nikoleris@arm.com    }
38412724Snikos.nikoleris@arm.com
38513416Sjavier.bueno@metempsy.com    if (prefetcher) {
38613416Sjavier.bueno@metempsy.com        // track time of availability of next prefetch, if any
38713416Sjavier.bueno@metempsy.com        Tick next_pf_time = prefetcher->nextPrefetchReadyTime();
38813416Sjavier.bueno@metempsy.com        if (next_pf_time != MaxTick) {
38913416Sjavier.bueno@metempsy.com            schedMemSideSendEvent(next_pf_time);
39013416Sjavier.bueno@metempsy.com        }
39112724Snikos.nikoleris@arm.com    }
39212724Snikos.nikoleris@arm.com}
39312724Snikos.nikoleris@arm.com
39412724Snikos.nikoleris@arm.comvoid
39512724Snikos.nikoleris@arm.comBaseCache::handleUncacheableWriteResp(PacketPtr pkt)
39612724Snikos.nikoleris@arm.com{
39712724Snikos.nikoleris@arm.com    Tick completion_time = clockEdge(responseLatency) +
39812724Snikos.nikoleris@arm.com        pkt->headerDelay + pkt->payloadDelay;
39912724Snikos.nikoleris@arm.com
40012724Snikos.nikoleris@arm.com    // Reset the bus additional time as it is now accounted for
40112724Snikos.nikoleris@arm.com    pkt->headerDelay = pkt->payloadDelay = 0;
40212724Snikos.nikoleris@arm.com
40312724Snikos.nikoleris@arm.com    cpuSidePort.schedTimingResp(pkt, completion_time, true);
40412724Snikos.nikoleris@arm.com}
40512724Snikos.nikoleris@arm.com
40612724Snikos.nikoleris@arm.comvoid
40712724Snikos.nikoleris@arm.comBaseCache::recvTimingResp(PacketPtr pkt)
40812724Snikos.nikoleris@arm.com{
40912724Snikos.nikoleris@arm.com    assert(pkt->isResponse());
41012724Snikos.nikoleris@arm.com
41112724Snikos.nikoleris@arm.com    // all header delay should be paid for by the crossbar, unless
41212724Snikos.nikoleris@arm.com    // this is a prefetch response from above
41312724Snikos.nikoleris@arm.com    panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp,
41412724Snikos.nikoleris@arm.com             "%s saw a non-zero packet delay\n", name());
41512724Snikos.nikoleris@arm.com
41612724Snikos.nikoleris@arm.com    const bool is_error = pkt->isError();
41712724Snikos.nikoleris@arm.com
41812724Snikos.nikoleris@arm.com    if (is_error) {
41912724Snikos.nikoleris@arm.com        DPRINTF(Cache, "%s: Cache received %s with error\n", __func__,
42012724Snikos.nikoleris@arm.com                pkt->print());
42112724Snikos.nikoleris@arm.com    }
42212724Snikos.nikoleris@arm.com
42312724Snikos.nikoleris@arm.com    DPRINTF(Cache, "%s: Handling response %s\n", __func__,
42412724Snikos.nikoleris@arm.com            pkt->print());
42512724Snikos.nikoleris@arm.com
42612724Snikos.nikoleris@arm.com    // if this is a write, we should be looking at an uncacheable
42712724Snikos.nikoleris@arm.com    // write
42812724Snikos.nikoleris@arm.com    if (pkt->isWrite()) {
42912724Snikos.nikoleris@arm.com        assert(pkt->req->isUncacheable());
43012724Snikos.nikoleris@arm.com        handleUncacheableWriteResp(pkt);
43112724Snikos.nikoleris@arm.com        return;
43212724Snikos.nikoleris@arm.com    }
43312724Snikos.nikoleris@arm.com
43412724Snikos.nikoleris@arm.com    // we have dealt with any (uncacheable) writes above, from here on
43512724Snikos.nikoleris@arm.com    // we know we are dealing with an MSHR due to a miss or a prefetch
43612724Snikos.nikoleris@arm.com    MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState());
43712724Snikos.nikoleris@arm.com    assert(mshr);
43812724Snikos.nikoleris@arm.com
43912724Snikos.nikoleris@arm.com    if (mshr == noTargetMSHR) {
44012724Snikos.nikoleris@arm.com        // we always clear at least one target
44112724Snikos.nikoleris@arm.com        clearBlocked(Blocked_NoTargets);
44212724Snikos.nikoleris@arm.com        noTargetMSHR = nullptr;
44312724Snikos.nikoleris@arm.com    }
44412724Snikos.nikoleris@arm.com
44512724Snikos.nikoleris@arm.com    // Initial target is used just for stats
44612724Snikos.nikoleris@arm.com    MSHR::Target *initial_tgt = mshr->getTarget();
44712724Snikos.nikoleris@arm.com    int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
44812724Snikos.nikoleris@arm.com    Tick miss_latency = curTick() - initial_tgt->recvTime;
44912724Snikos.nikoleris@arm.com
45012724Snikos.nikoleris@arm.com    if (pkt->req->isUncacheable()) {
45112724Snikos.nikoleris@arm.com        assert(pkt->req->masterId() < system->maxMasters());
45212724Snikos.nikoleris@arm.com        mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
45312724Snikos.nikoleris@arm.com            miss_latency;
45412724Snikos.nikoleris@arm.com    } else {
45512724Snikos.nikoleris@arm.com        assert(pkt->req->masterId() < system->maxMasters());
45612724Snikos.nikoleris@arm.com        mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] +=
45712724Snikos.nikoleris@arm.com            miss_latency;
45812724Snikos.nikoleris@arm.com    }
45912724Snikos.nikoleris@arm.com
46012724Snikos.nikoleris@arm.com    PacketList writebacks;
46112724Snikos.nikoleris@arm.com
46212724Snikos.nikoleris@arm.com    bool is_fill = !mshr->isForward &&
46313350Snikos.nikoleris@arm.com        (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp ||
46413350Snikos.nikoleris@arm.com         mshr->wasWholeLineWrite);
46513350Snikos.nikoleris@arm.com
46613350Snikos.nikoleris@arm.com    // make sure that if the mshr was due to a whole line write then
46713350Snikos.nikoleris@arm.com    // the response is an invalidation
46813350Snikos.nikoleris@arm.com    assert(!mshr->wasWholeLineWrite || pkt->isInvalidate());
46912724Snikos.nikoleris@arm.com
47012724Snikos.nikoleris@arm.com    CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
47112724Snikos.nikoleris@arm.com
47212724Snikos.nikoleris@arm.com    if (is_fill && !is_error) {
47312724Snikos.nikoleris@arm.com        DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
47412724Snikos.nikoleris@arm.com                pkt->getAddr());
47512724Snikos.nikoleris@arm.com
47613352Snikos.nikoleris@arm.com        const bool allocate = (writeAllocator && mshr->wasWholeLineWrite) ?
47713352Snikos.nikoleris@arm.com            writeAllocator->allocate() : mshr->allocOnFill();
47813352Snikos.nikoleris@arm.com        blk = handleFill(pkt, blk, writebacks, allocate);
47912724Snikos.nikoleris@arm.com        assert(blk != nullptr);
48012724Snikos.nikoleris@arm.com    }
48112724Snikos.nikoleris@arm.com
48212724Snikos.nikoleris@arm.com    if (blk && blk->isValid() && pkt->isClean() && !pkt->isInvalidate()) {
48312724Snikos.nikoleris@arm.com        // The block was marked not readable while there was a pending
48412724Snikos.nikoleris@arm.com        // cache maintenance operation, restore its flag.
48512724Snikos.nikoleris@arm.com        blk->status |= BlkReadable;
48612794Snikos.nikoleris@arm.com
48712794Snikos.nikoleris@arm.com        // This was a cache clean operation (without invalidate)
48812794Snikos.nikoleris@arm.com        // and we have a copy of the block already. Since there
48912794Snikos.nikoleris@arm.com        // is no invalidation, we can promote targets that don't
49012794Snikos.nikoleris@arm.com        // require a writable copy
49112794Snikos.nikoleris@arm.com        mshr->promoteReadable();
49212724Snikos.nikoleris@arm.com    }
49312724Snikos.nikoleris@arm.com
49412724Snikos.nikoleris@arm.com    if (blk && blk->isWritable() && !pkt->req->isCacheInvalidate()) {
49512724Snikos.nikoleris@arm.com        // If at this point the referenced block is writable and the
49612724Snikos.nikoleris@arm.com        // response is not a cache invalidate, we promote targets that
49712724Snikos.nikoleris@arm.com        // were deferred as we couldn't guarrantee a writable copy
49812724Snikos.nikoleris@arm.com        mshr->promoteWritable();
49912724Snikos.nikoleris@arm.com    }
50012724Snikos.nikoleris@arm.com
50112724Snikos.nikoleris@arm.com    serviceMSHRTargets(mshr, pkt, blk, writebacks);
50212724Snikos.nikoleris@arm.com
50312724Snikos.nikoleris@arm.com    if (mshr->promoteDeferredTargets()) {
50412724Snikos.nikoleris@arm.com        // avoid later read getting stale data while write miss is
50512724Snikos.nikoleris@arm.com        // outstanding.. see comment in timingAccess()
50612724Snikos.nikoleris@arm.com        if (blk) {
50712724Snikos.nikoleris@arm.com            blk->status &= ~BlkReadable;
50812724Snikos.nikoleris@arm.com        }
50912724Snikos.nikoleris@arm.com        mshrQueue.markPending(mshr);
51012724Snikos.nikoleris@arm.com        schedMemSideSendEvent(clockEdge() + pkt->payloadDelay);
51112724Snikos.nikoleris@arm.com    } else {
51212724Snikos.nikoleris@arm.com        // while we deallocate an mshr from the queue we still have to
51312724Snikos.nikoleris@arm.com        // check the isFull condition before and after as we might
51412724Snikos.nikoleris@arm.com        // have been using the reserved entries already
51512724Snikos.nikoleris@arm.com        const bool was_full = mshrQueue.isFull();
51612724Snikos.nikoleris@arm.com        mshrQueue.deallocate(mshr);
51712724Snikos.nikoleris@arm.com        if (was_full && !mshrQueue.isFull()) {
51812724Snikos.nikoleris@arm.com            clearBlocked(Blocked_NoMSHRs);
51912724Snikos.nikoleris@arm.com        }
52012724Snikos.nikoleris@arm.com
52112724Snikos.nikoleris@arm.com        // Request the bus for a prefetch if this deallocation freed enough
52212724Snikos.nikoleris@arm.com        // MSHRs for a prefetch to take place
52312724Snikos.nikoleris@arm.com        if (prefetcher && mshrQueue.canPrefetch()) {
52412724Snikos.nikoleris@arm.com            Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(),
52512724Snikos.nikoleris@arm.com                                         clockEdge());
52612724Snikos.nikoleris@arm.com            if (next_pf_time != MaxTick)
52712724Snikos.nikoleris@arm.com                schedMemSideSendEvent(next_pf_time);
52812724Snikos.nikoleris@arm.com        }
52912724Snikos.nikoleris@arm.com    }
53012724Snikos.nikoleris@arm.com
53112724Snikos.nikoleris@arm.com    // if we used temp block, check to see if its valid and then clear it out
53212724Snikos.nikoleris@arm.com    if (blk == tempBlock && tempBlock->isValid()) {
53312724Snikos.nikoleris@arm.com        evictBlock(blk, writebacks);
53412724Snikos.nikoleris@arm.com    }
53512724Snikos.nikoleris@arm.com
53612724Snikos.nikoleris@arm.com    const Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
53712724Snikos.nikoleris@arm.com    // copy writebacks to write buffer
53812724Snikos.nikoleris@arm.com    doWritebacks(writebacks, forward_time);
53912724Snikos.nikoleris@arm.com
54012724Snikos.nikoleris@arm.com    DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print());
54112724Snikos.nikoleris@arm.com    delete pkt;
54212724Snikos.nikoleris@arm.com}
54312724Snikos.nikoleris@arm.com
54412724Snikos.nikoleris@arm.com
54512724Snikos.nikoleris@arm.comTick
54612724Snikos.nikoleris@arm.comBaseCache::recvAtomic(PacketPtr pkt)
54712724Snikos.nikoleris@arm.com{
54812724Snikos.nikoleris@arm.com    // should assert here that there are no outstanding MSHRs or
54912724Snikos.nikoleris@arm.com    // writebacks... that would mean that someone used an atomic
55012724Snikos.nikoleris@arm.com    // access in timing mode
55112724Snikos.nikoleris@arm.com
55213412Snikos.nikoleris@arm.com    // We use lookupLatency here because it is used to specify the latency
55313412Snikos.nikoleris@arm.com    // to access.
55413412Snikos.nikoleris@arm.com    Cycles lat = lookupLatency;
55513412Snikos.nikoleris@arm.com
55612724Snikos.nikoleris@arm.com    CacheBlk *blk = nullptr;
55712724Snikos.nikoleris@arm.com    PacketList writebacks;
55812724Snikos.nikoleris@arm.com    bool satisfied = access(pkt, blk, lat, writebacks);
55912724Snikos.nikoleris@arm.com
56012724Snikos.nikoleris@arm.com    if (pkt->isClean() && blk && blk->isDirty()) {
56112724Snikos.nikoleris@arm.com        // A cache clean opearation is looking for a dirty
56212724Snikos.nikoleris@arm.com        // block. If a dirty block is encountered a WriteClean
56312724Snikos.nikoleris@arm.com        // will update any copies to the path to the memory
56412724Snikos.nikoleris@arm.com        // until the point of reference.
56512724Snikos.nikoleris@arm.com        DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n",
56612724Snikos.nikoleris@arm.com                __func__, pkt->print(), blk->print());
56712724Snikos.nikoleris@arm.com        PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id);
56812724Snikos.nikoleris@arm.com        writebacks.push_back(wb_pkt);
56912724Snikos.nikoleris@arm.com        pkt->setSatisfied();
57012724Snikos.nikoleris@arm.com    }
57112724Snikos.nikoleris@arm.com
57212724Snikos.nikoleris@arm.com    // handle writebacks resulting from the access here to ensure they
57312820Srmk35@cl.cam.ac.uk    // logically precede anything happening below
57412724Snikos.nikoleris@arm.com    doWritebacksAtomic(writebacks);
57512724Snikos.nikoleris@arm.com    assert(writebacks.empty());
57612724Snikos.nikoleris@arm.com
57712724Snikos.nikoleris@arm.com    if (!satisfied) {
57812724Snikos.nikoleris@arm.com        lat += handleAtomicReqMiss(pkt, blk, writebacks);
57912724Snikos.nikoleris@arm.com    }
58012724Snikos.nikoleris@arm.com
58112724Snikos.nikoleris@arm.com    // Note that we don't invoke the prefetcher at all in atomic mode.
58212724Snikos.nikoleris@arm.com    // It's not clear how to do it properly, particularly for
58312724Snikos.nikoleris@arm.com    // prefetchers that aggressively generate prefetch candidates and
58412724Snikos.nikoleris@arm.com    // rely on bandwidth contention to throttle them; these will tend
58512724Snikos.nikoleris@arm.com    // to pollute the cache in atomic mode since there is no bandwidth
58612724Snikos.nikoleris@arm.com    // contention.  If we ever do want to enable prefetching in atomic
58712724Snikos.nikoleris@arm.com    // mode, though, this is the place to do it... see timingAccess()
58812724Snikos.nikoleris@arm.com    // for an example (though we'd want to issue the prefetch(es)
58912724Snikos.nikoleris@arm.com    // immediately rather than calling requestMemSideBus() as we do
59012724Snikos.nikoleris@arm.com    // there).
59112724Snikos.nikoleris@arm.com
59212724Snikos.nikoleris@arm.com    // do any writebacks resulting from the response handling
59312724Snikos.nikoleris@arm.com    doWritebacksAtomic(writebacks);
59412724Snikos.nikoleris@arm.com
59512724Snikos.nikoleris@arm.com    // if we used temp block, check to see if its valid and if so
59612724Snikos.nikoleris@arm.com    // clear it out, but only do so after the call to recvAtomic is
59712724Snikos.nikoleris@arm.com    // finished so that any downstream observers (such as a snoop
59812724Snikos.nikoleris@arm.com    // filter), first see the fill, and only then see the eviction
59912724Snikos.nikoleris@arm.com    if (blk == tempBlock && tempBlock->isValid()) {
60012724Snikos.nikoleris@arm.com        // the atomic CPU calls recvAtomic for fetch and load/store
60112724Snikos.nikoleris@arm.com        // sequentuially, and we may already have a tempBlock
60212724Snikos.nikoleris@arm.com        // writeback from the fetch that we have not yet sent
60312724Snikos.nikoleris@arm.com        if (tempBlockWriteback) {
60412724Snikos.nikoleris@arm.com            // if that is the case, write the prevoius one back, and
60512724Snikos.nikoleris@arm.com            // do not schedule any new event
60612724Snikos.nikoleris@arm.com            writebackTempBlockAtomic();
60712724Snikos.nikoleris@arm.com        } else {
60812724Snikos.nikoleris@arm.com            // the writeback/clean eviction happens after the call to
60912724Snikos.nikoleris@arm.com            // recvAtomic has finished (but before any successive
61012724Snikos.nikoleris@arm.com            // calls), so that the response handling from the fill is
61112724Snikos.nikoleris@arm.com            // allowed to happen first
61212724Snikos.nikoleris@arm.com            schedule(writebackTempBlockAtomicEvent, curTick());
61312724Snikos.nikoleris@arm.com        }
61412724Snikos.nikoleris@arm.com
61512724Snikos.nikoleris@arm.com        tempBlockWriteback = evictBlock(blk);
61612724Snikos.nikoleris@arm.com    }
61712724Snikos.nikoleris@arm.com
61812724Snikos.nikoleris@arm.com    if (pkt->needsResponse()) {
61912724Snikos.nikoleris@arm.com        pkt->makeAtomicResponse();
62012724Snikos.nikoleris@arm.com    }
62112724Snikos.nikoleris@arm.com
62212724Snikos.nikoleris@arm.com    return lat * clockPeriod();
62312724Snikos.nikoleris@arm.com}
62412724Snikos.nikoleris@arm.com
62512724Snikos.nikoleris@arm.comvoid
62612724Snikos.nikoleris@arm.comBaseCache::functionalAccess(PacketPtr pkt, bool from_cpu_side)
62712724Snikos.nikoleris@arm.com{
62812724Snikos.nikoleris@arm.com    Addr blk_addr = pkt->getBlockAddr(blkSize);
62912724Snikos.nikoleris@arm.com    bool is_secure = pkt->isSecure();
63012724Snikos.nikoleris@arm.com    CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
63112724Snikos.nikoleris@arm.com    MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
63212724Snikos.nikoleris@arm.com
63312724Snikos.nikoleris@arm.com    pkt->pushLabel(name());
63412724Snikos.nikoleris@arm.com
63512724Snikos.nikoleris@arm.com    CacheBlkPrintWrapper cbpw(blk);
63612724Snikos.nikoleris@arm.com
63712724Snikos.nikoleris@arm.com    // Note that just because an L2/L3 has valid data doesn't mean an
63812724Snikos.nikoleris@arm.com    // L1 doesn't have a more up-to-date modified copy that still
63912724Snikos.nikoleris@arm.com    // needs to be found.  As a result we always update the request if
64012724Snikos.nikoleris@arm.com    // we have it, but only declare it satisfied if we are the owner.
64112724Snikos.nikoleris@arm.com
64212724Snikos.nikoleris@arm.com    // see if we have data at all (owned or otherwise)
64312724Snikos.nikoleris@arm.com    bool have_data = blk && blk->isValid()
64412823Srmk35@cl.cam.ac.uk        && pkt->trySatisfyFunctional(&cbpw, blk_addr, is_secure, blkSize,
64512823Srmk35@cl.cam.ac.uk                                     blk->data);
64612724Snikos.nikoleris@arm.com
64712724Snikos.nikoleris@arm.com    // data we have is dirty if marked as such or if we have an
64812724Snikos.nikoleris@arm.com    // in-service MSHR that is pending a modified line
64912724Snikos.nikoleris@arm.com    bool have_dirty =
65012724Snikos.nikoleris@arm.com        have_data && (blk->isDirty() ||
65112724Snikos.nikoleris@arm.com                      (mshr && mshr->inService && mshr->isPendingModified()));
65212724Snikos.nikoleris@arm.com
65312724Snikos.nikoleris@arm.com    bool done = have_dirty ||
65412823Srmk35@cl.cam.ac.uk        cpuSidePort.trySatisfyFunctional(pkt) ||
65512823Srmk35@cl.cam.ac.uk        mshrQueue.trySatisfyFunctional(pkt, blk_addr) ||
65612823Srmk35@cl.cam.ac.uk        writeBuffer.trySatisfyFunctional(pkt, blk_addr) ||
65712823Srmk35@cl.cam.ac.uk        memSidePort.trySatisfyFunctional(pkt);
65812724Snikos.nikoleris@arm.com
65912724Snikos.nikoleris@arm.com    DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__,  pkt->print(),
66012724Snikos.nikoleris@arm.com            (blk && blk->isValid()) ? "valid " : "",
66112724Snikos.nikoleris@arm.com            have_data ? "data " : "", done ? "done " : "");
66212724Snikos.nikoleris@arm.com
66312724Snikos.nikoleris@arm.com    // We're leaving the cache, so pop cache->name() label
66412724Snikos.nikoleris@arm.com    pkt->popLabel();
66512724Snikos.nikoleris@arm.com
66612724Snikos.nikoleris@arm.com    if (done) {
66712724Snikos.nikoleris@arm.com        pkt->makeResponse();
66812724Snikos.nikoleris@arm.com    } else {
66912724Snikos.nikoleris@arm.com        // if it came as a request from the CPU side then make sure it
67012724Snikos.nikoleris@arm.com        // continues towards the memory side
67112724Snikos.nikoleris@arm.com        if (from_cpu_side) {
67212724Snikos.nikoleris@arm.com            memSidePort.sendFunctional(pkt);
67312724Snikos.nikoleris@arm.com        } else if (cpuSidePort.isSnooping()) {
67412724Snikos.nikoleris@arm.com            // if it came from the memory side, it must be a snoop request
67512724Snikos.nikoleris@arm.com            // and we should only forward it if we are forwarding snoops
67612724Snikos.nikoleris@arm.com            cpuSidePort.sendFunctionalSnoop(pkt);
67712724Snikos.nikoleris@arm.com        }
67812724Snikos.nikoleris@arm.com    }
67912724Snikos.nikoleris@arm.com}
68012724Snikos.nikoleris@arm.com
68112724Snikos.nikoleris@arm.com
68212724Snikos.nikoleris@arm.comvoid
68312724Snikos.nikoleris@arm.comBaseCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt)
68412724Snikos.nikoleris@arm.com{
68512724Snikos.nikoleris@arm.com    assert(pkt->isRequest());
68612724Snikos.nikoleris@arm.com
68712724Snikos.nikoleris@arm.com    uint64_t overwrite_val;
68812724Snikos.nikoleris@arm.com    bool overwrite_mem;
68912724Snikos.nikoleris@arm.com    uint64_t condition_val64;
69012724Snikos.nikoleris@arm.com    uint32_t condition_val32;
69112724Snikos.nikoleris@arm.com
69212724Snikos.nikoleris@arm.com    int offset = pkt->getOffset(blkSize);
69312724Snikos.nikoleris@arm.com    uint8_t *blk_data = blk->data + offset;
69412724Snikos.nikoleris@arm.com
69512724Snikos.nikoleris@arm.com    assert(sizeof(uint64_t) >= pkt->getSize());
69612724Snikos.nikoleris@arm.com
69712724Snikos.nikoleris@arm.com    overwrite_mem = true;
69812724Snikos.nikoleris@arm.com    // keep a copy of our possible write value, and copy what is at the
69912724Snikos.nikoleris@arm.com    // memory address into the packet
70012724Snikos.nikoleris@arm.com    pkt->writeData((uint8_t *)&overwrite_val);
70112724Snikos.nikoleris@arm.com    pkt->setData(blk_data);
70212724Snikos.nikoleris@arm.com
70312724Snikos.nikoleris@arm.com    if (pkt->req->isCondSwap()) {
70412724Snikos.nikoleris@arm.com        if (pkt->getSize() == sizeof(uint64_t)) {
70512724Snikos.nikoleris@arm.com            condition_val64 = pkt->req->getExtraData();
70612724Snikos.nikoleris@arm.com            overwrite_mem = !std::memcmp(&condition_val64, blk_data,
70712724Snikos.nikoleris@arm.com                                         sizeof(uint64_t));
70812724Snikos.nikoleris@arm.com        } else if (pkt->getSize() == sizeof(uint32_t)) {
70912724Snikos.nikoleris@arm.com            condition_val32 = (uint32_t)pkt->req->getExtraData();
71012724Snikos.nikoleris@arm.com            overwrite_mem = !std::memcmp(&condition_val32, blk_data,
71112724Snikos.nikoleris@arm.com                                         sizeof(uint32_t));
71212724Snikos.nikoleris@arm.com        } else
71312724Snikos.nikoleris@arm.com            panic("Invalid size for conditional read/write\n");
71412724Snikos.nikoleris@arm.com    }
71512724Snikos.nikoleris@arm.com
71612724Snikos.nikoleris@arm.com    if (overwrite_mem) {
71712724Snikos.nikoleris@arm.com        std::memcpy(blk_data, &overwrite_val, pkt->getSize());
71812724Snikos.nikoleris@arm.com        blk->status |= BlkDirty;
71912724Snikos.nikoleris@arm.com    }
72012724Snikos.nikoleris@arm.com}
72112724Snikos.nikoleris@arm.com
72212724Snikos.nikoleris@arm.comQueueEntry*
72312724Snikos.nikoleris@arm.comBaseCache::getNextQueueEntry()
72412724Snikos.nikoleris@arm.com{
72512724Snikos.nikoleris@arm.com    // Check both MSHR queue and write buffer for potential requests,
72612724Snikos.nikoleris@arm.com    // note that null does not mean there is no request, it could
72712724Snikos.nikoleris@arm.com    // simply be that it is not ready
72812724Snikos.nikoleris@arm.com    MSHR *miss_mshr  = mshrQueue.getNext();
72912724Snikos.nikoleris@arm.com    WriteQueueEntry *wq_entry = writeBuffer.getNext();
73012724Snikos.nikoleris@arm.com
73112724Snikos.nikoleris@arm.com    // If we got a write buffer request ready, first priority is a
73212724Snikos.nikoleris@arm.com    // full write buffer, otherwise we favour the miss requests
73312724Snikos.nikoleris@arm.com    if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) {
73412724Snikos.nikoleris@arm.com        // need to search MSHR queue for conflicting earlier miss.
73512724Snikos.nikoleris@arm.com        MSHR *conflict_mshr =
73612724Snikos.nikoleris@arm.com            mshrQueue.findPending(wq_entry->blkAddr,
73712724Snikos.nikoleris@arm.com                                  wq_entry->isSecure);
73812724Snikos.nikoleris@arm.com
73912724Snikos.nikoleris@arm.com        if (conflict_mshr && conflict_mshr->order < wq_entry->order) {
74012724Snikos.nikoleris@arm.com            // Service misses in order until conflict is cleared.
74112724Snikos.nikoleris@arm.com            return conflict_mshr;
74212724Snikos.nikoleris@arm.com
74312724Snikos.nikoleris@arm.com            // @todo Note that we ignore the ready time of the conflict here
74412724Snikos.nikoleris@arm.com        }
74512724Snikos.nikoleris@arm.com
74612724Snikos.nikoleris@arm.com        // No conflicts; issue write
74712724Snikos.nikoleris@arm.com        return wq_entry;
74812724Snikos.nikoleris@arm.com    } else if (miss_mshr) {
74912724Snikos.nikoleris@arm.com        // need to check for conflicting earlier writeback
75012724Snikos.nikoleris@arm.com        WriteQueueEntry *conflict_mshr =
75112724Snikos.nikoleris@arm.com            writeBuffer.findPending(miss_mshr->blkAddr,
75212724Snikos.nikoleris@arm.com                                    miss_mshr->isSecure);
75312724Snikos.nikoleris@arm.com        if (conflict_mshr) {
75412724Snikos.nikoleris@arm.com            // not sure why we don't check order here... it was in the
75512724Snikos.nikoleris@arm.com            // original code but commented out.
75612724Snikos.nikoleris@arm.com
75712724Snikos.nikoleris@arm.com            // The only way this happens is if we are
75812724Snikos.nikoleris@arm.com            // doing a write and we didn't have permissions
75912724Snikos.nikoleris@arm.com            // then subsequently saw a writeback (owned got evicted)
76012724Snikos.nikoleris@arm.com            // We need to make sure to perform the writeback first
76112724Snikos.nikoleris@arm.com            // To preserve the dirty data, then we can issue the write
76212724Snikos.nikoleris@arm.com
76312724Snikos.nikoleris@arm.com            // should we return wq_entry here instead?  I.e. do we
76412724Snikos.nikoleris@arm.com            // have to flush writes in order?  I don't think so... not
76512724Snikos.nikoleris@arm.com            // for Alpha anyway.  Maybe for x86?
76612724Snikos.nikoleris@arm.com            return conflict_mshr;
76712724Snikos.nikoleris@arm.com
76812724Snikos.nikoleris@arm.com            // @todo Note that we ignore the ready time of the conflict here
76912724Snikos.nikoleris@arm.com        }
77012724Snikos.nikoleris@arm.com
77112724Snikos.nikoleris@arm.com        // No conflicts; issue read
77212724Snikos.nikoleris@arm.com        return miss_mshr;
77312724Snikos.nikoleris@arm.com    }
77412724Snikos.nikoleris@arm.com
77512724Snikos.nikoleris@arm.com    // fall through... no pending requests.  Try a prefetch.
77612724Snikos.nikoleris@arm.com    assert(!miss_mshr && !wq_entry);
77712724Snikos.nikoleris@arm.com    if (prefetcher && mshrQueue.canPrefetch()) {
77812724Snikos.nikoleris@arm.com        // If we have a miss queue slot, we can try a prefetch
77912724Snikos.nikoleris@arm.com        PacketPtr pkt = prefetcher->getPacket();
78012724Snikos.nikoleris@arm.com        if (pkt) {
78112724Snikos.nikoleris@arm.com            Addr pf_addr = pkt->getBlockAddr(blkSize);
78212724Snikos.nikoleris@arm.com            if (!tags->findBlock(pf_addr, pkt->isSecure()) &&
78312724Snikos.nikoleris@arm.com                !mshrQueue.findMatch(pf_addr, pkt->isSecure()) &&
78412724Snikos.nikoleris@arm.com                !writeBuffer.findMatch(pf_addr, pkt->isSecure())) {
78512724Snikos.nikoleris@arm.com                // Update statistic on number of prefetches issued
78612724Snikos.nikoleris@arm.com                // (hwpf_mshr_misses)
78712724Snikos.nikoleris@arm.com                assert(pkt->req->masterId() < system->maxMasters());
78812724Snikos.nikoleris@arm.com                mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
78912724Snikos.nikoleris@arm.com
79012724Snikos.nikoleris@arm.com                // allocate an MSHR and return it, note
79112724Snikos.nikoleris@arm.com                // that we send the packet straight away, so do not
79212724Snikos.nikoleris@arm.com                // schedule the send
79312724Snikos.nikoleris@arm.com                return allocateMissBuffer(pkt, curTick(), false);
79412724Snikos.nikoleris@arm.com            } else {
79512724Snikos.nikoleris@arm.com                // free the request and packet
79612724Snikos.nikoleris@arm.com                delete pkt;
79712724Snikos.nikoleris@arm.com            }
79812724Snikos.nikoleris@arm.com        }
79912724Snikos.nikoleris@arm.com    }
80012724Snikos.nikoleris@arm.com
80112724Snikos.nikoleris@arm.com    return nullptr;
80212724Snikos.nikoleris@arm.com}
80312724Snikos.nikoleris@arm.com
80412724Snikos.nikoleris@arm.comvoid
80512724Snikos.nikoleris@arm.comBaseCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool, bool)
80612724Snikos.nikoleris@arm.com{
80712724Snikos.nikoleris@arm.com    assert(pkt->isRequest());
80812724Snikos.nikoleris@arm.com
80912724Snikos.nikoleris@arm.com    assert(blk && blk->isValid());
81012724Snikos.nikoleris@arm.com    // Occasionally this is not true... if we are a lower-level cache
81112724Snikos.nikoleris@arm.com    // satisfying a string of Read and ReadEx requests from
81212724Snikos.nikoleris@arm.com    // upper-level caches, a Read will mark the block as shared but we
81312724Snikos.nikoleris@arm.com    // can satisfy a following ReadEx anyway since we can rely on the
81412724Snikos.nikoleris@arm.com    // Read requester(s) to have buffered the ReadEx snoop and to
81512724Snikos.nikoleris@arm.com    // invalidate their blocks after receiving them.
81612724Snikos.nikoleris@arm.com    // assert(!pkt->needsWritable() || blk->isWritable());
81712724Snikos.nikoleris@arm.com    assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize);
81812724Snikos.nikoleris@arm.com
81912724Snikos.nikoleris@arm.com    // Check RMW operations first since both isRead() and
82012724Snikos.nikoleris@arm.com    // isWrite() will be true for them
82112724Snikos.nikoleris@arm.com    if (pkt->cmd == MemCmd::SwapReq) {
82212766Sqtt2@cornell.edu        if (pkt->isAtomicOp()) {
82312766Sqtt2@cornell.edu            // extract data from cache and save it into the data field in
82412766Sqtt2@cornell.edu            // the packet as a return value from this atomic op
82512766Sqtt2@cornell.edu            int offset = tags->extractBlkOffset(pkt->getAddr());
82612766Sqtt2@cornell.edu            uint8_t *blk_data = blk->data + offset;
82713377Sodanrc@yahoo.com.br            pkt->setData(blk_data);
82812766Sqtt2@cornell.edu
82912766Sqtt2@cornell.edu            // execute AMO operation
83012766Sqtt2@cornell.edu            (*(pkt->getAtomicOp()))(blk_data);
83112766Sqtt2@cornell.edu
83212766Sqtt2@cornell.edu            // set block status to dirty
83312766Sqtt2@cornell.edu            blk->status |= BlkDirty;
83412766Sqtt2@cornell.edu        } else {
83512766Sqtt2@cornell.edu            cmpAndSwap(blk, pkt);
83612766Sqtt2@cornell.edu        }
83712724Snikos.nikoleris@arm.com    } else if (pkt->isWrite()) {
83812724Snikos.nikoleris@arm.com        // we have the block in a writable state and can go ahead,
83912724Snikos.nikoleris@arm.com        // note that the line may be also be considered writable in
84012724Snikos.nikoleris@arm.com        // downstream caches along the path to memory, but always
84112724Snikos.nikoleris@arm.com        // Exclusive, and never Modified
84212724Snikos.nikoleris@arm.com        assert(blk->isWritable());
84312724Snikos.nikoleris@arm.com        // Write or WriteLine at the first cache with block in writable state
84412724Snikos.nikoleris@arm.com        if (blk->checkWrite(pkt)) {
84512724Snikos.nikoleris@arm.com            pkt->writeDataToBlock(blk->data, blkSize);
84612724Snikos.nikoleris@arm.com        }
84712724Snikos.nikoleris@arm.com        // Always mark the line as dirty (and thus transition to the
84812724Snikos.nikoleris@arm.com        // Modified state) even if we are a failed StoreCond so we
84912724Snikos.nikoleris@arm.com        // supply data to any snoops that have appended themselves to
85012724Snikos.nikoleris@arm.com        // this cache before knowing the store will fail.
85112724Snikos.nikoleris@arm.com        blk->status |= BlkDirty;
85212724Snikos.nikoleris@arm.com        DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print());
85312724Snikos.nikoleris@arm.com    } else if (pkt->isRead()) {
85412724Snikos.nikoleris@arm.com        if (pkt->isLLSC()) {
85512724Snikos.nikoleris@arm.com            blk->trackLoadLocked(pkt);
85612724Snikos.nikoleris@arm.com        }
85712724Snikos.nikoleris@arm.com
85812724Snikos.nikoleris@arm.com        // all read responses have a data payload
85912724Snikos.nikoleris@arm.com        assert(pkt->hasRespData());
86012724Snikos.nikoleris@arm.com        pkt->setDataFromBlock(blk->data, blkSize);
86112724Snikos.nikoleris@arm.com    } else if (pkt->isUpgrade()) {
86212724Snikos.nikoleris@arm.com        // sanity check
86312724Snikos.nikoleris@arm.com        assert(!pkt->hasSharers());
86412724Snikos.nikoleris@arm.com
86512724Snikos.nikoleris@arm.com        if (blk->isDirty()) {
86612724Snikos.nikoleris@arm.com            // we were in the Owned state, and a cache above us that
86712724Snikos.nikoleris@arm.com            // has the line in Shared state needs to be made aware
86812724Snikos.nikoleris@arm.com            // that the data it already has is in fact dirty
86912724Snikos.nikoleris@arm.com            pkt->setCacheResponding();
87012724Snikos.nikoleris@arm.com            blk->status &= ~BlkDirty;
87112724Snikos.nikoleris@arm.com        }
87212794Snikos.nikoleris@arm.com    } else if (pkt->isClean()) {
87312794Snikos.nikoleris@arm.com        blk->status &= ~BlkDirty;
87412724Snikos.nikoleris@arm.com    } else {
87512724Snikos.nikoleris@arm.com        assert(pkt->isInvalidate());
87612724Snikos.nikoleris@arm.com        invalidateBlock(blk);
87712724Snikos.nikoleris@arm.com        DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__,
87812724Snikos.nikoleris@arm.com                pkt->print());
87912724Snikos.nikoleris@arm.com    }
88012724Snikos.nikoleris@arm.com}
88112724Snikos.nikoleris@arm.com
88212724Snikos.nikoleris@arm.com/////////////////////////////////////////////////////
88312724Snikos.nikoleris@arm.com//
88412724Snikos.nikoleris@arm.com// Access path: requests coming in from the CPU side
88512724Snikos.nikoleris@arm.com//
88612724Snikos.nikoleris@arm.com/////////////////////////////////////////////////////
88713418Sodanrc@yahoo.com.brCycles
88813418Sodanrc@yahoo.com.brBaseCache::calculateAccessLatency(const CacheBlk* blk,
88913418Sodanrc@yahoo.com.br                                  const Cycles lookup_lat) const
89013418Sodanrc@yahoo.com.br{
89113418Sodanrc@yahoo.com.br    Cycles lat(lookup_lat);
89213418Sodanrc@yahoo.com.br
89313418Sodanrc@yahoo.com.br    if (blk != nullptr) {
89413418Sodanrc@yahoo.com.br        // First access tags, then data
89513418Sodanrc@yahoo.com.br        if (sequentialAccess) {
89613418Sodanrc@yahoo.com.br            lat += dataLatency;
89713418Sodanrc@yahoo.com.br        // Latency is dictated by the slowest of tag and data latencies
89813418Sodanrc@yahoo.com.br        } else {
89913418Sodanrc@yahoo.com.br            lat = std::max(lookup_lat, dataLatency);
90013418Sodanrc@yahoo.com.br        }
90113418Sodanrc@yahoo.com.br
90213418Sodanrc@yahoo.com.br        // Check if the block to be accessed is available. If not, apply the
90313418Sodanrc@yahoo.com.br        // access latency on top of block->whenReady.
90413418Sodanrc@yahoo.com.br        if (blk->whenReady > curTick() &&
90513418Sodanrc@yahoo.com.br            ticksToCycles(blk->whenReady - curTick()) > lat) {
90613418Sodanrc@yahoo.com.br            lat += ticksToCycles(blk->whenReady - curTick());
90713418Sodanrc@yahoo.com.br        }
90813418Sodanrc@yahoo.com.br    }
90913418Sodanrc@yahoo.com.br
91013418Sodanrc@yahoo.com.br    return lat;
91113418Sodanrc@yahoo.com.br}
91212724Snikos.nikoleris@arm.com
91312724Snikos.nikoleris@arm.combool
91412724Snikos.nikoleris@arm.comBaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
91512724Snikos.nikoleris@arm.com                  PacketList &writebacks)
91612724Snikos.nikoleris@arm.com{
91712724Snikos.nikoleris@arm.com    // sanity check
91812724Snikos.nikoleris@arm.com    assert(pkt->isRequest());
91912724Snikos.nikoleris@arm.com
92012724Snikos.nikoleris@arm.com    chatty_assert(!(isReadOnly && pkt->isWrite()),
92112724Snikos.nikoleris@arm.com                  "Should never see a write in a read-only cache %s\n",
92212724Snikos.nikoleris@arm.com                  name());
92312724Snikos.nikoleris@arm.com
92413418Sodanrc@yahoo.com.br    // Access block in the tags
92513418Sodanrc@yahoo.com.br    Cycles tag_latency(0);
92613418Sodanrc@yahoo.com.br    blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), tag_latency);
92713418Sodanrc@yahoo.com.br
92813418Sodanrc@yahoo.com.br    // Calculate access latency
92913418Sodanrc@yahoo.com.br    lat = calculateAccessLatency(blk, tag_latency);
93012724Snikos.nikoleris@arm.com
93112724Snikos.nikoleris@arm.com    DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(),
93212724Snikos.nikoleris@arm.com            blk ? "hit " + blk->print() : "miss");
93312724Snikos.nikoleris@arm.com
93412724Snikos.nikoleris@arm.com    if (pkt->req->isCacheMaintenance()) {
93512724Snikos.nikoleris@arm.com        // A cache maintenance operation is always forwarded to the
93612724Snikos.nikoleris@arm.com        // memory below even if the block is found in dirty state.
93712724Snikos.nikoleris@arm.com
93812724Snikos.nikoleris@arm.com        // We defer any changes to the state of the block until we
93912724Snikos.nikoleris@arm.com        // create and mark as in service the mshr for the downstream
94012724Snikos.nikoleris@arm.com        // packet.
94112724Snikos.nikoleris@arm.com        return false;
94212724Snikos.nikoleris@arm.com    }
94312724Snikos.nikoleris@arm.com
94412724Snikos.nikoleris@arm.com    if (pkt->isEviction()) {
94512724Snikos.nikoleris@arm.com        // We check for presence of block in above caches before issuing
94612724Snikos.nikoleris@arm.com        // Writeback or CleanEvict to write buffer. Therefore the only
94712724Snikos.nikoleris@arm.com        // possible cases can be of a CleanEvict packet coming from above
94812724Snikos.nikoleris@arm.com        // encountering a Writeback generated in this cache peer cache and
94912724Snikos.nikoleris@arm.com        // waiting in the write buffer. Cases of upper level peer caches
95012724Snikos.nikoleris@arm.com        // generating CleanEvict and Writeback or simply CleanEvict and
95112724Snikos.nikoleris@arm.com        // CleanEvict almost simultaneously will be caught by snoops sent out
95212724Snikos.nikoleris@arm.com        // by crossbar.
95312724Snikos.nikoleris@arm.com        WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(),
95412724Snikos.nikoleris@arm.com                                                          pkt->isSecure());
95512724Snikos.nikoleris@arm.com        if (wb_entry) {
95612724Snikos.nikoleris@arm.com            assert(wb_entry->getNumTargets() == 1);
95712724Snikos.nikoleris@arm.com            PacketPtr wbPkt = wb_entry->getTarget()->pkt;
95812724Snikos.nikoleris@arm.com            assert(wbPkt->isWriteback());
95912724Snikos.nikoleris@arm.com
96012724Snikos.nikoleris@arm.com            if (pkt->isCleanEviction()) {
96112724Snikos.nikoleris@arm.com                // The CleanEvict and WritebackClean snoops into other
96212724Snikos.nikoleris@arm.com                // peer caches of the same level while traversing the
96312724Snikos.nikoleris@arm.com                // crossbar. If a copy of the block is found, the
96412724Snikos.nikoleris@arm.com                // packet is deleted in the crossbar. Hence, none of
96512724Snikos.nikoleris@arm.com                // the other upper level caches connected to this
96612724Snikos.nikoleris@arm.com                // cache have the block, so we can clear the
96712724Snikos.nikoleris@arm.com                // BLOCK_CACHED flag in the Writeback if set and
96812724Snikos.nikoleris@arm.com                // discard the CleanEvict by returning true.
96912724Snikos.nikoleris@arm.com                wbPkt->clearBlockCached();
97012724Snikos.nikoleris@arm.com                return true;
97112724Snikos.nikoleris@arm.com            } else {
97212724Snikos.nikoleris@arm.com                assert(pkt->cmd == MemCmd::WritebackDirty);
97312724Snikos.nikoleris@arm.com                // Dirty writeback from above trumps our clean
97412724Snikos.nikoleris@arm.com                // writeback... discard here
97512724Snikos.nikoleris@arm.com                // Note: markInService will remove entry from writeback buffer.
97612724Snikos.nikoleris@arm.com                markInService(wb_entry);
97712724Snikos.nikoleris@arm.com                delete wbPkt;
97812724Snikos.nikoleris@arm.com            }
97912724Snikos.nikoleris@arm.com        }
98012724Snikos.nikoleris@arm.com    }
98112724Snikos.nikoleris@arm.com
98212724Snikos.nikoleris@arm.com    // Writeback handling is special case.  We can write the block into
98312724Snikos.nikoleris@arm.com    // the cache without having a writeable copy (or any copy at all).
98412724Snikos.nikoleris@arm.com    if (pkt->isWriteback()) {
98512724Snikos.nikoleris@arm.com        assert(blkSize == pkt->getSize());
98612724Snikos.nikoleris@arm.com
98712724Snikos.nikoleris@arm.com        // we could get a clean writeback while we are having
98812724Snikos.nikoleris@arm.com        // outstanding accesses to a block, do the simple thing for
98912724Snikos.nikoleris@arm.com        // now and drop the clean writeback so that we do not upset
99012724Snikos.nikoleris@arm.com        // any ordering/decisions about ownership already taken
99112724Snikos.nikoleris@arm.com        if (pkt->cmd == MemCmd::WritebackClean &&
99212724Snikos.nikoleris@arm.com            mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) {
99312724Snikos.nikoleris@arm.com            DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, "
99412724Snikos.nikoleris@arm.com                    "dropping\n", pkt->getAddr());
99512724Snikos.nikoleris@arm.com            return true;
99612724Snikos.nikoleris@arm.com        }
99712724Snikos.nikoleris@arm.com
99812724Snikos.nikoleris@arm.com        if (!blk) {
99912724Snikos.nikoleris@arm.com            // need to do a replacement
100012754Sodanrc@yahoo.com.br            blk = allocateBlock(pkt, writebacks);
100112724Snikos.nikoleris@arm.com            if (!blk) {
100212724Snikos.nikoleris@arm.com                // no replaceable block available: give up, fwd to next level.
100312724Snikos.nikoleris@arm.com                incMissCount(pkt);
100412724Snikos.nikoleris@arm.com                return false;
100512724Snikos.nikoleris@arm.com            }
100612724Snikos.nikoleris@arm.com
100712724Snikos.nikoleris@arm.com            blk->status |= (BlkValid | BlkReadable);
100812724Snikos.nikoleris@arm.com        }
100912724Snikos.nikoleris@arm.com        // only mark the block dirty if we got a writeback command,
101012724Snikos.nikoleris@arm.com        // and leave it as is for a clean writeback
101112724Snikos.nikoleris@arm.com        if (pkt->cmd == MemCmd::WritebackDirty) {
101212724Snikos.nikoleris@arm.com            // TODO: the coherent cache can assert(!blk->isDirty());
101312724Snikos.nikoleris@arm.com            blk->status |= BlkDirty;
101412724Snikos.nikoleris@arm.com        }
101512724Snikos.nikoleris@arm.com        // if the packet does not have sharers, it is passing
101612724Snikos.nikoleris@arm.com        // writable, and we got the writeback in Modified or Exclusive
101712724Snikos.nikoleris@arm.com        // state, if not we are in the Owned or Shared state
101812724Snikos.nikoleris@arm.com        if (!pkt->hasSharers()) {
101912724Snikos.nikoleris@arm.com            blk->status |= BlkWritable;
102012724Snikos.nikoleris@arm.com        }
102112724Snikos.nikoleris@arm.com        // nothing else to do; writeback doesn't expect response
102212724Snikos.nikoleris@arm.com        assert(!pkt->needsResponse());
102312724Snikos.nikoleris@arm.com        pkt->writeDataToBlock(blk->data, blkSize);
102412724Snikos.nikoleris@arm.com        DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
102512724Snikos.nikoleris@arm.com        incHitCount(pkt);
102612724Snikos.nikoleris@arm.com        // populate the time when the block will be ready to access.
102712724Snikos.nikoleris@arm.com        blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
102812724Snikos.nikoleris@arm.com            pkt->payloadDelay;
102912724Snikos.nikoleris@arm.com        return true;
103012724Snikos.nikoleris@arm.com    } else if (pkt->cmd == MemCmd::CleanEvict) {
103112724Snikos.nikoleris@arm.com        if (blk) {
103212724Snikos.nikoleris@arm.com            // Found the block in the tags, need to stop CleanEvict from
103312724Snikos.nikoleris@arm.com            // propagating further down the hierarchy. Returning true will
103412724Snikos.nikoleris@arm.com            // treat the CleanEvict like a satisfied write request and delete
103512724Snikos.nikoleris@arm.com            // it.
103612724Snikos.nikoleris@arm.com            return true;
103712724Snikos.nikoleris@arm.com        }
103812724Snikos.nikoleris@arm.com        // We didn't find the block here, propagate the CleanEvict further
103912724Snikos.nikoleris@arm.com        // down the memory hierarchy. Returning false will treat the CleanEvict
104012724Snikos.nikoleris@arm.com        // like a Writeback which could not find a replaceable block so has to
104112724Snikos.nikoleris@arm.com        // go to next level.
104212724Snikos.nikoleris@arm.com        return false;
104312724Snikos.nikoleris@arm.com    } else if (pkt->cmd == MemCmd::WriteClean) {
104412724Snikos.nikoleris@arm.com        // WriteClean handling is a special case. We can allocate a
104512724Snikos.nikoleris@arm.com        // block directly if it doesn't exist and we can update the
104612724Snikos.nikoleris@arm.com        // block immediately. The WriteClean transfers the ownership
104712724Snikos.nikoleris@arm.com        // of the block as well.
104812724Snikos.nikoleris@arm.com        assert(blkSize == pkt->getSize());
104912724Snikos.nikoleris@arm.com
105012724Snikos.nikoleris@arm.com        if (!blk) {
105112724Snikos.nikoleris@arm.com            if (pkt->writeThrough()) {
105212724Snikos.nikoleris@arm.com                // if this is a write through packet, we don't try to
105312724Snikos.nikoleris@arm.com                // allocate if the block is not present
105412724Snikos.nikoleris@arm.com                return false;
105512724Snikos.nikoleris@arm.com            } else {
105612724Snikos.nikoleris@arm.com                // a writeback that misses needs to allocate a new block
105712754Sodanrc@yahoo.com.br                blk = allocateBlock(pkt, writebacks);
105812724Snikos.nikoleris@arm.com                if (!blk) {
105912724Snikos.nikoleris@arm.com                    // no replaceable block available: give up, fwd to
106012724Snikos.nikoleris@arm.com                    // next level.
106112724Snikos.nikoleris@arm.com                    incMissCount(pkt);
106212724Snikos.nikoleris@arm.com                    return false;
106312724Snikos.nikoleris@arm.com                }
106412724Snikos.nikoleris@arm.com
106512724Snikos.nikoleris@arm.com                blk->status |= (BlkValid | BlkReadable);
106612724Snikos.nikoleris@arm.com            }
106712724Snikos.nikoleris@arm.com        }
106812724Snikos.nikoleris@arm.com
106912724Snikos.nikoleris@arm.com        // at this point either this is a writeback or a write-through
107012724Snikos.nikoleris@arm.com        // write clean operation and the block is already in this
107112724Snikos.nikoleris@arm.com        // cache, we need to update the data and the block flags
107212724Snikos.nikoleris@arm.com        assert(blk);
107312724Snikos.nikoleris@arm.com        // TODO: the coherent cache can assert(!blk->isDirty());
107412724Snikos.nikoleris@arm.com        if (!pkt->writeThrough()) {
107512724Snikos.nikoleris@arm.com            blk->status |= BlkDirty;
107612724Snikos.nikoleris@arm.com        }
107712724Snikos.nikoleris@arm.com        // nothing else to do; writeback doesn't expect response
107812724Snikos.nikoleris@arm.com        assert(!pkt->needsResponse());
107912724Snikos.nikoleris@arm.com        pkt->writeDataToBlock(blk->data, blkSize);
108012724Snikos.nikoleris@arm.com        DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
108112724Snikos.nikoleris@arm.com
108212724Snikos.nikoleris@arm.com        incHitCount(pkt);
108312724Snikos.nikoleris@arm.com        // populate the time when the block will be ready to access.
108412724Snikos.nikoleris@arm.com        blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
108512724Snikos.nikoleris@arm.com            pkt->payloadDelay;
108612724Snikos.nikoleris@arm.com        // if this a write-through packet it will be sent to cache
108712724Snikos.nikoleris@arm.com        // below
108812724Snikos.nikoleris@arm.com        return !pkt->writeThrough();
108912724Snikos.nikoleris@arm.com    } else if (blk && (pkt->needsWritable() ? blk->isWritable() :
109012724Snikos.nikoleris@arm.com                       blk->isReadable())) {
109112724Snikos.nikoleris@arm.com        // OK to satisfy access
109212724Snikos.nikoleris@arm.com        incHitCount(pkt);
109312724Snikos.nikoleris@arm.com        satisfyRequest(pkt, blk);
109412724Snikos.nikoleris@arm.com        maintainClusivity(pkt->fromCache(), blk);
109512724Snikos.nikoleris@arm.com
109612724Snikos.nikoleris@arm.com        return true;
109712724Snikos.nikoleris@arm.com    }
109812724Snikos.nikoleris@arm.com
109912724Snikos.nikoleris@arm.com    // Can't satisfy access normally... either no block (blk == nullptr)
110012724Snikos.nikoleris@arm.com    // or have block but need writable
110112724Snikos.nikoleris@arm.com
110212724Snikos.nikoleris@arm.com    incMissCount(pkt);
110312724Snikos.nikoleris@arm.com
110412724Snikos.nikoleris@arm.com    if (!blk && pkt->isLLSC() && pkt->isWrite()) {
110512724Snikos.nikoleris@arm.com        // complete miss on store conditional... just give up now
110612724Snikos.nikoleris@arm.com        pkt->req->setExtraData(0);
110712724Snikos.nikoleris@arm.com        return true;
110812724Snikos.nikoleris@arm.com    }
110912724Snikos.nikoleris@arm.com
111012724Snikos.nikoleris@arm.com    return false;
111112724Snikos.nikoleris@arm.com}
111212724Snikos.nikoleris@arm.com
111312724Snikos.nikoleris@arm.comvoid
111412724Snikos.nikoleris@arm.comBaseCache::maintainClusivity(bool from_cache, CacheBlk *blk)
111512724Snikos.nikoleris@arm.com{
111612724Snikos.nikoleris@arm.com    if (from_cache && blk && blk->isValid() && !blk->isDirty() &&
111712724Snikos.nikoleris@arm.com        clusivity == Enums::mostly_excl) {
111812724Snikos.nikoleris@arm.com        // if we have responded to a cache, and our block is still
111912724Snikos.nikoleris@arm.com        // valid, but not dirty, and this cache is mostly exclusive
112012724Snikos.nikoleris@arm.com        // with respect to the cache above, drop the block
112112724Snikos.nikoleris@arm.com        invalidateBlock(blk);
112212724Snikos.nikoleris@arm.com    }
112312724Snikos.nikoleris@arm.com}
112412724Snikos.nikoleris@arm.com
112512724Snikos.nikoleris@arm.comCacheBlk*
112612724Snikos.nikoleris@arm.comBaseCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks,
112712724Snikos.nikoleris@arm.com                      bool allocate)
112812724Snikos.nikoleris@arm.com{
112913350Snikos.nikoleris@arm.com    assert(pkt->isResponse());
113012724Snikos.nikoleris@arm.com    Addr addr = pkt->getAddr();
113112724Snikos.nikoleris@arm.com    bool is_secure = pkt->isSecure();
113212724Snikos.nikoleris@arm.com#if TRACING_ON
113312724Snikos.nikoleris@arm.com    CacheBlk::State old_state = blk ? blk->status : 0;
113412724Snikos.nikoleris@arm.com#endif
113512724Snikos.nikoleris@arm.com
113612724Snikos.nikoleris@arm.com    // When handling a fill, we should have no writes to this line.
113712724Snikos.nikoleris@arm.com    assert(addr == pkt->getBlockAddr(blkSize));
113812724Snikos.nikoleris@arm.com    assert(!writeBuffer.findMatch(addr, is_secure));
113912724Snikos.nikoleris@arm.com
114012724Snikos.nikoleris@arm.com    if (!blk) {
114112724Snikos.nikoleris@arm.com        // better have read new data...
114213350Snikos.nikoleris@arm.com        assert(pkt->hasData() || pkt->cmd == MemCmd::InvalidateResp);
114312724Snikos.nikoleris@arm.com
114412724Snikos.nikoleris@arm.com        // need to do a replacement if allocating, otherwise we stick
114512724Snikos.nikoleris@arm.com        // with the temporary storage
114612754Sodanrc@yahoo.com.br        blk = allocate ? allocateBlock(pkt, writebacks) : nullptr;
114712724Snikos.nikoleris@arm.com
114812724Snikos.nikoleris@arm.com        if (!blk) {
114912724Snikos.nikoleris@arm.com            // No replaceable block or a mostly exclusive
115012724Snikos.nikoleris@arm.com            // cache... just use temporary storage to complete the
115112724Snikos.nikoleris@arm.com            // current request and then get rid of it
115212724Snikos.nikoleris@arm.com            assert(!tempBlock->isValid());
115312724Snikos.nikoleris@arm.com            blk = tempBlock;
115412730Sodanrc@yahoo.com.br            tempBlock->insert(addr, is_secure);
115512724Snikos.nikoleris@arm.com            DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr,
115612724Snikos.nikoleris@arm.com                    is_secure ? "s" : "ns");
115712724Snikos.nikoleris@arm.com        }
115812724Snikos.nikoleris@arm.com
115912724Snikos.nikoleris@arm.com        // we should never be overwriting a valid block
116012724Snikos.nikoleris@arm.com        assert(!blk->isValid());
116112724Snikos.nikoleris@arm.com    } else {
116212724Snikos.nikoleris@arm.com        // existing block... probably an upgrade
116312747Sodanrc@yahoo.com.br        assert(regenerateBlkAddr(blk) == addr);
116412729Sodanrc@yahoo.com.br        assert(blk->isSecure() == is_secure);
116512724Snikos.nikoleris@arm.com        // either we're getting new data or the block should already be valid
116612724Snikos.nikoleris@arm.com        assert(pkt->hasData() || blk->isValid());
116712724Snikos.nikoleris@arm.com        // don't clear block status... if block is already dirty we
116812724Snikos.nikoleris@arm.com        // don't want to lose that
116912724Snikos.nikoleris@arm.com    }
117012724Snikos.nikoleris@arm.com
117112724Snikos.nikoleris@arm.com    blk->status |= BlkValid | BlkReadable;
117212724Snikos.nikoleris@arm.com
117312724Snikos.nikoleris@arm.com    // sanity check for whole-line writes, which should always be
117412724Snikos.nikoleris@arm.com    // marked as writable as part of the fill, and then later marked
117512724Snikos.nikoleris@arm.com    // dirty as part of satisfyRequest
117613350Snikos.nikoleris@arm.com    if (pkt->cmd == MemCmd::InvalidateResp) {
117712724Snikos.nikoleris@arm.com        assert(!pkt->hasSharers());
117812724Snikos.nikoleris@arm.com    }
117912724Snikos.nikoleris@arm.com
118012724Snikos.nikoleris@arm.com    // here we deal with setting the appropriate state of the line,
118112724Snikos.nikoleris@arm.com    // and we start by looking at the hasSharers flag, and ignore the
118212724Snikos.nikoleris@arm.com    // cacheResponding flag (normally signalling dirty data) if the
118312724Snikos.nikoleris@arm.com    // packet has sharers, thus the line is never allocated as Owned
118412724Snikos.nikoleris@arm.com    // (dirty but not writable), and always ends up being either
118512724Snikos.nikoleris@arm.com    // Shared, Exclusive or Modified, see Packet::setCacheResponding
118612724Snikos.nikoleris@arm.com    // for more details
118712724Snikos.nikoleris@arm.com    if (!pkt->hasSharers()) {
118812724Snikos.nikoleris@arm.com        // we could get a writable line from memory (rather than a
118912724Snikos.nikoleris@arm.com        // cache) even in a read-only cache, note that we set this bit
119012724Snikos.nikoleris@arm.com        // even for a read-only cache, possibly revisit this decision
119112724Snikos.nikoleris@arm.com        blk->status |= BlkWritable;
119212724Snikos.nikoleris@arm.com
119312724Snikos.nikoleris@arm.com        // check if we got this via cache-to-cache transfer (i.e., from a
119412724Snikos.nikoleris@arm.com        // cache that had the block in Modified or Owned state)
119512724Snikos.nikoleris@arm.com        if (pkt->cacheResponding()) {
119612724Snikos.nikoleris@arm.com            // we got the block in Modified state, and invalidated the
119712724Snikos.nikoleris@arm.com            // owners copy
119812724Snikos.nikoleris@arm.com            blk->status |= BlkDirty;
119912724Snikos.nikoleris@arm.com
120012724Snikos.nikoleris@arm.com            chatty_assert(!isReadOnly, "Should never see dirty snoop response "
120112724Snikos.nikoleris@arm.com                          "in read-only cache %s\n", name());
120212724Snikos.nikoleris@arm.com        }
120312724Snikos.nikoleris@arm.com    }
120412724Snikos.nikoleris@arm.com
120512724Snikos.nikoleris@arm.com    DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n",
120612724Snikos.nikoleris@arm.com            addr, is_secure ? "s" : "ns", old_state, blk->print());
120712724Snikos.nikoleris@arm.com
120812724Snikos.nikoleris@arm.com    // if we got new data, copy it in (checking for a read response
120912724Snikos.nikoleris@arm.com    // and a response that has data is the same in the end)
121012724Snikos.nikoleris@arm.com    if (pkt->isRead()) {
121112724Snikos.nikoleris@arm.com        // sanity checks
121212724Snikos.nikoleris@arm.com        assert(pkt->hasData());
121312724Snikos.nikoleris@arm.com        assert(pkt->getSize() == blkSize);
121412724Snikos.nikoleris@arm.com
121512724Snikos.nikoleris@arm.com        pkt->writeDataToBlock(blk->data, blkSize);
121612724Snikos.nikoleris@arm.com    }
121712724Snikos.nikoleris@arm.com    // We pay for fillLatency here.
121812724Snikos.nikoleris@arm.com    blk->whenReady = clockEdge() + fillLatency * clockPeriod() +
121912724Snikos.nikoleris@arm.com        pkt->payloadDelay;
122012724Snikos.nikoleris@arm.com
122112724Snikos.nikoleris@arm.com    return blk;
122212724Snikos.nikoleris@arm.com}
122312724Snikos.nikoleris@arm.com
122412724Snikos.nikoleris@arm.comCacheBlk*
122512754Sodanrc@yahoo.com.brBaseCache::allocateBlock(const PacketPtr pkt, PacketList &writebacks)
122612724Snikos.nikoleris@arm.com{
122712754Sodanrc@yahoo.com.br    // Get address
122812754Sodanrc@yahoo.com.br    const Addr addr = pkt->getAddr();
122912754Sodanrc@yahoo.com.br
123012754Sodanrc@yahoo.com.br    // Get secure bit
123112754Sodanrc@yahoo.com.br    const bool is_secure = pkt->isSecure();
123212754Sodanrc@yahoo.com.br
123312724Snikos.nikoleris@arm.com    // Find replacement victim
123412744Sodanrc@yahoo.com.br    std::vector<CacheBlk*> evict_blks;
123512746Sodanrc@yahoo.com.br    CacheBlk *victim = tags->findVictim(addr, is_secure, evict_blks);
123612724Snikos.nikoleris@arm.com
123712724Snikos.nikoleris@arm.com    // It is valid to return nullptr if there is no victim
123812744Sodanrc@yahoo.com.br    if (!victim)
123912724Snikos.nikoleris@arm.com        return nullptr;
124012724Snikos.nikoleris@arm.com
124113222Sodanrc@yahoo.com.br    // Print victim block's information
124213222Sodanrc@yahoo.com.br    DPRINTF(CacheRepl, "Replacement victim: %s\n", victim->print());
124313222Sodanrc@yahoo.com.br
124412744Sodanrc@yahoo.com.br    // Check for transient state allocations. If any of the entries listed
124512744Sodanrc@yahoo.com.br    // for eviction has a transient state, the allocation fails
124612744Sodanrc@yahoo.com.br    for (const auto& blk : evict_blks) {
124712744Sodanrc@yahoo.com.br        if (blk->isValid()) {
124812744Sodanrc@yahoo.com.br            Addr repl_addr = regenerateBlkAddr(blk);
124912744Sodanrc@yahoo.com.br            MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure());
125012744Sodanrc@yahoo.com.br            if (repl_mshr) {
125112744Sodanrc@yahoo.com.br                // must be an outstanding upgrade or clean request
125212744Sodanrc@yahoo.com.br                // on a block we're about to replace...
125312744Sodanrc@yahoo.com.br                assert((!blk->isWritable() && repl_mshr->needsWritable()) ||
125412744Sodanrc@yahoo.com.br                       repl_mshr->isCleaning());
125512724Snikos.nikoleris@arm.com
125612744Sodanrc@yahoo.com.br                // too hard to replace block with transient state
125712744Sodanrc@yahoo.com.br                // allocation failed, block not inserted
125812744Sodanrc@yahoo.com.br                return nullptr;
125912744Sodanrc@yahoo.com.br            }
126012744Sodanrc@yahoo.com.br        }
126112744Sodanrc@yahoo.com.br    }
126212744Sodanrc@yahoo.com.br
126312744Sodanrc@yahoo.com.br    // The victim will be replaced by a new entry, so increase the replacement
126412744Sodanrc@yahoo.com.br    // counter if a valid block is being replaced
126512744Sodanrc@yahoo.com.br    if (victim->isValid()) {
126612744Sodanrc@yahoo.com.br        DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx "
126712744Sodanrc@yahoo.com.br                "(%s): %s\n", regenerateBlkAddr(victim),
126812744Sodanrc@yahoo.com.br                victim->isSecure() ? "s" : "ns",
126912744Sodanrc@yahoo.com.br                addr, is_secure ? "s" : "ns",
127012744Sodanrc@yahoo.com.br                victim->isDirty() ? "writeback" : "clean");
127112744Sodanrc@yahoo.com.br
127212744Sodanrc@yahoo.com.br        replacements++;
127312744Sodanrc@yahoo.com.br    }
127412744Sodanrc@yahoo.com.br
127512744Sodanrc@yahoo.com.br    // Evict valid blocks associated to this victim block
127612744Sodanrc@yahoo.com.br    for (const auto& blk : evict_blks) {
127712744Sodanrc@yahoo.com.br        if (blk->isValid()) {
127812724Snikos.nikoleris@arm.com            if (blk->wasPrefetched()) {
127912724Snikos.nikoleris@arm.com                unusedPrefetches++;
128012724Snikos.nikoleris@arm.com            }
128112744Sodanrc@yahoo.com.br
128212724Snikos.nikoleris@arm.com            evictBlock(blk, writebacks);
128312724Snikos.nikoleris@arm.com        }
128412724Snikos.nikoleris@arm.com    }
128512724Snikos.nikoleris@arm.com
128612754Sodanrc@yahoo.com.br    // Insert new block at victimized entry
128713215Sodanrc@yahoo.com.br    tags->insertBlock(addr, is_secure, pkt->req->masterId(),
128813215Sodanrc@yahoo.com.br                      pkt->req->taskId(), victim);
128912754Sodanrc@yahoo.com.br
129012744Sodanrc@yahoo.com.br    return victim;
129112724Snikos.nikoleris@arm.com}
129212724Snikos.nikoleris@arm.com
129312724Snikos.nikoleris@arm.comvoid
129412724Snikos.nikoleris@arm.comBaseCache::invalidateBlock(CacheBlk *blk)
129512724Snikos.nikoleris@arm.com{
129613376Sodanrc@yahoo.com.br    // If handling a block present in the Tags, let it do its invalidation
129713376Sodanrc@yahoo.com.br    // process, which will update stats and invalidate the block itself
129813376Sodanrc@yahoo.com.br    if (blk != tempBlock) {
129912724Snikos.nikoleris@arm.com        tags->invalidate(blk);
130013376Sodanrc@yahoo.com.br    } else {
130113376Sodanrc@yahoo.com.br        tempBlock->invalidate();
130213376Sodanrc@yahoo.com.br    }
130312724Snikos.nikoleris@arm.com}
130412724Snikos.nikoleris@arm.com
130513358Sodanrc@yahoo.com.brvoid
130613358Sodanrc@yahoo.com.brBaseCache::evictBlock(CacheBlk *blk, PacketList &writebacks)
130713358Sodanrc@yahoo.com.br{
130813358Sodanrc@yahoo.com.br    PacketPtr pkt = evictBlock(blk);
130913358Sodanrc@yahoo.com.br    if (pkt) {
131013358Sodanrc@yahoo.com.br        writebacks.push_back(pkt);
131113358Sodanrc@yahoo.com.br    }
131213358Sodanrc@yahoo.com.br}
131313358Sodanrc@yahoo.com.br
131412724Snikos.nikoleris@arm.comPacketPtr
131512724Snikos.nikoleris@arm.comBaseCache::writebackBlk(CacheBlk *blk)
131612724Snikos.nikoleris@arm.com{
131712724Snikos.nikoleris@arm.com    chatty_assert(!isReadOnly || writebackClean,
131812724Snikos.nikoleris@arm.com                  "Writeback from read-only cache");
131912724Snikos.nikoleris@arm.com    assert(blk && blk->isValid() && (blk->isDirty() || writebackClean));
132012724Snikos.nikoleris@arm.com
132112724Snikos.nikoleris@arm.com    writebacks[Request::wbMasterId]++;
132212724Snikos.nikoleris@arm.com
132312749Sgiacomo.travaglini@arm.com    RequestPtr req = std::make_shared<Request>(
132412749Sgiacomo.travaglini@arm.com        regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId);
132512749Sgiacomo.travaglini@arm.com
132612724Snikos.nikoleris@arm.com    if (blk->isSecure())
132712724Snikos.nikoleris@arm.com        req->setFlags(Request::SECURE);
132812724Snikos.nikoleris@arm.com
132912724Snikos.nikoleris@arm.com    req->taskId(blk->task_id);
133012724Snikos.nikoleris@arm.com
133112724Snikos.nikoleris@arm.com    PacketPtr pkt =
133212724Snikos.nikoleris@arm.com        new Packet(req, blk->isDirty() ?
133312724Snikos.nikoleris@arm.com                   MemCmd::WritebackDirty : MemCmd::WritebackClean);
133412724Snikos.nikoleris@arm.com
133512724Snikos.nikoleris@arm.com    DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n",
133612724Snikos.nikoleris@arm.com            pkt->print(), blk->isWritable(), blk->isDirty());
133712724Snikos.nikoleris@arm.com
133812724Snikos.nikoleris@arm.com    if (blk->isWritable()) {
133912724Snikos.nikoleris@arm.com        // not asserting shared means we pass the block in modified
134012724Snikos.nikoleris@arm.com        // state, mark our own block non-writeable
134112724Snikos.nikoleris@arm.com        blk->status &= ~BlkWritable;
134212724Snikos.nikoleris@arm.com    } else {
134312724Snikos.nikoleris@arm.com        // we are in the Owned state, tell the receiver
134412724Snikos.nikoleris@arm.com        pkt->setHasSharers();
134512724Snikos.nikoleris@arm.com    }
134612724Snikos.nikoleris@arm.com
134712724Snikos.nikoleris@arm.com    // make sure the block is not marked dirty
134812724Snikos.nikoleris@arm.com    blk->status &= ~BlkDirty;
134912724Snikos.nikoleris@arm.com
135012724Snikos.nikoleris@arm.com    pkt->allocate();
135112724Snikos.nikoleris@arm.com    pkt->setDataFromBlock(blk->data, blkSize);
135212724Snikos.nikoleris@arm.com
135312724Snikos.nikoleris@arm.com    return pkt;
135412724Snikos.nikoleris@arm.com}
135512724Snikos.nikoleris@arm.com
135612724Snikos.nikoleris@arm.comPacketPtr
135712724Snikos.nikoleris@arm.comBaseCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id)
135812724Snikos.nikoleris@arm.com{
135912749Sgiacomo.travaglini@arm.com    RequestPtr req = std::make_shared<Request>(
136012749Sgiacomo.travaglini@arm.com        regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId);
136112749Sgiacomo.travaglini@arm.com
136212724Snikos.nikoleris@arm.com    if (blk->isSecure()) {
136312724Snikos.nikoleris@arm.com        req->setFlags(Request::SECURE);
136412724Snikos.nikoleris@arm.com    }
136512724Snikos.nikoleris@arm.com    req->taskId(blk->task_id);
136612724Snikos.nikoleris@arm.com
136712724Snikos.nikoleris@arm.com    PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id);
136812724Snikos.nikoleris@arm.com
136912724Snikos.nikoleris@arm.com    if (dest) {
137012724Snikos.nikoleris@arm.com        req->setFlags(dest);
137112724Snikos.nikoleris@arm.com        pkt->setWriteThrough();
137212724Snikos.nikoleris@arm.com    }
137312724Snikos.nikoleris@arm.com
137412724Snikos.nikoleris@arm.com    DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(),
137512724Snikos.nikoleris@arm.com            blk->isWritable(), blk->isDirty());
137612724Snikos.nikoleris@arm.com
137712724Snikos.nikoleris@arm.com    if (blk->isWritable()) {
137812724Snikos.nikoleris@arm.com        // not asserting shared means we pass the block in modified
137912724Snikos.nikoleris@arm.com        // state, mark our own block non-writeable
138012724Snikos.nikoleris@arm.com        blk->status &= ~BlkWritable;
138112724Snikos.nikoleris@arm.com    } else {
138212724Snikos.nikoleris@arm.com        // we are in the Owned state, tell the receiver
138312724Snikos.nikoleris@arm.com        pkt->setHasSharers();
138412724Snikos.nikoleris@arm.com    }
138512724Snikos.nikoleris@arm.com
138612724Snikos.nikoleris@arm.com    // make sure the block is not marked dirty
138712724Snikos.nikoleris@arm.com    blk->status &= ~BlkDirty;
138812724Snikos.nikoleris@arm.com
138912724Snikos.nikoleris@arm.com    pkt->allocate();
139012724Snikos.nikoleris@arm.com    pkt->setDataFromBlock(blk->data, blkSize);
139112724Snikos.nikoleris@arm.com
139212724Snikos.nikoleris@arm.com    return pkt;
139312724Snikos.nikoleris@arm.com}
139412724Snikos.nikoleris@arm.com
139512724Snikos.nikoleris@arm.com
139612724Snikos.nikoleris@arm.comvoid
139712724Snikos.nikoleris@arm.comBaseCache::memWriteback()
139812724Snikos.nikoleris@arm.com{
139912728Snikos.nikoleris@arm.com    tags->forEachBlk([this](CacheBlk &blk) { writebackVisitor(blk); });
140012724Snikos.nikoleris@arm.com}
140112724Snikos.nikoleris@arm.com
140212724Snikos.nikoleris@arm.comvoid
140312724Snikos.nikoleris@arm.comBaseCache::memInvalidate()
140412724Snikos.nikoleris@arm.com{
140512728Snikos.nikoleris@arm.com    tags->forEachBlk([this](CacheBlk &blk) { invalidateVisitor(blk); });
140612724Snikos.nikoleris@arm.com}
140712724Snikos.nikoleris@arm.com
140812724Snikos.nikoleris@arm.combool
140912724Snikos.nikoleris@arm.comBaseCache::isDirty() const
141012724Snikos.nikoleris@arm.com{
141112728Snikos.nikoleris@arm.com    return tags->anyBlk([](CacheBlk &blk) { return blk.isDirty(); });
141212724Snikos.nikoleris@arm.com}
141312724Snikos.nikoleris@arm.com
141413416Sjavier.bueno@metempsy.combool
141513416Sjavier.bueno@metempsy.comBaseCache::coalesce() const
141613416Sjavier.bueno@metempsy.com{
141713416Sjavier.bueno@metempsy.com    return writeAllocator && writeAllocator->coalesce();
141813416Sjavier.bueno@metempsy.com}
141913416Sjavier.bueno@metempsy.com
142012728Snikos.nikoleris@arm.comvoid
142112724Snikos.nikoleris@arm.comBaseCache::writebackVisitor(CacheBlk &blk)
142212724Snikos.nikoleris@arm.com{
142312724Snikos.nikoleris@arm.com    if (blk.isDirty()) {
142412724Snikos.nikoleris@arm.com        assert(blk.isValid());
142512724Snikos.nikoleris@arm.com
142612749Sgiacomo.travaglini@arm.com        RequestPtr request = std::make_shared<Request>(
142712749Sgiacomo.travaglini@arm.com            regenerateBlkAddr(&blk), blkSize, 0, Request::funcMasterId);
142812749Sgiacomo.travaglini@arm.com
142912749Sgiacomo.travaglini@arm.com        request->taskId(blk.task_id);
143012724Snikos.nikoleris@arm.com        if (blk.isSecure()) {
143112749Sgiacomo.travaglini@arm.com            request->setFlags(Request::SECURE);
143212724Snikos.nikoleris@arm.com        }
143312724Snikos.nikoleris@arm.com
143412749Sgiacomo.travaglini@arm.com        Packet packet(request, MemCmd::WriteReq);
143512724Snikos.nikoleris@arm.com        packet.dataStatic(blk.data);
143612724Snikos.nikoleris@arm.com
143712724Snikos.nikoleris@arm.com        memSidePort.sendFunctional(&packet);
143812724Snikos.nikoleris@arm.com
143912724Snikos.nikoleris@arm.com        blk.status &= ~BlkDirty;
144012724Snikos.nikoleris@arm.com    }
144112724Snikos.nikoleris@arm.com}
144212724Snikos.nikoleris@arm.com
144312728Snikos.nikoleris@arm.comvoid
144412724Snikos.nikoleris@arm.comBaseCache::invalidateVisitor(CacheBlk &blk)
144512724Snikos.nikoleris@arm.com{
144612724Snikos.nikoleris@arm.com    if (blk.isDirty())
144712724Snikos.nikoleris@arm.com        warn_once("Invalidating dirty cache lines. " \
144812724Snikos.nikoleris@arm.com                  "Expect things to break.\n");
144912724Snikos.nikoleris@arm.com
145012724Snikos.nikoleris@arm.com    if (blk.isValid()) {
145112724Snikos.nikoleris@arm.com        assert(!blk.isDirty());
145212724Snikos.nikoleris@arm.com        invalidateBlock(&blk);
145312724Snikos.nikoleris@arm.com    }
145412724Snikos.nikoleris@arm.com}
145512724Snikos.nikoleris@arm.com
145612724Snikos.nikoleris@arm.comTick
145712724Snikos.nikoleris@arm.comBaseCache::nextQueueReadyTime() const
145812724Snikos.nikoleris@arm.com{
145912724Snikos.nikoleris@arm.com    Tick nextReady = std::min(mshrQueue.nextReadyTime(),
146012724Snikos.nikoleris@arm.com                              writeBuffer.nextReadyTime());
146112724Snikos.nikoleris@arm.com
146212724Snikos.nikoleris@arm.com    // Don't signal prefetch ready time if no MSHRs available
146312724Snikos.nikoleris@arm.com    // Will signal once enoguh MSHRs are deallocated
146412724Snikos.nikoleris@arm.com    if (prefetcher && mshrQueue.canPrefetch()) {
146512724Snikos.nikoleris@arm.com        nextReady = std::min(nextReady,
146612724Snikos.nikoleris@arm.com                             prefetcher->nextPrefetchReadyTime());
146712724Snikos.nikoleris@arm.com    }
146812724Snikos.nikoleris@arm.com
146912724Snikos.nikoleris@arm.com    return nextReady;
147012724Snikos.nikoleris@arm.com}
147112724Snikos.nikoleris@arm.com
147212724Snikos.nikoleris@arm.com
147312724Snikos.nikoleris@arm.combool
147412724Snikos.nikoleris@arm.comBaseCache::sendMSHRQueuePacket(MSHR* mshr)
147512724Snikos.nikoleris@arm.com{
147612724Snikos.nikoleris@arm.com    assert(mshr);
147712724Snikos.nikoleris@arm.com
147812724Snikos.nikoleris@arm.com    // use request from 1st target
147912724Snikos.nikoleris@arm.com    PacketPtr tgt_pkt = mshr->getTarget()->pkt;
148012724Snikos.nikoleris@arm.com
148112724Snikos.nikoleris@arm.com    DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print());
148212724Snikos.nikoleris@arm.com
148313352Snikos.nikoleris@arm.com    // if the cache is in write coalescing mode or (additionally) in
148413352Snikos.nikoleris@arm.com    // no allocation mode, and we have a write packet with an MSHR
148513352Snikos.nikoleris@arm.com    // that is not a whole-line write (due to incompatible flags etc),
148613352Snikos.nikoleris@arm.com    // then reset the write mode
148713352Snikos.nikoleris@arm.com    if (writeAllocator && writeAllocator->coalesce() && tgt_pkt->isWrite()) {
148813352Snikos.nikoleris@arm.com        if (!mshr->isWholeLineWrite()) {
148913352Snikos.nikoleris@arm.com            // if we are currently write coalescing, hold on the
149013352Snikos.nikoleris@arm.com            // MSHR as many cycles extra as we need to completely
149113352Snikos.nikoleris@arm.com            // write a cache line
149213352Snikos.nikoleris@arm.com            if (writeAllocator->delay(mshr->blkAddr)) {
149313352Snikos.nikoleris@arm.com                Tick delay = blkSize / tgt_pkt->getSize() * clockPeriod();
149413352Snikos.nikoleris@arm.com                DPRINTF(CacheVerbose, "Delaying pkt %s %llu ticks to allow "
149513352Snikos.nikoleris@arm.com                        "for write coalescing\n", tgt_pkt->print(), delay);
149613352Snikos.nikoleris@arm.com                mshrQueue.delay(mshr, delay);
149713352Snikos.nikoleris@arm.com                return false;
149813352Snikos.nikoleris@arm.com            } else {
149913352Snikos.nikoleris@arm.com                writeAllocator->reset();
150013352Snikos.nikoleris@arm.com            }
150113352Snikos.nikoleris@arm.com        } else {
150213352Snikos.nikoleris@arm.com            writeAllocator->resetDelay(mshr->blkAddr);
150313352Snikos.nikoleris@arm.com        }
150413352Snikos.nikoleris@arm.com    }
150513352Snikos.nikoleris@arm.com
150612724Snikos.nikoleris@arm.com    CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure);
150712724Snikos.nikoleris@arm.com
150812724Snikos.nikoleris@arm.com    // either a prefetch that is not present upstream, or a normal
150912724Snikos.nikoleris@arm.com    // MSHR request, proceed to get the packet to send downstream
151013350Snikos.nikoleris@arm.com    PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable(),
151113350Snikos.nikoleris@arm.com                                     mshr->isWholeLineWrite());
151212724Snikos.nikoleris@arm.com
151312724Snikos.nikoleris@arm.com    mshr->isForward = (pkt == nullptr);
151412724Snikos.nikoleris@arm.com
151512724Snikos.nikoleris@arm.com    if (mshr->isForward) {
151612724Snikos.nikoleris@arm.com        // not a cache block request, but a response is expected
151712724Snikos.nikoleris@arm.com        // make copy of current packet to forward, keep current
151812724Snikos.nikoleris@arm.com        // copy for response handling
151912724Snikos.nikoleris@arm.com        pkt = new Packet(tgt_pkt, false, true);
152012724Snikos.nikoleris@arm.com        assert(!pkt->isWrite());
152112724Snikos.nikoleris@arm.com    }
152212724Snikos.nikoleris@arm.com
152312724Snikos.nikoleris@arm.com    // play it safe and append (rather than set) the sender state,
152412724Snikos.nikoleris@arm.com    // as forwarded packets may already have existing state
152512724Snikos.nikoleris@arm.com    pkt->pushSenderState(mshr);
152612724Snikos.nikoleris@arm.com
152712724Snikos.nikoleris@arm.com    if (pkt->isClean() && blk && blk->isDirty()) {
152812724Snikos.nikoleris@arm.com        // A cache clean opearation is looking for a dirty block. Mark
152912724Snikos.nikoleris@arm.com        // the packet so that the destination xbar can determine that
153012724Snikos.nikoleris@arm.com        // there will be a follow-up write packet as well.
153112724Snikos.nikoleris@arm.com        pkt->setSatisfied();
153212724Snikos.nikoleris@arm.com    }
153312724Snikos.nikoleris@arm.com
153412724Snikos.nikoleris@arm.com    if (!memSidePort.sendTimingReq(pkt)) {
153512724Snikos.nikoleris@arm.com        // we are awaiting a retry, but we
153612724Snikos.nikoleris@arm.com        // delete the packet and will be creating a new packet
153712724Snikos.nikoleris@arm.com        // when we get the opportunity
153812724Snikos.nikoleris@arm.com        delete pkt;
153912724Snikos.nikoleris@arm.com
154012724Snikos.nikoleris@arm.com        // note that we have now masked any requestBus and
154112724Snikos.nikoleris@arm.com        // schedSendEvent (we will wait for a retry before
154212724Snikos.nikoleris@arm.com        // doing anything), and this is so even if we do not
154312724Snikos.nikoleris@arm.com        // care about this packet and might override it before
154412724Snikos.nikoleris@arm.com        // it gets retried
154512724Snikos.nikoleris@arm.com        return true;
154612724Snikos.nikoleris@arm.com    } else {
154712724Snikos.nikoleris@arm.com        // As part of the call to sendTimingReq the packet is
154812724Snikos.nikoleris@arm.com        // forwarded to all neighbouring caches (and any caches
154912724Snikos.nikoleris@arm.com        // above them) as a snoop. Thus at this point we know if
155012724Snikos.nikoleris@arm.com        // any of the neighbouring caches are responding, and if
155112724Snikos.nikoleris@arm.com        // so, we know it is dirty, and we can determine if it is
155212724Snikos.nikoleris@arm.com        // being passed as Modified, making our MSHR the ordering
155312724Snikos.nikoleris@arm.com        // point
155412724Snikos.nikoleris@arm.com        bool pending_modified_resp = !pkt->hasSharers() &&
155512724Snikos.nikoleris@arm.com            pkt->cacheResponding();
155612724Snikos.nikoleris@arm.com        markInService(mshr, pending_modified_resp);
155712724Snikos.nikoleris@arm.com
155812724Snikos.nikoleris@arm.com        if (pkt->isClean() && blk && blk->isDirty()) {
155912724Snikos.nikoleris@arm.com            // A cache clean opearation is looking for a dirty
156012724Snikos.nikoleris@arm.com            // block. If a dirty block is encountered a WriteClean
156112724Snikos.nikoleris@arm.com            // will update any copies to the path to the memory
156212724Snikos.nikoleris@arm.com            // until the point of reference.
156312724Snikos.nikoleris@arm.com            DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n",
156412724Snikos.nikoleris@arm.com                    __func__, pkt->print(), blk->print());
156512724Snikos.nikoleris@arm.com            PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(),
156612724Snikos.nikoleris@arm.com                                             pkt->id);
156712724Snikos.nikoleris@arm.com            PacketList writebacks;
156812724Snikos.nikoleris@arm.com            writebacks.push_back(wb_pkt);
156912724Snikos.nikoleris@arm.com            doWritebacks(writebacks, 0);
157012724Snikos.nikoleris@arm.com        }
157112724Snikos.nikoleris@arm.com
157212724Snikos.nikoleris@arm.com        return false;
157312724Snikos.nikoleris@arm.com    }
157412724Snikos.nikoleris@arm.com}
157512724Snikos.nikoleris@arm.com
157612724Snikos.nikoleris@arm.combool
157712724Snikos.nikoleris@arm.comBaseCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry)
157812724Snikos.nikoleris@arm.com{
157912724Snikos.nikoleris@arm.com    assert(wq_entry);
158012724Snikos.nikoleris@arm.com
158112724Snikos.nikoleris@arm.com    // always a single target for write queue entries
158212724Snikos.nikoleris@arm.com    PacketPtr tgt_pkt = wq_entry->getTarget()->pkt;
158312724Snikos.nikoleris@arm.com
158412724Snikos.nikoleris@arm.com    DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print());
158512724Snikos.nikoleris@arm.com
158612724Snikos.nikoleris@arm.com    // forward as is, both for evictions and uncacheable writes
158712724Snikos.nikoleris@arm.com    if (!memSidePort.sendTimingReq(tgt_pkt)) {
158812724Snikos.nikoleris@arm.com        // note that we have now masked any requestBus and
158912724Snikos.nikoleris@arm.com        // schedSendEvent (we will wait for a retry before
159012724Snikos.nikoleris@arm.com        // doing anything), and this is so even if we do not
159112724Snikos.nikoleris@arm.com        // care about this packet and might override it before
159212724Snikos.nikoleris@arm.com        // it gets retried
159312724Snikos.nikoleris@arm.com        return true;
159412724Snikos.nikoleris@arm.com    } else {
159512724Snikos.nikoleris@arm.com        markInService(wq_entry);
159612724Snikos.nikoleris@arm.com        return false;
159712724Snikos.nikoleris@arm.com    }
159812724Snikos.nikoleris@arm.com}
159912724Snikos.nikoleris@arm.com
160012724Snikos.nikoleris@arm.comvoid
160112724Snikos.nikoleris@arm.comBaseCache::serialize(CheckpointOut &cp) const
160212724Snikos.nikoleris@arm.com{
160312724Snikos.nikoleris@arm.com    bool dirty(isDirty());
160412724Snikos.nikoleris@arm.com
160512724Snikos.nikoleris@arm.com    if (dirty) {
160612724Snikos.nikoleris@arm.com        warn("*** The cache still contains dirty data. ***\n");
160712724Snikos.nikoleris@arm.com        warn("    Make sure to drain the system using the correct flags.\n");
160812724Snikos.nikoleris@arm.com        warn("    This checkpoint will not restore correctly " \
160912724Snikos.nikoleris@arm.com             "and dirty data in the cache will be lost!\n");
161012724Snikos.nikoleris@arm.com    }
161112724Snikos.nikoleris@arm.com
161212724Snikos.nikoleris@arm.com    // Since we don't checkpoint the data in the cache, any dirty data
161312724Snikos.nikoleris@arm.com    // will be lost when restoring from a checkpoint of a system that
161412724Snikos.nikoleris@arm.com    // wasn't drained properly. Flag the checkpoint as invalid if the
161512724Snikos.nikoleris@arm.com    // cache contains dirty data.
161612724Snikos.nikoleris@arm.com    bool bad_checkpoint(dirty);
161712724Snikos.nikoleris@arm.com    SERIALIZE_SCALAR(bad_checkpoint);
161812724Snikos.nikoleris@arm.com}
161912724Snikos.nikoleris@arm.com
162012724Snikos.nikoleris@arm.comvoid
162112724Snikos.nikoleris@arm.comBaseCache::unserialize(CheckpointIn &cp)
162212724Snikos.nikoleris@arm.com{
162312724Snikos.nikoleris@arm.com    bool bad_checkpoint;
162412724Snikos.nikoleris@arm.com    UNSERIALIZE_SCALAR(bad_checkpoint);
162512724Snikos.nikoleris@arm.com    if (bad_checkpoint) {
162612724Snikos.nikoleris@arm.com        fatal("Restoring from checkpoints with dirty caches is not "
162712724Snikos.nikoleris@arm.com              "supported in the classic memory system. Please remove any "
162812724Snikos.nikoleris@arm.com              "caches or drain them properly before taking checkpoints.\n");
162912724Snikos.nikoleris@arm.com    }
163012724Snikos.nikoleris@arm.com}
163112724Snikos.nikoleris@arm.com
163212724Snikos.nikoleris@arm.comvoid
16332810SN/ABaseCache::regStats()
16342810SN/A{
163511522Sstephan.diestelhorst@arm.com    MemObject::regStats();
163611522Sstephan.diestelhorst@arm.com
16372810SN/A    using namespace Stats;
16382810SN/A
16392810SN/A    // Hit statistics
16404022SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
16414022SN/A        MemCmd cmd(access_idx);
16424022SN/A        const string &cstr = cmd.toString();
16432810SN/A
16442810SN/A        hits[access_idx]
16458833Sdam.sunwoo@arm.com            .init(system->maxMasters())
16462810SN/A            .name(name() + "." + cstr + "_hits")
16472810SN/A            .desc("number of " + cstr + " hits")
16482810SN/A            .flags(total | nozero | nonan)
16492810SN/A            ;
16508833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
16518833Sdam.sunwoo@arm.com            hits[access_idx].subname(i, system->getMasterName(i));
16528833Sdam.sunwoo@arm.com        }
16532810SN/A    }
16542810SN/A
16554871SN/A// These macros make it easier to sum the right subset of commands and
16564871SN/A// to change the subset of commands that are considered "demand" vs
16574871SN/A// "non-demand"
16584871SN/A#define SUM_DEMAND(s) \
165911455Sandreas.hansson@arm.com    (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \
166010885Sandreas.hansson@arm.com     s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq])
16614871SN/A
16624871SN/A// should writebacks be included here?  prior code was inconsistent...
16634871SN/A#define SUM_NON_DEMAND(s) \
166413367Syuetsu.kodama@riken.jp    (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq] + s[MemCmd::SoftPFExReq])
16654871SN/A
16662810SN/A    demandHits
16672810SN/A        .name(name() + ".demand_hits")
16682810SN/A        .desc("number of demand (read+write) hits")
16698833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
16702810SN/A        ;
16714871SN/A    demandHits = SUM_DEMAND(hits);
16728833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
16738833Sdam.sunwoo@arm.com        demandHits.subname(i, system->getMasterName(i));
16748833Sdam.sunwoo@arm.com    }
16752810SN/A
16762810SN/A    overallHits
16772810SN/A        .name(name() + ".overall_hits")
16782810SN/A        .desc("number of overall hits")
16798833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
16802810SN/A        ;
16814871SN/A    overallHits = demandHits + SUM_NON_DEMAND(hits);
16828833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
16838833Sdam.sunwoo@arm.com        overallHits.subname(i, system->getMasterName(i));
16848833Sdam.sunwoo@arm.com    }
16852810SN/A
16862810SN/A    // Miss statistics
16874022SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
16884022SN/A        MemCmd cmd(access_idx);
16894022SN/A        const string &cstr = cmd.toString();
16902810SN/A
16912810SN/A        misses[access_idx]
16928833Sdam.sunwoo@arm.com            .init(system->maxMasters())
16932810SN/A            .name(name() + "." + cstr + "_misses")
16942810SN/A            .desc("number of " + cstr + " misses")
16952810SN/A            .flags(total | nozero | nonan)
16962810SN/A            ;
16978833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
16988833Sdam.sunwoo@arm.com            misses[access_idx].subname(i, system->getMasterName(i));
16998833Sdam.sunwoo@arm.com        }
17002810SN/A    }
17012810SN/A
17022810SN/A    demandMisses
17032810SN/A        .name(name() + ".demand_misses")
17042810SN/A        .desc("number of demand (read+write) misses")
17058833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
17062810SN/A        ;
17074871SN/A    demandMisses = SUM_DEMAND(misses);
17088833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
17098833Sdam.sunwoo@arm.com        demandMisses.subname(i, system->getMasterName(i));
17108833Sdam.sunwoo@arm.com    }
17112810SN/A
17122810SN/A    overallMisses
17132810SN/A        .name(name() + ".overall_misses")
17142810SN/A        .desc("number of overall misses")
17158833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
17162810SN/A        ;
17174871SN/A    overallMisses = demandMisses + SUM_NON_DEMAND(misses);
17188833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
17198833Sdam.sunwoo@arm.com        overallMisses.subname(i, system->getMasterName(i));
17208833Sdam.sunwoo@arm.com    }
17212810SN/A
17222810SN/A    // Miss latency statistics
17234022SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
17244022SN/A        MemCmd cmd(access_idx);
17254022SN/A        const string &cstr = cmd.toString();
17262810SN/A
17272810SN/A        missLatency[access_idx]
17288833Sdam.sunwoo@arm.com            .init(system->maxMasters())
17292810SN/A            .name(name() + "." + cstr + "_miss_latency")
17302810SN/A            .desc("number of " + cstr + " miss cycles")
17312810SN/A            .flags(total | nozero | nonan)
17322810SN/A            ;
17338833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
17348833Sdam.sunwoo@arm.com            missLatency[access_idx].subname(i, system->getMasterName(i));
17358833Sdam.sunwoo@arm.com        }
17362810SN/A    }
17372810SN/A
17382810SN/A    demandMissLatency
17392810SN/A        .name(name() + ".demand_miss_latency")
17402810SN/A        .desc("number of demand (read+write) miss cycles")
17418833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
17422810SN/A        ;
17434871SN/A    demandMissLatency = SUM_DEMAND(missLatency);
17448833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
17458833Sdam.sunwoo@arm.com        demandMissLatency.subname(i, system->getMasterName(i));
17468833Sdam.sunwoo@arm.com    }
17472810SN/A
17482810SN/A    overallMissLatency
17492810SN/A        .name(name() + ".overall_miss_latency")
17502810SN/A        .desc("number of overall miss cycles")
17518833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
17522810SN/A        ;
17534871SN/A    overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency);
17548833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
17558833Sdam.sunwoo@arm.com        overallMissLatency.subname(i, system->getMasterName(i));
17568833Sdam.sunwoo@arm.com    }
17572810SN/A
17582810SN/A    // access formulas
17594022SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
17604022SN/A        MemCmd cmd(access_idx);
17614022SN/A        const string &cstr = cmd.toString();
17622810SN/A
17632810SN/A        accesses[access_idx]
17642810SN/A            .name(name() + "." + cstr + "_accesses")
17652810SN/A            .desc("number of " + cstr + " accesses(hits+misses)")
17662810SN/A            .flags(total | nozero | nonan)
17672810SN/A            ;
17688833Sdam.sunwoo@arm.com        accesses[access_idx] = hits[access_idx] + misses[access_idx];
17692810SN/A
17708833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
17718833Sdam.sunwoo@arm.com            accesses[access_idx].subname(i, system->getMasterName(i));
17728833Sdam.sunwoo@arm.com        }
17732810SN/A    }
17742810SN/A
17752810SN/A    demandAccesses
17762810SN/A        .name(name() + ".demand_accesses")
17772810SN/A        .desc("number of demand (read+write) accesses")
17788833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
17792810SN/A        ;
17802810SN/A    demandAccesses = demandHits + demandMisses;
17818833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
17828833Sdam.sunwoo@arm.com        demandAccesses.subname(i, system->getMasterName(i));
17838833Sdam.sunwoo@arm.com    }
17842810SN/A
17852810SN/A    overallAccesses
17862810SN/A        .name(name() + ".overall_accesses")
17872810SN/A        .desc("number of overall (read+write) accesses")
17888833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
17892810SN/A        ;
17902810SN/A    overallAccesses = overallHits + overallMisses;
17918833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
17928833Sdam.sunwoo@arm.com        overallAccesses.subname(i, system->getMasterName(i));
17938833Sdam.sunwoo@arm.com    }
17942810SN/A
17952810SN/A    // miss rate formulas
17964022SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
17974022SN/A        MemCmd cmd(access_idx);
17984022SN/A        const string &cstr = cmd.toString();
17992810SN/A
18002810SN/A        missRate[access_idx]
18012810SN/A            .name(name() + "." + cstr + "_miss_rate")
18022810SN/A            .desc("miss rate for " + cstr + " accesses")
18032810SN/A            .flags(total | nozero | nonan)
18042810SN/A            ;
18058833Sdam.sunwoo@arm.com        missRate[access_idx] = misses[access_idx] / accesses[access_idx];
18062810SN/A
18078833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
18088833Sdam.sunwoo@arm.com            missRate[access_idx].subname(i, system->getMasterName(i));
18098833Sdam.sunwoo@arm.com        }
18102810SN/A    }
18112810SN/A
18122810SN/A    demandMissRate
18132810SN/A        .name(name() + ".demand_miss_rate")
18142810SN/A        .desc("miss rate for demand accesses")
18158833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
18162810SN/A        ;
18172810SN/A    demandMissRate = demandMisses / demandAccesses;
18188833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
18198833Sdam.sunwoo@arm.com        demandMissRate.subname(i, system->getMasterName(i));
18208833Sdam.sunwoo@arm.com    }
18212810SN/A
18222810SN/A    overallMissRate
18232810SN/A        .name(name() + ".overall_miss_rate")
18242810SN/A        .desc("miss rate for overall accesses")
18258833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
18262810SN/A        ;
18272810SN/A    overallMissRate = overallMisses / overallAccesses;
18288833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
18298833Sdam.sunwoo@arm.com        overallMissRate.subname(i, system->getMasterName(i));
18308833Sdam.sunwoo@arm.com    }
18312810SN/A
18322810SN/A    // miss latency formulas
18334022SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
18344022SN/A        MemCmd cmd(access_idx);
18354022SN/A        const string &cstr = cmd.toString();
18362810SN/A
18372810SN/A        avgMissLatency[access_idx]
18382810SN/A            .name(name() + "." + cstr + "_avg_miss_latency")
18392810SN/A            .desc("average " + cstr + " miss latency")
18402810SN/A            .flags(total | nozero | nonan)
18412810SN/A            ;
18422810SN/A        avgMissLatency[access_idx] =
18432810SN/A            missLatency[access_idx] / misses[access_idx];
18448833Sdam.sunwoo@arm.com
18458833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
18468833Sdam.sunwoo@arm.com            avgMissLatency[access_idx].subname(i, system->getMasterName(i));
18478833Sdam.sunwoo@arm.com        }
18482810SN/A    }
18492810SN/A
18502810SN/A    demandAvgMissLatency
18512810SN/A        .name(name() + ".demand_avg_miss_latency")
18522810SN/A        .desc("average overall miss latency")
18538833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
18542810SN/A        ;
18552810SN/A    demandAvgMissLatency = demandMissLatency / demandMisses;
18568833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
18578833Sdam.sunwoo@arm.com        demandAvgMissLatency.subname(i, system->getMasterName(i));
18588833Sdam.sunwoo@arm.com    }
18592810SN/A
18602810SN/A    overallAvgMissLatency
18612810SN/A        .name(name() + ".overall_avg_miss_latency")
18622810SN/A        .desc("average overall miss latency")
18638833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
18642810SN/A        ;
18652810SN/A    overallAvgMissLatency = overallMissLatency / overallMisses;
18668833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
18678833Sdam.sunwoo@arm.com        overallAvgMissLatency.subname(i, system->getMasterName(i));
18688833Sdam.sunwoo@arm.com    }
18692810SN/A
18702810SN/A    blocked_cycles.init(NUM_BLOCKED_CAUSES);
18712810SN/A    blocked_cycles
18722810SN/A        .name(name() + ".blocked_cycles")
18732810SN/A        .desc("number of cycles access was blocked")
18742810SN/A        .subname(Blocked_NoMSHRs, "no_mshrs")
18752810SN/A        .subname(Blocked_NoTargets, "no_targets")
18762810SN/A        ;
18772810SN/A
18782810SN/A
18792810SN/A    blocked_causes.init(NUM_BLOCKED_CAUSES);
18802810SN/A    blocked_causes
18812810SN/A        .name(name() + ".blocked")
18822810SN/A        .desc("number of cycles access was blocked")
18832810SN/A        .subname(Blocked_NoMSHRs, "no_mshrs")
18842810SN/A        .subname(Blocked_NoTargets, "no_targets")
18852810SN/A        ;
18862810SN/A
18872810SN/A    avg_blocked
18882810SN/A        .name(name() + ".avg_blocked_cycles")
18892810SN/A        .desc("average number of cycles each access was blocked")
18902810SN/A        .subname(Blocked_NoMSHRs, "no_mshrs")
18912810SN/A        .subname(Blocked_NoTargets, "no_targets")
18922810SN/A        ;
18932810SN/A
18942810SN/A    avg_blocked = blocked_cycles / blocked_causes;
18952810SN/A
189611436SRekai.GonzalezAlberquilla@arm.com    unusedPrefetches
189711436SRekai.GonzalezAlberquilla@arm.com        .name(name() + ".unused_prefetches")
189811436SRekai.GonzalezAlberquilla@arm.com        .desc("number of HardPF blocks evicted w/o reference")
189911436SRekai.GonzalezAlberquilla@arm.com        .flags(nozero)
190011436SRekai.GonzalezAlberquilla@arm.com        ;
190111436SRekai.GonzalezAlberquilla@arm.com
19024626SN/A    writebacks
19038833Sdam.sunwoo@arm.com        .init(system->maxMasters())
19044626SN/A        .name(name() + ".writebacks")
19054626SN/A        .desc("number of writebacks")
19068833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
19074626SN/A        ;
19088833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
19098833Sdam.sunwoo@arm.com        writebacks.subname(i, system->getMasterName(i));
19108833Sdam.sunwoo@arm.com    }
19114626SN/A
19124626SN/A    // MSHR statistics
19134626SN/A    // MSHR hit statistics
19144626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
19154626SN/A        MemCmd cmd(access_idx);
19164626SN/A        const string &cstr = cmd.toString();
19174626SN/A
19184626SN/A        mshr_hits[access_idx]
19198833Sdam.sunwoo@arm.com            .init(system->maxMasters())
19204626SN/A            .name(name() + "." + cstr + "_mshr_hits")
19214626SN/A            .desc("number of " + cstr + " MSHR hits")
19224626SN/A            .flags(total | nozero | nonan)
19234626SN/A            ;
19248833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
19258833Sdam.sunwoo@arm.com            mshr_hits[access_idx].subname(i, system->getMasterName(i));
19268833Sdam.sunwoo@arm.com        }
19274626SN/A    }
19284626SN/A
19294626SN/A    demandMshrHits
19304626SN/A        .name(name() + ".demand_mshr_hits")
19314626SN/A        .desc("number of demand (read+write) MSHR hits")
19328833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
19334626SN/A        ;
19344871SN/A    demandMshrHits = SUM_DEMAND(mshr_hits);
19358833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
19368833Sdam.sunwoo@arm.com        demandMshrHits.subname(i, system->getMasterName(i));
19378833Sdam.sunwoo@arm.com    }
19384626SN/A
19394626SN/A    overallMshrHits
19404626SN/A        .name(name() + ".overall_mshr_hits")
19414626SN/A        .desc("number of overall MSHR hits")
19428833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
19434626SN/A        ;
19444871SN/A    overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits);
19458833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
19468833Sdam.sunwoo@arm.com        overallMshrHits.subname(i, system->getMasterName(i));
19478833Sdam.sunwoo@arm.com    }
19484626SN/A
19494626SN/A    // MSHR miss statistics
19504626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
19514626SN/A        MemCmd cmd(access_idx);
19524626SN/A        const string &cstr = cmd.toString();
19534626SN/A
19544626SN/A        mshr_misses[access_idx]
19558833Sdam.sunwoo@arm.com            .init(system->maxMasters())
19564626SN/A            .name(name() + "." + cstr + "_mshr_misses")
19574626SN/A            .desc("number of " + cstr + " MSHR misses")
19584626SN/A            .flags(total | nozero | nonan)
19594626SN/A            ;
19608833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
19618833Sdam.sunwoo@arm.com            mshr_misses[access_idx].subname(i, system->getMasterName(i));
19628833Sdam.sunwoo@arm.com        }
19634626SN/A    }
19644626SN/A
19654626SN/A    demandMshrMisses
19664626SN/A        .name(name() + ".demand_mshr_misses")
19674626SN/A        .desc("number of demand (read+write) MSHR misses")
19688833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
19694626SN/A        ;
19704871SN/A    demandMshrMisses = SUM_DEMAND(mshr_misses);
19718833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
19728833Sdam.sunwoo@arm.com        demandMshrMisses.subname(i, system->getMasterName(i));
19738833Sdam.sunwoo@arm.com    }
19744626SN/A
19754626SN/A    overallMshrMisses
19764626SN/A        .name(name() + ".overall_mshr_misses")
19774626SN/A        .desc("number of overall MSHR misses")
19788833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
19794626SN/A        ;
19804871SN/A    overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses);
19818833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
19828833Sdam.sunwoo@arm.com        overallMshrMisses.subname(i, system->getMasterName(i));
19838833Sdam.sunwoo@arm.com    }
19844626SN/A
19854626SN/A    // MSHR miss latency statistics
19864626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
19874626SN/A        MemCmd cmd(access_idx);
19884626SN/A        const string &cstr = cmd.toString();
19894626SN/A
19904626SN/A        mshr_miss_latency[access_idx]
19918833Sdam.sunwoo@arm.com            .init(system->maxMasters())
19924626SN/A            .name(name() + "." + cstr + "_mshr_miss_latency")
19934626SN/A            .desc("number of " + cstr + " MSHR miss cycles")
19944626SN/A            .flags(total | nozero | nonan)
19954626SN/A            ;
19968833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
19978833Sdam.sunwoo@arm.com            mshr_miss_latency[access_idx].subname(i, system->getMasterName(i));
19988833Sdam.sunwoo@arm.com        }
19994626SN/A    }
20004626SN/A
20014626SN/A    demandMshrMissLatency
20024626SN/A        .name(name() + ".demand_mshr_miss_latency")
20034626SN/A        .desc("number of demand (read+write) MSHR miss cycles")
20048833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
20054626SN/A        ;
20064871SN/A    demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency);
20078833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
20088833Sdam.sunwoo@arm.com        demandMshrMissLatency.subname(i, system->getMasterName(i));
20098833Sdam.sunwoo@arm.com    }
20104626SN/A
20114626SN/A    overallMshrMissLatency
20124626SN/A        .name(name() + ".overall_mshr_miss_latency")
20134626SN/A        .desc("number of overall MSHR miss cycles")
20148833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
20154626SN/A        ;
20164871SN/A    overallMshrMissLatency =
20174871SN/A        demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency);
20188833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
20198833Sdam.sunwoo@arm.com        overallMshrMissLatency.subname(i, system->getMasterName(i));
20208833Sdam.sunwoo@arm.com    }
20214626SN/A
20224626SN/A    // MSHR uncacheable statistics
20234626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
20244626SN/A        MemCmd cmd(access_idx);
20254626SN/A        const string &cstr = cmd.toString();
20264626SN/A
20274626SN/A        mshr_uncacheable[access_idx]
20288833Sdam.sunwoo@arm.com            .init(system->maxMasters())
20294626SN/A            .name(name() + "." + cstr + "_mshr_uncacheable")
20304626SN/A            .desc("number of " + cstr + " MSHR uncacheable")
20314626SN/A            .flags(total | nozero | nonan)
20324626SN/A            ;
20338833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
20348833Sdam.sunwoo@arm.com            mshr_uncacheable[access_idx].subname(i, system->getMasterName(i));
20358833Sdam.sunwoo@arm.com        }
20364626SN/A    }
20374626SN/A
20384626SN/A    overallMshrUncacheable
20394626SN/A        .name(name() + ".overall_mshr_uncacheable_misses")
20404626SN/A        .desc("number of overall MSHR uncacheable misses")
20418833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
20424626SN/A        ;
20434871SN/A    overallMshrUncacheable =
20444871SN/A        SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable);
20458833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
20468833Sdam.sunwoo@arm.com        overallMshrUncacheable.subname(i, system->getMasterName(i));
20478833Sdam.sunwoo@arm.com    }
20484626SN/A
20494626SN/A    // MSHR miss latency statistics
20504626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
20514626SN/A        MemCmd cmd(access_idx);
20524626SN/A        const string &cstr = cmd.toString();
20534626SN/A
20544626SN/A        mshr_uncacheable_lat[access_idx]
20558833Sdam.sunwoo@arm.com            .init(system->maxMasters())
20564626SN/A            .name(name() + "." + cstr + "_mshr_uncacheable_latency")
20574626SN/A            .desc("number of " + cstr + " MSHR uncacheable cycles")
20584626SN/A            .flags(total | nozero | nonan)
20594626SN/A            ;
20608833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
206111483Snikos.nikoleris@arm.com            mshr_uncacheable_lat[access_idx].subname(
206211483Snikos.nikoleris@arm.com                i, system->getMasterName(i));
20638833Sdam.sunwoo@arm.com        }
20644626SN/A    }
20654626SN/A
20664626SN/A    overallMshrUncacheableLatency
20674626SN/A        .name(name() + ".overall_mshr_uncacheable_latency")
20684626SN/A        .desc("number of overall MSHR uncacheable cycles")
20698833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
20704626SN/A        ;
20714871SN/A    overallMshrUncacheableLatency =
20724871SN/A        SUM_DEMAND(mshr_uncacheable_lat) +
20734871SN/A        SUM_NON_DEMAND(mshr_uncacheable_lat);
20748833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
20758833Sdam.sunwoo@arm.com        overallMshrUncacheableLatency.subname(i, system->getMasterName(i));
20768833Sdam.sunwoo@arm.com    }
20774626SN/A
20784626SN/A#if 0
20794626SN/A    // MSHR access formulas
20804626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
20814626SN/A        MemCmd cmd(access_idx);
20824626SN/A        const string &cstr = cmd.toString();
20834626SN/A
20844626SN/A        mshrAccesses[access_idx]
20854626SN/A            .name(name() + "." + cstr + "_mshr_accesses")
20864626SN/A            .desc("number of " + cstr + " mshr accesses(hits+misses)")
20874626SN/A            .flags(total | nozero | nonan)
20884626SN/A            ;
20894626SN/A        mshrAccesses[access_idx] =
20904626SN/A            mshr_hits[access_idx] + mshr_misses[access_idx]
20914626SN/A            + mshr_uncacheable[access_idx];
20924626SN/A    }
20934626SN/A
20944626SN/A    demandMshrAccesses
20954626SN/A        .name(name() + ".demand_mshr_accesses")
20964626SN/A        .desc("number of demand (read+write) mshr accesses")
20974626SN/A        .flags(total | nozero | nonan)
20984626SN/A        ;
20994626SN/A    demandMshrAccesses = demandMshrHits + demandMshrMisses;
21004626SN/A
21014626SN/A    overallMshrAccesses
21024626SN/A        .name(name() + ".overall_mshr_accesses")
21034626SN/A        .desc("number of overall (read+write) mshr accesses")
21044626SN/A        .flags(total | nozero | nonan)
21054626SN/A        ;
21064626SN/A    overallMshrAccesses = overallMshrHits + overallMshrMisses
21074626SN/A        + overallMshrUncacheable;
21084626SN/A#endif
21094626SN/A
21104626SN/A    // MSHR miss rate formulas
21114626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
21124626SN/A        MemCmd cmd(access_idx);
21134626SN/A        const string &cstr = cmd.toString();
21144626SN/A
21154626SN/A        mshrMissRate[access_idx]
21164626SN/A            .name(name() + "." + cstr + "_mshr_miss_rate")
21174626SN/A            .desc("mshr miss rate for " + cstr + " accesses")
21184626SN/A            .flags(total | nozero | nonan)
21194626SN/A            ;
21204626SN/A        mshrMissRate[access_idx] =
21214626SN/A            mshr_misses[access_idx] / accesses[access_idx];
21228833Sdam.sunwoo@arm.com
21238833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
21248833Sdam.sunwoo@arm.com            mshrMissRate[access_idx].subname(i, system->getMasterName(i));
21258833Sdam.sunwoo@arm.com        }
21264626SN/A    }
21274626SN/A
21284626SN/A    demandMshrMissRate
21294626SN/A        .name(name() + ".demand_mshr_miss_rate")
21304626SN/A        .desc("mshr miss rate for demand accesses")
21318833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
21324626SN/A        ;
21334626SN/A    demandMshrMissRate = demandMshrMisses / demandAccesses;
21348833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
21358833Sdam.sunwoo@arm.com        demandMshrMissRate.subname(i, system->getMasterName(i));
21368833Sdam.sunwoo@arm.com    }
21374626SN/A
21384626SN/A    overallMshrMissRate
21394626SN/A        .name(name() + ".overall_mshr_miss_rate")
21404626SN/A        .desc("mshr miss rate for overall accesses")
21418833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
21424626SN/A        ;
21434626SN/A    overallMshrMissRate = overallMshrMisses / overallAccesses;
21448833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
21458833Sdam.sunwoo@arm.com        overallMshrMissRate.subname(i, system->getMasterName(i));
21468833Sdam.sunwoo@arm.com    }
21474626SN/A
21484626SN/A    // mshrMiss latency formulas
21494626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
21504626SN/A        MemCmd cmd(access_idx);
21514626SN/A        const string &cstr = cmd.toString();
21524626SN/A
21534626SN/A        avgMshrMissLatency[access_idx]
21544626SN/A            .name(name() + "." + cstr + "_avg_mshr_miss_latency")
21554626SN/A            .desc("average " + cstr + " mshr miss latency")
21564626SN/A            .flags(total | nozero | nonan)
21574626SN/A            ;
21584626SN/A        avgMshrMissLatency[access_idx] =
21594626SN/A            mshr_miss_latency[access_idx] / mshr_misses[access_idx];
21608833Sdam.sunwoo@arm.com
21618833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
216211483Snikos.nikoleris@arm.com            avgMshrMissLatency[access_idx].subname(
216311483Snikos.nikoleris@arm.com                i, system->getMasterName(i));
21648833Sdam.sunwoo@arm.com        }
21654626SN/A    }
21664626SN/A
21674626SN/A    demandAvgMshrMissLatency
21684626SN/A        .name(name() + ".demand_avg_mshr_miss_latency")
21694626SN/A        .desc("average overall mshr miss latency")
21708833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
21714626SN/A        ;
21724626SN/A    demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses;
21738833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
21748833Sdam.sunwoo@arm.com        demandAvgMshrMissLatency.subname(i, system->getMasterName(i));
21758833Sdam.sunwoo@arm.com    }
21764626SN/A
21774626SN/A    overallAvgMshrMissLatency
21784626SN/A        .name(name() + ".overall_avg_mshr_miss_latency")
21794626SN/A        .desc("average overall mshr miss latency")
21808833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
21814626SN/A        ;
21824626SN/A    overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses;
21838833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
21848833Sdam.sunwoo@arm.com        overallAvgMshrMissLatency.subname(i, system->getMasterName(i));
21858833Sdam.sunwoo@arm.com    }
21864626SN/A
21874626SN/A    // mshrUncacheable latency formulas
21884626SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
21894626SN/A        MemCmd cmd(access_idx);
21904626SN/A        const string &cstr = cmd.toString();
21914626SN/A
21924626SN/A        avgMshrUncacheableLatency[access_idx]
21934626SN/A            .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency")
21944626SN/A            .desc("average " + cstr + " mshr uncacheable latency")
21954626SN/A            .flags(total | nozero | nonan)
21964626SN/A            ;
21974626SN/A        avgMshrUncacheableLatency[access_idx] =
21984626SN/A            mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx];
21998833Sdam.sunwoo@arm.com
22008833Sdam.sunwoo@arm.com        for (int i = 0; i < system->maxMasters(); i++) {
220111483Snikos.nikoleris@arm.com            avgMshrUncacheableLatency[access_idx].subname(
220211483Snikos.nikoleris@arm.com                i, system->getMasterName(i));
22038833Sdam.sunwoo@arm.com        }
22044626SN/A    }
22054626SN/A
22064626SN/A    overallAvgMshrUncacheableLatency
22074626SN/A        .name(name() + ".overall_avg_mshr_uncacheable_latency")
22084626SN/A        .desc("average overall mshr uncacheable latency")
22098833Sdam.sunwoo@arm.com        .flags(total | nozero | nonan)
22104626SN/A        ;
221111483Snikos.nikoleris@arm.com    overallAvgMshrUncacheableLatency =
221211483Snikos.nikoleris@arm.com        overallMshrUncacheableLatency / overallMshrUncacheable;
22138833Sdam.sunwoo@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
22148833Sdam.sunwoo@arm.com        overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i));
22158833Sdam.sunwoo@arm.com    }
22164626SN/A
221712702Snikos.nikoleris@arm.com    replacements
221812702Snikos.nikoleris@arm.com        .name(name() + ".replacements")
221912702Snikos.nikoleris@arm.com        .desc("number of replacements")
222012702Snikos.nikoleris@arm.com        ;
22212810SN/A}
222212724Snikos.nikoleris@arm.com
222313416Sjavier.bueno@metempsy.comvoid
222413416Sjavier.bueno@metempsy.comBaseCache::regProbePoints()
222513416Sjavier.bueno@metempsy.com{
222613416Sjavier.bueno@metempsy.com    ppHit = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Hit");
222713416Sjavier.bueno@metempsy.com    ppMiss = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Miss");
222813416Sjavier.bueno@metempsy.com}
222913416Sjavier.bueno@metempsy.com
223012724Snikos.nikoleris@arm.com///////////////
223112724Snikos.nikoleris@arm.com//
223212724Snikos.nikoleris@arm.com// CpuSidePort
223312724Snikos.nikoleris@arm.com//
223412724Snikos.nikoleris@arm.com///////////////
223512724Snikos.nikoleris@arm.combool
223612724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
223712724Snikos.nikoleris@arm.com{
223812725Snikos.nikoleris@arm.com    // Snoops shouldn't happen when bypassing caches
223912725Snikos.nikoleris@arm.com    assert(!cache->system->bypassCaches());
224012725Snikos.nikoleris@arm.com
224112725Snikos.nikoleris@arm.com    assert(pkt->isResponse());
224212725Snikos.nikoleris@arm.com
224312724Snikos.nikoleris@arm.com    // Express snoop responses from master to slave, e.g., from L1 to L2
224412724Snikos.nikoleris@arm.com    cache->recvTimingSnoopResp(pkt);
224512724Snikos.nikoleris@arm.com    return true;
224612724Snikos.nikoleris@arm.com}
224712724Snikos.nikoleris@arm.com
224812724Snikos.nikoleris@arm.com
224912724Snikos.nikoleris@arm.combool
225012724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::tryTiming(PacketPtr pkt)
225112724Snikos.nikoleris@arm.com{
225212725Snikos.nikoleris@arm.com    if (cache->system->bypassCaches() || pkt->isExpressSnoop()) {
225312724Snikos.nikoleris@arm.com        // always let express snoop packets through even if blocked
225412724Snikos.nikoleris@arm.com        return true;
225512724Snikos.nikoleris@arm.com    } else if (blocked || mustSendRetry) {
225612724Snikos.nikoleris@arm.com        // either already committed to send a retry, or blocked
225712724Snikos.nikoleris@arm.com        mustSendRetry = true;
225812724Snikos.nikoleris@arm.com        return false;
225912724Snikos.nikoleris@arm.com    }
226012724Snikos.nikoleris@arm.com    mustSendRetry = false;
226112724Snikos.nikoleris@arm.com    return true;
226212724Snikos.nikoleris@arm.com}
226312724Snikos.nikoleris@arm.com
226412724Snikos.nikoleris@arm.combool
226512724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt)
226612724Snikos.nikoleris@arm.com{
226712725Snikos.nikoleris@arm.com    assert(pkt->isRequest());
226812725Snikos.nikoleris@arm.com
226912725Snikos.nikoleris@arm.com    if (cache->system->bypassCaches()) {
227012725Snikos.nikoleris@arm.com        // Just forward the packet if caches are disabled.
227112725Snikos.nikoleris@arm.com        // @todo This should really enqueue the packet rather
227212725Snikos.nikoleris@arm.com        bool M5_VAR_USED success = cache->memSidePort.sendTimingReq(pkt);
227312725Snikos.nikoleris@arm.com        assert(success);
227412725Snikos.nikoleris@arm.com        return true;
227512725Snikos.nikoleris@arm.com    } else if (tryTiming(pkt)) {
227612724Snikos.nikoleris@arm.com        cache->recvTimingReq(pkt);
227712724Snikos.nikoleris@arm.com        return true;
227812724Snikos.nikoleris@arm.com    }
227912724Snikos.nikoleris@arm.com    return false;
228012724Snikos.nikoleris@arm.com}
228112724Snikos.nikoleris@arm.com
228212724Snikos.nikoleris@arm.comTick
228312724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvAtomic(PacketPtr pkt)
228412724Snikos.nikoleris@arm.com{
228512725Snikos.nikoleris@arm.com    if (cache->system->bypassCaches()) {
228612725Snikos.nikoleris@arm.com        // Forward the request if the system is in cache bypass mode.
228712725Snikos.nikoleris@arm.com        return cache->memSidePort.sendAtomic(pkt);
228812725Snikos.nikoleris@arm.com    } else {
228912725Snikos.nikoleris@arm.com        return cache->recvAtomic(pkt);
229012725Snikos.nikoleris@arm.com    }
229112724Snikos.nikoleris@arm.com}
229212724Snikos.nikoleris@arm.com
229312724Snikos.nikoleris@arm.comvoid
229412724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvFunctional(PacketPtr pkt)
229512724Snikos.nikoleris@arm.com{
229612725Snikos.nikoleris@arm.com    if (cache->system->bypassCaches()) {
229712725Snikos.nikoleris@arm.com        // The cache should be flushed if we are in cache bypass mode,
229812725Snikos.nikoleris@arm.com        // so we don't need to check if we need to update anything.
229912725Snikos.nikoleris@arm.com        cache->memSidePort.sendFunctional(pkt);
230012725Snikos.nikoleris@arm.com        return;
230112725Snikos.nikoleris@arm.com    }
230212725Snikos.nikoleris@arm.com
230312724Snikos.nikoleris@arm.com    // functional request
230412724Snikos.nikoleris@arm.com    cache->functionalAccess(pkt, true);
230512724Snikos.nikoleris@arm.com}
230612724Snikos.nikoleris@arm.com
230712724Snikos.nikoleris@arm.comAddrRangeList
230812724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::getAddrRanges() const
230912724Snikos.nikoleris@arm.com{
231012724Snikos.nikoleris@arm.com    return cache->getAddrRanges();
231112724Snikos.nikoleris@arm.com}
231212724Snikos.nikoleris@arm.com
231312724Snikos.nikoleris@arm.com
231412724Snikos.nikoleris@arm.comBaseCache::
231512724Snikos.nikoleris@arm.comCpuSidePort::CpuSidePort(const std::string &_name, BaseCache *_cache,
231612724Snikos.nikoleris@arm.com                         const std::string &_label)
231712724Snikos.nikoleris@arm.com    : CacheSlavePort(_name, _cache, _label), cache(_cache)
231812724Snikos.nikoleris@arm.com{
231912724Snikos.nikoleris@arm.com}
232012724Snikos.nikoleris@arm.com
232112724Snikos.nikoleris@arm.com///////////////
232212724Snikos.nikoleris@arm.com//
232312724Snikos.nikoleris@arm.com// MemSidePort
232412724Snikos.nikoleris@arm.com//
232512724Snikos.nikoleris@arm.com///////////////
232612724Snikos.nikoleris@arm.combool
232712724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvTimingResp(PacketPtr pkt)
232812724Snikos.nikoleris@arm.com{
232912724Snikos.nikoleris@arm.com    cache->recvTimingResp(pkt);
233012724Snikos.nikoleris@arm.com    return true;
233112724Snikos.nikoleris@arm.com}
233212724Snikos.nikoleris@arm.com
233312724Snikos.nikoleris@arm.com// Express snooping requests to memside port
233412724Snikos.nikoleris@arm.comvoid
233512724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt)
233612724Snikos.nikoleris@arm.com{
233712725Snikos.nikoleris@arm.com    // Snoops shouldn't happen when bypassing caches
233812725Snikos.nikoleris@arm.com    assert(!cache->system->bypassCaches());
233912725Snikos.nikoleris@arm.com
234012724Snikos.nikoleris@arm.com    // handle snooping requests
234112724Snikos.nikoleris@arm.com    cache->recvTimingSnoopReq(pkt);
234212724Snikos.nikoleris@arm.com}
234312724Snikos.nikoleris@arm.com
234412724Snikos.nikoleris@arm.comTick
234512724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt)
234612724Snikos.nikoleris@arm.com{
234712725Snikos.nikoleris@arm.com    // Snoops shouldn't happen when bypassing caches
234812725Snikos.nikoleris@arm.com    assert(!cache->system->bypassCaches());
234912725Snikos.nikoleris@arm.com
235012724Snikos.nikoleris@arm.com    return cache->recvAtomicSnoop(pkt);
235112724Snikos.nikoleris@arm.com}
235212724Snikos.nikoleris@arm.com
235312724Snikos.nikoleris@arm.comvoid
235412724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt)
235512724Snikos.nikoleris@arm.com{
235612725Snikos.nikoleris@arm.com    // Snoops shouldn't happen when bypassing caches
235712725Snikos.nikoleris@arm.com    assert(!cache->system->bypassCaches());
235812725Snikos.nikoleris@arm.com
235912724Snikos.nikoleris@arm.com    // functional snoop (note that in contrast to atomic we don't have
236012724Snikos.nikoleris@arm.com    // a specific functionalSnoop method, as they have the same
236112724Snikos.nikoleris@arm.com    // behaviour regardless)
236212724Snikos.nikoleris@arm.com    cache->functionalAccess(pkt, false);
236312724Snikos.nikoleris@arm.com}
236412724Snikos.nikoleris@arm.com
236512724Snikos.nikoleris@arm.comvoid
236612724Snikos.nikoleris@arm.comBaseCache::CacheReqPacketQueue::sendDeferredPacket()
236712724Snikos.nikoleris@arm.com{
236812724Snikos.nikoleris@arm.com    // sanity check
236912724Snikos.nikoleris@arm.com    assert(!waitingOnRetry);
237012724Snikos.nikoleris@arm.com
237112724Snikos.nikoleris@arm.com    // there should never be any deferred request packets in the
237212724Snikos.nikoleris@arm.com    // queue, instead we resly on the cache to provide the packets
237312724Snikos.nikoleris@arm.com    // from the MSHR queue or write queue
237412724Snikos.nikoleris@arm.com    assert(deferredPacketReadyTime() == MaxTick);
237512724Snikos.nikoleris@arm.com
237612724Snikos.nikoleris@arm.com    // check for request packets (requests & writebacks)
237712724Snikos.nikoleris@arm.com    QueueEntry* entry = cache.getNextQueueEntry();
237812724Snikos.nikoleris@arm.com
237912724Snikos.nikoleris@arm.com    if (!entry) {
238012724Snikos.nikoleris@arm.com        // can happen if e.g. we attempt a writeback and fail, but
238112724Snikos.nikoleris@arm.com        // before the retry, the writeback is eliminated because
238212724Snikos.nikoleris@arm.com        // we snoop another cache's ReadEx.
238312724Snikos.nikoleris@arm.com    } else {
238412724Snikos.nikoleris@arm.com        // let our snoop responses go first if there are responses to
238512724Snikos.nikoleris@arm.com        // the same addresses
238612724Snikos.nikoleris@arm.com        if (checkConflictingSnoop(entry->blkAddr)) {
238712724Snikos.nikoleris@arm.com            return;
238812724Snikos.nikoleris@arm.com        }
238912724Snikos.nikoleris@arm.com        waitingOnRetry = entry->sendPacket(cache);
239012724Snikos.nikoleris@arm.com    }
239112724Snikos.nikoleris@arm.com
239212724Snikos.nikoleris@arm.com    // if we succeeded and are not waiting for a retry, schedule the
239312724Snikos.nikoleris@arm.com    // next send considering when the next queue is ready, note that
239412724Snikos.nikoleris@arm.com    // snoop responses have their own packet queue and thus schedule
239512724Snikos.nikoleris@arm.com    // their own events
239612724Snikos.nikoleris@arm.com    if (!waitingOnRetry) {
239712724Snikos.nikoleris@arm.com        schedSendEvent(cache.nextQueueReadyTime());
239812724Snikos.nikoleris@arm.com    }
239912724Snikos.nikoleris@arm.com}
240012724Snikos.nikoleris@arm.com
240112724Snikos.nikoleris@arm.comBaseCache::MemSidePort::MemSidePort(const std::string &_name,
240212724Snikos.nikoleris@arm.com                                    BaseCache *_cache,
240312724Snikos.nikoleris@arm.com                                    const std::string &_label)
240412724Snikos.nikoleris@arm.com    : CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue),
240512724Snikos.nikoleris@arm.com      _reqQueue(*_cache, *this, _snoopRespQueue, _label),
240612724Snikos.nikoleris@arm.com      _snoopRespQueue(*_cache, *this, _label), cache(_cache)
240712724Snikos.nikoleris@arm.com{
240812724Snikos.nikoleris@arm.com}
240913352Snikos.nikoleris@arm.com
241013352Snikos.nikoleris@arm.comvoid
241113352Snikos.nikoleris@arm.comWriteAllocator::updateMode(Addr write_addr, unsigned write_size,
241213352Snikos.nikoleris@arm.com                           Addr blk_addr)
241313352Snikos.nikoleris@arm.com{
241413352Snikos.nikoleris@arm.com    // check if we are continuing where the last write ended
241513352Snikos.nikoleris@arm.com    if (nextAddr == write_addr) {
241613352Snikos.nikoleris@arm.com        delayCtr[blk_addr] = delayThreshold;
241713352Snikos.nikoleris@arm.com        // stop if we have already saturated
241813352Snikos.nikoleris@arm.com        if (mode != WriteMode::NO_ALLOCATE) {
241913352Snikos.nikoleris@arm.com            byteCount += write_size;
242013352Snikos.nikoleris@arm.com            // switch to streaming mode if we have passed the lower
242113352Snikos.nikoleris@arm.com            // threshold
242213352Snikos.nikoleris@arm.com            if (mode == WriteMode::ALLOCATE &&
242313352Snikos.nikoleris@arm.com                byteCount > coalesceLimit) {
242413352Snikos.nikoleris@arm.com                mode = WriteMode::COALESCE;
242513352Snikos.nikoleris@arm.com                DPRINTF(Cache, "Switched to write coalescing\n");
242613352Snikos.nikoleris@arm.com            } else if (mode == WriteMode::COALESCE &&
242713352Snikos.nikoleris@arm.com                       byteCount > noAllocateLimit) {
242813352Snikos.nikoleris@arm.com                // and continue and switch to non-allocating mode if we
242913352Snikos.nikoleris@arm.com                // pass the upper threshold
243013352Snikos.nikoleris@arm.com                mode = WriteMode::NO_ALLOCATE;
243113352Snikos.nikoleris@arm.com                DPRINTF(Cache, "Switched to write-no-allocate\n");
243213352Snikos.nikoleris@arm.com            }
243313352Snikos.nikoleris@arm.com        }
243413352Snikos.nikoleris@arm.com    } else {
243513352Snikos.nikoleris@arm.com        // we did not see a write matching the previous one, start
243613352Snikos.nikoleris@arm.com        // over again
243713352Snikos.nikoleris@arm.com        byteCount = write_size;
243813352Snikos.nikoleris@arm.com        mode = WriteMode::ALLOCATE;
243913352Snikos.nikoleris@arm.com        resetDelay(blk_addr);
244013352Snikos.nikoleris@arm.com    }
244113352Snikos.nikoleris@arm.com    nextAddr = write_addr + write_size;
244213352Snikos.nikoleris@arm.com}
244313352Snikos.nikoleris@arm.com
244413352Snikos.nikoleris@arm.comWriteAllocator*
244513352Snikos.nikoleris@arm.comWriteAllocatorParams::create()
244613352Snikos.nikoleris@arm.com{
244713352Snikos.nikoleris@arm.com    return new WriteAllocator(this);
244813352Snikos.nikoleris@arm.com}
2449