base.cc revision 12702
12810SN/A/* 29614Srene.dejong@arm.com * Copyright (c) 2012-2013 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 412810SN/A */ 422810SN/A 432810SN/A/** 442810SN/A * @file 452810SN/A * Definition of BaseCache functions. 462810SN/A */ 472810SN/A 4811486Snikos.nikoleris@arm.com#include "mem/cache/base.hh" 4911486Snikos.nikoleris@arm.com 508232Snate@binkert.org#include "debug/Cache.hh" 519152Satgutier@umich.edu#include "debug/Drain.hh" 5211486Snikos.nikoleris@arm.com#include "mem/cache/cache.hh" 5311486Snikos.nikoleris@arm.com#include "mem/cache/mshr.hh" 549795Sandreas.hansson@arm.com#include "mem/cache/tags/fa_lru.hh" 558786Sgblack@eecs.umich.edu#include "sim/full_system.hh" 562810SN/A 572810SN/Ausing namespace std; 582810SN/A 598856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 608856Sandreas.hansson@arm.com BaseCache *_cache, 618856Sandreas.hansson@arm.com const std::string &_label) 628922Swilliam.wang@arm.com : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 6312084Sspwilson2@wisc.edu blocked(false), mustSendRetry(false), 6412084Sspwilson2@wisc.edu sendRetryEvent([this]{ processSendRetry(); }, _name) 658856Sandreas.hansson@arm.com{ 668856Sandreas.hansson@arm.com} 674475SN/A 6811053Sandreas.hansson@arm.comBaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) 695034SN/A : MemObject(p), 7010360Sandreas.hansson@arm.com cpuSidePort(nullptr), memSidePort(nullptr), 7111377Sandreas.hansson@arm.com mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below 7211377Sandreas.hansson@arm.com writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below 7311053Sandreas.hansson@arm.com blkSize(blk_size), 7411722Ssophiane.senni@gmail.com lookupLatency(p->tag_latency), 7511722Ssophiane.senni@gmail.com dataLatency(p->data_latency), 7611722Ssophiane.senni@gmail.com forwardLatency(p->tag_latency), 7711722Ssophiane.senni@gmail.com fillLatency(p->data_latency), 789263Smrinmoy.ghosh@arm.com responseLatency(p->response_latency), 795034SN/A numTarget(p->tgts_per_mshr), 8011331Sandreas.hansson@arm.com forwardSnoops(true), 8110884Sandreas.hansson@arm.com isReadOnly(p->is_read_only), 824626SN/A blocked(0), 8310360Sandreas.hansson@arm.com order(0), 8411484Snikos.nikoleris@arm.com noTargetMSHR(nullptr), 855034SN/A missCount(p->max_miss_count), 868883SAli.Saidi@ARM.com addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 878833Sdam.sunwoo@arm.com system(p->system) 884458SN/A{ 8911377Sandreas.hansson@arm.com // the MSHR queue has no reserve entries as we check the MSHR 9011377Sandreas.hansson@arm.com // queue on every single allocation, whereas the write queue has 9111377Sandreas.hansson@arm.com // as many reserve entries as we have MSHRs, since every MSHR may 9211377Sandreas.hansson@arm.com // eventually require a writeback, and we do not check the write 9311377Sandreas.hansson@arm.com // buffer before committing to an MSHR 9411377Sandreas.hansson@arm.com 9511331Sandreas.hansson@arm.com // forward snoops is overridden in init() once we can query 9611331Sandreas.hansson@arm.com // whether the connected master is actually snooping or not 972810SN/A} 982810SN/A 993013SN/Avoid 1008856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::setBlocked() 1012810SN/A{ 1023013SN/A assert(!blocked); 10310714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is blocking new requests\n"); 1042810SN/A blocked = true; 1059614Srene.dejong@arm.com // if we already scheduled a retry in this cycle, but it has not yet 1069614Srene.dejong@arm.com // happened, cancel it 1079614Srene.dejong@arm.com if (sendRetryEvent.scheduled()) { 10810345SCurtis.Dunham@arm.com owner.deschedule(sendRetryEvent); 10910714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port descheduled retry\n"); 11010345SCurtis.Dunham@arm.com mustSendRetry = true; 1119614Srene.dejong@arm.com } 1122810SN/A} 1132810SN/A 1142810SN/Avoid 1158856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::clearBlocked() 1162810SN/A{ 1173013SN/A assert(blocked); 11810714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is accepting new requests\n"); 1193013SN/A blocked = false; 1208856Sandreas.hansson@arm.com if (mustSendRetry) { 12110714Sandreas.hansson@arm.com // @TODO: need to find a better time (next cycle?) 1228922Swilliam.wang@arm.com owner.schedule(sendRetryEvent, curTick() + 1); 1232897SN/A } 1242810SN/A} 1252810SN/A 12610344Sandreas.hansson@arm.comvoid 12710344Sandreas.hansson@arm.comBaseCache::CacheSlavePort::processSendRetry() 12810344Sandreas.hansson@arm.com{ 12910714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is sending retry\n"); 13010344Sandreas.hansson@arm.com 13110344Sandreas.hansson@arm.com // reset the flag and call retry 13210344Sandreas.hansson@arm.com mustSendRetry = false; 13310713Sandreas.hansson@arm.com sendRetryReq(); 13410344Sandreas.hansson@arm.com} 1352844SN/A 1362810SN/Avoid 1372858SN/ABaseCache::init() 1382858SN/A{ 1398856Sandreas.hansson@arm.com if (!cpuSidePort->isConnected() || !memSidePort->isConnected()) 1408922Swilliam.wang@arm.com fatal("Cache ports on %s are not connected\n", name()); 1418711Sandreas.hansson@arm.com cpuSidePort->sendRangeChange(); 14211331Sandreas.hansson@arm.com forwardSnoops = cpuSidePort->isSnooping(); 1432858SN/A} 1442858SN/A 1459294Sandreas.hansson@arm.comBaseMasterPort & 1469294Sandreas.hansson@arm.comBaseCache::getMasterPort(const std::string &if_name, PortID idx) 1478922Swilliam.wang@arm.com{ 1488922Swilliam.wang@arm.com if (if_name == "mem_side") { 1498922Swilliam.wang@arm.com return *memSidePort; 1508922Swilliam.wang@arm.com } else { 1518922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1528922Swilliam.wang@arm.com } 1538922Swilliam.wang@arm.com} 1548922Swilliam.wang@arm.com 1559294Sandreas.hansson@arm.comBaseSlavePort & 1569294Sandreas.hansson@arm.comBaseCache::getSlavePort(const std::string &if_name, PortID idx) 1578922Swilliam.wang@arm.com{ 1588922Swilliam.wang@arm.com if (if_name == "cpu_side") { 1598922Swilliam.wang@arm.com return *cpuSidePort; 1608922Swilliam.wang@arm.com } else { 1618922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 1628922Swilliam.wang@arm.com } 1638922Swilliam.wang@arm.com} 1644628SN/A 16510821Sandreas.hansson@arm.combool 16610821Sandreas.hansson@arm.comBaseCache::inRange(Addr addr) const 16710821Sandreas.hansson@arm.com{ 16810821Sandreas.hansson@arm.com for (const auto& r : addrRanges) { 16910821Sandreas.hansson@arm.com if (r.contains(addr)) { 17010821Sandreas.hansson@arm.com return true; 17110821Sandreas.hansson@arm.com } 17210821Sandreas.hansson@arm.com } 17310821Sandreas.hansson@arm.com return false; 17410821Sandreas.hansson@arm.com} 17510821Sandreas.hansson@arm.com 1762858SN/Avoid 1772810SN/ABaseCache::regStats() 1782810SN/A{ 17911522Sstephan.diestelhorst@arm.com MemObject::regStats(); 18011522Sstephan.diestelhorst@arm.com 1812810SN/A using namespace Stats; 1822810SN/A 1832810SN/A // Hit statistics 1844022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1854022SN/A MemCmd cmd(access_idx); 1864022SN/A const string &cstr = cmd.toString(); 1872810SN/A 1882810SN/A hits[access_idx] 1898833Sdam.sunwoo@arm.com .init(system->maxMasters()) 1902810SN/A .name(name() + "." + cstr + "_hits") 1912810SN/A .desc("number of " + cstr + " hits") 1922810SN/A .flags(total | nozero | nonan) 1932810SN/A ; 1948833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1958833Sdam.sunwoo@arm.com hits[access_idx].subname(i, system->getMasterName(i)); 1968833Sdam.sunwoo@arm.com } 1972810SN/A } 1982810SN/A 1994871SN/A// These macros make it easier to sum the right subset of commands and 2004871SN/A// to change the subset of commands that are considered "demand" vs 2014871SN/A// "non-demand" 2024871SN/A#define SUM_DEMAND(s) \ 20311455Sandreas.hansson@arm.com (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \ 20410885Sandreas.hansson@arm.com s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq]) 2054871SN/A 2064871SN/A// should writebacks be included here? prior code was inconsistent... 2074871SN/A#define SUM_NON_DEMAND(s) \ 2084871SN/A (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 2094871SN/A 2102810SN/A demandHits 2112810SN/A .name(name() + ".demand_hits") 2122810SN/A .desc("number of demand (read+write) hits") 2138833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2142810SN/A ; 2154871SN/A demandHits = SUM_DEMAND(hits); 2168833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2178833Sdam.sunwoo@arm.com demandHits.subname(i, system->getMasterName(i)); 2188833Sdam.sunwoo@arm.com } 2192810SN/A 2202810SN/A overallHits 2212810SN/A .name(name() + ".overall_hits") 2222810SN/A .desc("number of overall hits") 2238833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2242810SN/A ; 2254871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 2268833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2278833Sdam.sunwoo@arm.com overallHits.subname(i, system->getMasterName(i)); 2288833Sdam.sunwoo@arm.com } 2292810SN/A 2302810SN/A // Miss statistics 2314022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2324022SN/A MemCmd cmd(access_idx); 2334022SN/A const string &cstr = cmd.toString(); 2342810SN/A 2352810SN/A misses[access_idx] 2368833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2372810SN/A .name(name() + "." + cstr + "_misses") 2382810SN/A .desc("number of " + cstr + " misses") 2392810SN/A .flags(total | nozero | nonan) 2402810SN/A ; 2418833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2428833Sdam.sunwoo@arm.com misses[access_idx].subname(i, system->getMasterName(i)); 2438833Sdam.sunwoo@arm.com } 2442810SN/A } 2452810SN/A 2462810SN/A demandMisses 2472810SN/A .name(name() + ".demand_misses") 2482810SN/A .desc("number of demand (read+write) misses") 2498833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2502810SN/A ; 2514871SN/A demandMisses = SUM_DEMAND(misses); 2528833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2538833Sdam.sunwoo@arm.com demandMisses.subname(i, system->getMasterName(i)); 2548833Sdam.sunwoo@arm.com } 2552810SN/A 2562810SN/A overallMisses 2572810SN/A .name(name() + ".overall_misses") 2582810SN/A .desc("number of overall misses") 2598833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2602810SN/A ; 2614871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 2628833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2638833Sdam.sunwoo@arm.com overallMisses.subname(i, system->getMasterName(i)); 2648833Sdam.sunwoo@arm.com } 2652810SN/A 2662810SN/A // Miss latency statistics 2674022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2684022SN/A MemCmd cmd(access_idx); 2694022SN/A const string &cstr = cmd.toString(); 2702810SN/A 2712810SN/A missLatency[access_idx] 2728833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2732810SN/A .name(name() + "." + cstr + "_miss_latency") 2742810SN/A .desc("number of " + cstr + " miss cycles") 2752810SN/A .flags(total | nozero | nonan) 2762810SN/A ; 2778833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2788833Sdam.sunwoo@arm.com missLatency[access_idx].subname(i, system->getMasterName(i)); 2798833Sdam.sunwoo@arm.com } 2802810SN/A } 2812810SN/A 2822810SN/A demandMissLatency 2832810SN/A .name(name() + ".demand_miss_latency") 2842810SN/A .desc("number of demand (read+write) miss cycles") 2858833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2862810SN/A ; 2874871SN/A demandMissLatency = SUM_DEMAND(missLatency); 2888833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2898833Sdam.sunwoo@arm.com demandMissLatency.subname(i, system->getMasterName(i)); 2908833Sdam.sunwoo@arm.com } 2912810SN/A 2922810SN/A overallMissLatency 2932810SN/A .name(name() + ".overall_miss_latency") 2942810SN/A .desc("number of overall miss cycles") 2958833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2962810SN/A ; 2974871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 2988833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2998833Sdam.sunwoo@arm.com overallMissLatency.subname(i, system->getMasterName(i)); 3008833Sdam.sunwoo@arm.com } 3012810SN/A 3022810SN/A // access formulas 3034022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3044022SN/A MemCmd cmd(access_idx); 3054022SN/A const string &cstr = cmd.toString(); 3062810SN/A 3072810SN/A accesses[access_idx] 3082810SN/A .name(name() + "." + cstr + "_accesses") 3092810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 3102810SN/A .flags(total | nozero | nonan) 3112810SN/A ; 3128833Sdam.sunwoo@arm.com accesses[access_idx] = hits[access_idx] + misses[access_idx]; 3132810SN/A 3148833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3158833Sdam.sunwoo@arm.com accesses[access_idx].subname(i, system->getMasterName(i)); 3168833Sdam.sunwoo@arm.com } 3172810SN/A } 3182810SN/A 3192810SN/A demandAccesses 3202810SN/A .name(name() + ".demand_accesses") 3212810SN/A .desc("number of demand (read+write) accesses") 3228833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3232810SN/A ; 3242810SN/A demandAccesses = demandHits + demandMisses; 3258833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3268833Sdam.sunwoo@arm.com demandAccesses.subname(i, system->getMasterName(i)); 3278833Sdam.sunwoo@arm.com } 3282810SN/A 3292810SN/A overallAccesses 3302810SN/A .name(name() + ".overall_accesses") 3312810SN/A .desc("number of overall (read+write) accesses") 3328833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3332810SN/A ; 3342810SN/A overallAccesses = overallHits + overallMisses; 3358833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3368833Sdam.sunwoo@arm.com overallAccesses.subname(i, system->getMasterName(i)); 3378833Sdam.sunwoo@arm.com } 3382810SN/A 3392810SN/A // miss rate formulas 3404022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3414022SN/A MemCmd cmd(access_idx); 3424022SN/A const string &cstr = cmd.toString(); 3432810SN/A 3442810SN/A missRate[access_idx] 3452810SN/A .name(name() + "." + cstr + "_miss_rate") 3462810SN/A .desc("miss rate for " + cstr + " accesses") 3472810SN/A .flags(total | nozero | nonan) 3482810SN/A ; 3498833Sdam.sunwoo@arm.com missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 3502810SN/A 3518833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3528833Sdam.sunwoo@arm.com missRate[access_idx].subname(i, system->getMasterName(i)); 3538833Sdam.sunwoo@arm.com } 3542810SN/A } 3552810SN/A 3562810SN/A demandMissRate 3572810SN/A .name(name() + ".demand_miss_rate") 3582810SN/A .desc("miss rate for demand accesses") 3598833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3602810SN/A ; 3612810SN/A demandMissRate = demandMisses / demandAccesses; 3628833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3638833Sdam.sunwoo@arm.com demandMissRate.subname(i, system->getMasterName(i)); 3648833Sdam.sunwoo@arm.com } 3652810SN/A 3662810SN/A overallMissRate 3672810SN/A .name(name() + ".overall_miss_rate") 3682810SN/A .desc("miss rate for overall accesses") 3698833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3702810SN/A ; 3712810SN/A overallMissRate = overallMisses / overallAccesses; 3728833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3738833Sdam.sunwoo@arm.com overallMissRate.subname(i, system->getMasterName(i)); 3748833Sdam.sunwoo@arm.com } 3752810SN/A 3762810SN/A // miss latency formulas 3774022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3784022SN/A MemCmd cmd(access_idx); 3794022SN/A const string &cstr = cmd.toString(); 3802810SN/A 3812810SN/A avgMissLatency[access_idx] 3822810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 3832810SN/A .desc("average " + cstr + " miss latency") 3842810SN/A .flags(total | nozero | nonan) 3852810SN/A ; 3862810SN/A avgMissLatency[access_idx] = 3872810SN/A missLatency[access_idx] / misses[access_idx]; 3888833Sdam.sunwoo@arm.com 3898833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3908833Sdam.sunwoo@arm.com avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 3918833Sdam.sunwoo@arm.com } 3922810SN/A } 3932810SN/A 3942810SN/A demandAvgMissLatency 3952810SN/A .name(name() + ".demand_avg_miss_latency") 3962810SN/A .desc("average overall miss latency") 3978833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3982810SN/A ; 3992810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 4008833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4018833Sdam.sunwoo@arm.com demandAvgMissLatency.subname(i, system->getMasterName(i)); 4028833Sdam.sunwoo@arm.com } 4032810SN/A 4042810SN/A overallAvgMissLatency 4052810SN/A .name(name() + ".overall_avg_miss_latency") 4062810SN/A .desc("average overall miss latency") 4078833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4082810SN/A ; 4092810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 4108833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4118833Sdam.sunwoo@arm.com overallAvgMissLatency.subname(i, system->getMasterName(i)); 4128833Sdam.sunwoo@arm.com } 4132810SN/A 4142810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 4152810SN/A blocked_cycles 4162810SN/A .name(name() + ".blocked_cycles") 4172810SN/A .desc("number of cycles access was blocked") 4182810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4192810SN/A .subname(Blocked_NoTargets, "no_targets") 4202810SN/A ; 4212810SN/A 4222810SN/A 4232810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 4242810SN/A blocked_causes 4252810SN/A .name(name() + ".blocked") 4262810SN/A .desc("number of cycles access was blocked") 4272810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4282810SN/A .subname(Blocked_NoTargets, "no_targets") 4292810SN/A ; 4302810SN/A 4312810SN/A avg_blocked 4322810SN/A .name(name() + ".avg_blocked_cycles") 4332810SN/A .desc("average number of cycles each access was blocked") 4342810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4352810SN/A .subname(Blocked_NoTargets, "no_targets") 4362810SN/A ; 4372810SN/A 4382810SN/A avg_blocked = blocked_cycles / blocked_causes; 4392810SN/A 44011436SRekai.GonzalezAlberquilla@arm.com unusedPrefetches 44111436SRekai.GonzalezAlberquilla@arm.com .name(name() + ".unused_prefetches") 44211436SRekai.GonzalezAlberquilla@arm.com .desc("number of HardPF blocks evicted w/o reference") 44311436SRekai.GonzalezAlberquilla@arm.com .flags(nozero) 44411436SRekai.GonzalezAlberquilla@arm.com ; 44511436SRekai.GonzalezAlberquilla@arm.com 4464626SN/A writebacks 4478833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4484626SN/A .name(name() + ".writebacks") 4494626SN/A .desc("number of writebacks") 4508833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4514626SN/A ; 4528833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4538833Sdam.sunwoo@arm.com writebacks.subname(i, system->getMasterName(i)); 4548833Sdam.sunwoo@arm.com } 4554626SN/A 4564626SN/A // MSHR statistics 4574626SN/A // MSHR hit statistics 4584626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4594626SN/A MemCmd cmd(access_idx); 4604626SN/A const string &cstr = cmd.toString(); 4614626SN/A 4624626SN/A mshr_hits[access_idx] 4638833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4644626SN/A .name(name() + "." + cstr + "_mshr_hits") 4654626SN/A .desc("number of " + cstr + " MSHR hits") 4664626SN/A .flags(total | nozero | nonan) 4674626SN/A ; 4688833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4698833Sdam.sunwoo@arm.com mshr_hits[access_idx].subname(i, system->getMasterName(i)); 4708833Sdam.sunwoo@arm.com } 4714626SN/A } 4724626SN/A 4734626SN/A demandMshrHits 4744626SN/A .name(name() + ".demand_mshr_hits") 4754626SN/A .desc("number of demand (read+write) MSHR hits") 4768833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4774626SN/A ; 4784871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 4798833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4808833Sdam.sunwoo@arm.com demandMshrHits.subname(i, system->getMasterName(i)); 4818833Sdam.sunwoo@arm.com } 4824626SN/A 4834626SN/A overallMshrHits 4844626SN/A .name(name() + ".overall_mshr_hits") 4854626SN/A .desc("number of overall MSHR hits") 4868833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4874626SN/A ; 4884871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 4898833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4908833Sdam.sunwoo@arm.com overallMshrHits.subname(i, system->getMasterName(i)); 4918833Sdam.sunwoo@arm.com } 4924626SN/A 4934626SN/A // MSHR miss statistics 4944626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4954626SN/A MemCmd cmd(access_idx); 4964626SN/A const string &cstr = cmd.toString(); 4974626SN/A 4984626SN/A mshr_misses[access_idx] 4998833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5004626SN/A .name(name() + "." + cstr + "_mshr_misses") 5014626SN/A .desc("number of " + cstr + " MSHR misses") 5024626SN/A .flags(total | nozero | nonan) 5034626SN/A ; 5048833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5058833Sdam.sunwoo@arm.com mshr_misses[access_idx].subname(i, system->getMasterName(i)); 5068833Sdam.sunwoo@arm.com } 5074626SN/A } 5084626SN/A 5094626SN/A demandMshrMisses 5104626SN/A .name(name() + ".demand_mshr_misses") 5114626SN/A .desc("number of demand (read+write) MSHR misses") 5128833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5134626SN/A ; 5144871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 5158833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5168833Sdam.sunwoo@arm.com demandMshrMisses.subname(i, system->getMasterName(i)); 5178833Sdam.sunwoo@arm.com } 5184626SN/A 5194626SN/A overallMshrMisses 5204626SN/A .name(name() + ".overall_mshr_misses") 5214626SN/A .desc("number of overall MSHR misses") 5228833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5234626SN/A ; 5244871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 5258833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5268833Sdam.sunwoo@arm.com overallMshrMisses.subname(i, system->getMasterName(i)); 5278833Sdam.sunwoo@arm.com } 5284626SN/A 5294626SN/A // MSHR miss latency statistics 5304626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5314626SN/A MemCmd cmd(access_idx); 5324626SN/A const string &cstr = cmd.toString(); 5334626SN/A 5344626SN/A mshr_miss_latency[access_idx] 5358833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5364626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 5374626SN/A .desc("number of " + cstr + " MSHR miss cycles") 5384626SN/A .flags(total | nozero | nonan) 5394626SN/A ; 5408833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5418833Sdam.sunwoo@arm.com mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 5428833Sdam.sunwoo@arm.com } 5434626SN/A } 5444626SN/A 5454626SN/A demandMshrMissLatency 5464626SN/A .name(name() + ".demand_mshr_miss_latency") 5474626SN/A .desc("number of demand (read+write) MSHR miss cycles") 5488833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5494626SN/A ; 5504871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 5518833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5528833Sdam.sunwoo@arm.com demandMshrMissLatency.subname(i, system->getMasterName(i)); 5538833Sdam.sunwoo@arm.com } 5544626SN/A 5554626SN/A overallMshrMissLatency 5564626SN/A .name(name() + ".overall_mshr_miss_latency") 5574626SN/A .desc("number of overall MSHR miss cycles") 5588833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5594626SN/A ; 5604871SN/A overallMshrMissLatency = 5614871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 5628833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5638833Sdam.sunwoo@arm.com overallMshrMissLatency.subname(i, system->getMasterName(i)); 5648833Sdam.sunwoo@arm.com } 5654626SN/A 5664626SN/A // MSHR uncacheable statistics 5674626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5684626SN/A MemCmd cmd(access_idx); 5694626SN/A const string &cstr = cmd.toString(); 5704626SN/A 5714626SN/A mshr_uncacheable[access_idx] 5728833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5734626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 5744626SN/A .desc("number of " + cstr + " MSHR uncacheable") 5754626SN/A .flags(total | nozero | nonan) 5764626SN/A ; 5778833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5788833Sdam.sunwoo@arm.com mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 5798833Sdam.sunwoo@arm.com } 5804626SN/A } 5814626SN/A 5824626SN/A overallMshrUncacheable 5834626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 5844626SN/A .desc("number of overall MSHR uncacheable misses") 5858833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5864626SN/A ; 5874871SN/A overallMshrUncacheable = 5884871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 5898833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5908833Sdam.sunwoo@arm.com overallMshrUncacheable.subname(i, system->getMasterName(i)); 5918833Sdam.sunwoo@arm.com } 5924626SN/A 5934626SN/A // MSHR miss latency statistics 5944626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5954626SN/A MemCmd cmd(access_idx); 5964626SN/A const string &cstr = cmd.toString(); 5974626SN/A 5984626SN/A mshr_uncacheable_lat[access_idx] 5998833Sdam.sunwoo@arm.com .init(system->maxMasters()) 6004626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 6014626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 6024626SN/A .flags(total | nozero | nonan) 6034626SN/A ; 6048833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 60511483Snikos.nikoleris@arm.com mshr_uncacheable_lat[access_idx].subname( 60611483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 6078833Sdam.sunwoo@arm.com } 6084626SN/A } 6094626SN/A 6104626SN/A overallMshrUncacheableLatency 6114626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 6124626SN/A .desc("number of overall MSHR uncacheable cycles") 6138833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6144626SN/A ; 6154871SN/A overallMshrUncacheableLatency = 6164871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 6174871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 6188833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6198833Sdam.sunwoo@arm.com overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 6208833Sdam.sunwoo@arm.com } 6214626SN/A 6224626SN/A#if 0 6234626SN/A // MSHR access formulas 6244626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6254626SN/A MemCmd cmd(access_idx); 6264626SN/A const string &cstr = cmd.toString(); 6274626SN/A 6284626SN/A mshrAccesses[access_idx] 6294626SN/A .name(name() + "." + cstr + "_mshr_accesses") 6304626SN/A .desc("number of " + cstr + " mshr accesses(hits+misses)") 6314626SN/A .flags(total | nozero | nonan) 6324626SN/A ; 6334626SN/A mshrAccesses[access_idx] = 6344626SN/A mshr_hits[access_idx] + mshr_misses[access_idx] 6354626SN/A + mshr_uncacheable[access_idx]; 6364626SN/A } 6374626SN/A 6384626SN/A demandMshrAccesses 6394626SN/A .name(name() + ".demand_mshr_accesses") 6404626SN/A .desc("number of demand (read+write) mshr accesses") 6414626SN/A .flags(total | nozero | nonan) 6424626SN/A ; 6434626SN/A demandMshrAccesses = demandMshrHits + demandMshrMisses; 6444626SN/A 6454626SN/A overallMshrAccesses 6464626SN/A .name(name() + ".overall_mshr_accesses") 6474626SN/A .desc("number of overall (read+write) mshr accesses") 6484626SN/A .flags(total | nozero | nonan) 6494626SN/A ; 6504626SN/A overallMshrAccesses = overallMshrHits + overallMshrMisses 6514626SN/A + overallMshrUncacheable; 6524626SN/A#endif 6534626SN/A 6544626SN/A // MSHR miss rate formulas 6554626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6564626SN/A MemCmd cmd(access_idx); 6574626SN/A const string &cstr = cmd.toString(); 6584626SN/A 6594626SN/A mshrMissRate[access_idx] 6604626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 6614626SN/A .desc("mshr miss rate for " + cstr + " accesses") 6624626SN/A .flags(total | nozero | nonan) 6634626SN/A ; 6644626SN/A mshrMissRate[access_idx] = 6654626SN/A mshr_misses[access_idx] / accesses[access_idx]; 6668833Sdam.sunwoo@arm.com 6678833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6688833Sdam.sunwoo@arm.com mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 6698833Sdam.sunwoo@arm.com } 6704626SN/A } 6714626SN/A 6724626SN/A demandMshrMissRate 6734626SN/A .name(name() + ".demand_mshr_miss_rate") 6744626SN/A .desc("mshr miss rate for demand accesses") 6758833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6764626SN/A ; 6774626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 6788833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6798833Sdam.sunwoo@arm.com demandMshrMissRate.subname(i, system->getMasterName(i)); 6808833Sdam.sunwoo@arm.com } 6814626SN/A 6824626SN/A overallMshrMissRate 6834626SN/A .name(name() + ".overall_mshr_miss_rate") 6844626SN/A .desc("mshr miss rate for overall accesses") 6858833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6864626SN/A ; 6874626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 6888833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6898833Sdam.sunwoo@arm.com overallMshrMissRate.subname(i, system->getMasterName(i)); 6908833Sdam.sunwoo@arm.com } 6914626SN/A 6924626SN/A // mshrMiss latency formulas 6934626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6944626SN/A MemCmd cmd(access_idx); 6954626SN/A const string &cstr = cmd.toString(); 6964626SN/A 6974626SN/A avgMshrMissLatency[access_idx] 6984626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 6994626SN/A .desc("average " + cstr + " mshr miss latency") 7004626SN/A .flags(total | nozero | nonan) 7014626SN/A ; 7024626SN/A avgMshrMissLatency[access_idx] = 7034626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 7048833Sdam.sunwoo@arm.com 7058833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 70611483Snikos.nikoleris@arm.com avgMshrMissLatency[access_idx].subname( 70711483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 7088833Sdam.sunwoo@arm.com } 7094626SN/A } 7104626SN/A 7114626SN/A demandAvgMshrMissLatency 7124626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 7134626SN/A .desc("average overall mshr miss latency") 7148833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7154626SN/A ; 7164626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 7178833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7188833Sdam.sunwoo@arm.com demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 7198833Sdam.sunwoo@arm.com } 7204626SN/A 7214626SN/A overallAvgMshrMissLatency 7224626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 7234626SN/A .desc("average overall mshr miss latency") 7248833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7254626SN/A ; 7264626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 7278833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7288833Sdam.sunwoo@arm.com overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 7298833Sdam.sunwoo@arm.com } 7304626SN/A 7314626SN/A // mshrUncacheable latency formulas 7324626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 7334626SN/A MemCmd cmd(access_idx); 7344626SN/A const string &cstr = cmd.toString(); 7354626SN/A 7364626SN/A avgMshrUncacheableLatency[access_idx] 7374626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 7384626SN/A .desc("average " + cstr + " mshr uncacheable latency") 7394626SN/A .flags(total | nozero | nonan) 7404626SN/A ; 7414626SN/A avgMshrUncacheableLatency[access_idx] = 7424626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 7438833Sdam.sunwoo@arm.com 7448833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 74511483Snikos.nikoleris@arm.com avgMshrUncacheableLatency[access_idx].subname( 74611483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 7478833Sdam.sunwoo@arm.com } 7484626SN/A } 7494626SN/A 7504626SN/A overallAvgMshrUncacheableLatency 7514626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 7524626SN/A .desc("average overall mshr uncacheable latency") 7538833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7544626SN/A ; 75511483Snikos.nikoleris@arm.com overallAvgMshrUncacheableLatency = 75611483Snikos.nikoleris@arm.com overallMshrUncacheableLatency / overallMshrUncacheable; 7578833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7588833Sdam.sunwoo@arm.com overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 7598833Sdam.sunwoo@arm.com } 7604626SN/A 76112702Snikos.nikoleris@arm.com replacements 76212702Snikos.nikoleris@arm.com .name(name() + ".replacements") 76312702Snikos.nikoleris@arm.com .desc("number of replacements") 76412702Snikos.nikoleris@arm.com ; 7652810SN/A} 766