base.cc revision 11053
12391SN/A/* 210482Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited 37733SAli.Saidi@ARM.com * All rights reserved. 47733SAli.Saidi@ARM.com * 57733SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67733SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77733SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87733SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97733SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107733SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117733SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127733SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137733SAli.Saidi@ARM.com * 142391SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152391SN/A * All rights reserved. 162391SN/A * 172391SN/A * Redistribution and use in source and binary forms, with or without 182391SN/A * modification, are permitted provided that the following conditions are 192391SN/A * met: redistributions of source code must retain the above copyright 202391SN/A * notice, this list of conditions and the following disclaimer; 212391SN/A * redistributions in binary form must reproduce the above copyright 222391SN/A * notice, this list of conditions and the following disclaimer in the 232391SN/A * documentation and/or other materials provided with the distribution; 242391SN/A * neither the name of the copyright holders nor the names of its 252391SN/A * contributors may be used to endorse or promote products derived from 262391SN/A * this software without specific prior written permission. 272391SN/A * 282391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352391SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362665Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 378931Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392391SN/A * 409293Sandreas.hansson@arm.com * Authors: Erik Hallnor 419293Sandreas.hansson@arm.com */ 429293Sandreas.hansson@arm.com 439293Sandreas.hansson@arm.com/** 449293Sandreas.hansson@arm.com * @file 459293Sandreas.hansson@arm.com * Definition of BaseCache functions. 469293Sandreas.hansson@arm.com */ 479293Sandreas.hansson@arm.com 489293Sandreas.hansson@arm.com#include "debug/Cache.hh" 499293Sandreas.hansson@arm.com#include "debug/Drain.hh" 509293Sandreas.hansson@arm.com#include "mem/cache/tags/fa_lru.hh" 519293Sandreas.hansson@arm.com#include "mem/cache/tags/lru.hh" 529293Sandreas.hansson@arm.com#include "mem/cache/tags/random_repl.hh" 539356Snilay@cs.wisc.edu#include "mem/cache/base.hh" 5410405Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 559293Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 569293Sandreas.hansson@arm.com#include "sim/full_system.hh" 572394SN/A 582394SN/Ausing namespace std; 592391SN/A 602391SN/ABaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 619293Sandreas.hansson@arm.com BaseCache *_cache, 629293Sandreas.hansson@arm.com const std::string &_label) 639293Sandreas.hansson@arm.com : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 642391SN/A blocked(false), mustSendRetry(false), sendRetryEvent(this) 659293Sandreas.hansson@arm.com{ 669293Sandreas.hansson@arm.com} 6710482Sandreas.hansson@arm.com 688931Sandreas.hansson@arm.comBaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) 6910482Sandreas.hansson@arm.com : MemObject(p), 7010482Sandreas.hansson@arm.com cpuSidePort(nullptr), memSidePort(nullptr), 712391SN/A mshrQueue("MSHRs", p->mshrs, 4, p->demand_mshr_reserve, MSHRQueue_MSHRs), 728931Sandreas.hansson@arm.com writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 0, 7310482Sandreas.hansson@arm.com MSHRQueue_WriteBuffer), 748931Sandreas.hansson@arm.com blkSize(blk_size), 758931Sandreas.hansson@arm.com lookupLatency(p->hit_latency), 768931Sandreas.hansson@arm.com forwardLatency(p->hit_latency), 7710482Sandreas.hansson@arm.com fillLatency(p->response_latency), 7810482Sandreas.hansson@arm.com responseLatency(p->response_latency), 7910482Sandreas.hansson@arm.com numTarget(p->tgts_per_mshr), 809293Sandreas.hansson@arm.com forwardSnoops(p->forward_snoops), 819293Sandreas.hansson@arm.com isReadOnly(p->is_read_only), 829293Sandreas.hansson@arm.com blocked(0), 839293Sandreas.hansson@arm.com order(0), 8410482Sandreas.hansson@arm.com noTargetMSHR(NULL), 8510482Sandreas.hansson@arm.com missCount(p->max_miss_count), 8610482Sandreas.hansson@arm.com addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 8710482Sandreas.hansson@arm.com system(p->system) 8810482Sandreas.hansson@arm.com{ 8910482Sandreas.hansson@arm.com} 9010482Sandreas.hansson@arm.com 9110482Sandreas.hansson@arm.comvoid 929293Sandreas.hansson@arm.comBaseCache::CacheSlavePort::setBlocked() 939293Sandreas.hansson@arm.com{ 949293Sandreas.hansson@arm.com assert(!blocked); 959293Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is blocking new requests\n"); 9610482Sandreas.hansson@arm.com blocked = true; 9710482Sandreas.hansson@arm.com // if we already scheduled a retry in this cycle, but it has not yet 988931Sandreas.hansson@arm.com // happened, cancel it 999293Sandreas.hansson@arm.com if (sendRetryEvent.scheduled()) { 1009293Sandreas.hansson@arm.com owner.deschedule(sendRetryEvent); 10110070Sandreas.hansson@arm.com DPRINTF(CachePort, "Port descheduled retry\n"); 10210070Sandreas.hansson@arm.com mustSendRetry = true; 10310070Sandreas.hansson@arm.com } 1049565Sandreas.hansson@arm.com} 1059293Sandreas.hansson@arm.com 10610482Sandreas.hansson@arm.comvoid 1079293Sandreas.hansson@arm.comBaseCache::CacheSlavePort::clearBlocked() 1089293Sandreas.hansson@arm.com{ 10910482Sandreas.hansson@arm.com assert(blocked); 1109565Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is accepting new requests\n"); 11110482Sandreas.hansson@arm.com blocked = false; 1129565Sandreas.hansson@arm.com if (mustSendRetry) { 1139565Sandreas.hansson@arm.com // @TODO: need to find a better time (next cycle?) 1149565Sandreas.hansson@arm.com owner.schedule(sendRetryEvent, curTick() + 1); 1159565Sandreas.hansson@arm.com } 11610482Sandreas.hansson@arm.com} 1179565Sandreas.hansson@arm.com 1189565Sandreas.hansson@arm.comvoid 1199565Sandreas.hansson@arm.comBaseCache::CacheSlavePort::processSendRetry() 1209565Sandreas.hansson@arm.com{ 1219565Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is sending retry\n"); 12210482Sandreas.hansson@arm.com 12310482Sandreas.hansson@arm.com // reset the flag and call retry 1249565Sandreas.hansson@arm.com mustSendRetry = false; 12510482Sandreas.hansson@arm.com sendRetryReq(); 12610482Sandreas.hansson@arm.com} 1279565Sandreas.hansson@arm.com 1289293Sandreas.hansson@arm.comvoid 1299293Sandreas.hansson@arm.comBaseCache::init() 1309565Sandreas.hansson@arm.com{ 1319565Sandreas.hansson@arm.com if (!cpuSidePort->isConnected() || !memSidePort->isConnected()) 1329565Sandreas.hansson@arm.com fatal("Cache ports on %s are not connected\n", name()); 1339565Sandreas.hansson@arm.com cpuSidePort->sendRangeChange(); 1349565Sandreas.hansson@arm.com} 1359565Sandreas.hansson@arm.com 1369565Sandreas.hansson@arm.comBaseMasterPort & 1379293Sandreas.hansson@arm.comBaseCache::getMasterPort(const std::string &if_name, PortID idx) 1389293Sandreas.hansson@arm.com{ 1399293Sandreas.hansson@arm.com if (if_name == "mem_side") { 1409293Sandreas.hansson@arm.com return *memSidePort; 1419293Sandreas.hansson@arm.com } else { 1429293Sandreas.hansson@arm.com return MemObject::getMasterPort(if_name, idx); 14310482Sandreas.hansson@arm.com } 14410482Sandreas.hansson@arm.com} 1459411Sandreas.hansson@arm.com 1469411Sandreas.hansson@arm.comBaseSlavePort & 1479293Sandreas.hansson@arm.comBaseCache::getSlavePort(const std::string &if_name, PortID idx) 14810405Sandreas.hansson@arm.com{ 1499411Sandreas.hansson@arm.com if (if_name == "cpu_side") { 1509293Sandreas.hansson@arm.com return *cpuSidePort; 1519293Sandreas.hansson@arm.com } else { 1529293Sandreas.hansson@arm.com return MemObject::getSlavePort(if_name, idx); 1539293Sandreas.hansson@arm.com } 1549293Sandreas.hansson@arm.com} 1559293Sandreas.hansson@arm.com 1569293Sandreas.hansson@arm.combool 1579405Sandreas.hansson@arm.comBaseCache::inRange(Addr addr) const 1589405Sandreas.hansson@arm.com{ 1599293Sandreas.hansson@arm.com for (const auto& r : addrRanges) { 1609293Sandreas.hansson@arm.com if (r.contains(addr)) { 1619293Sandreas.hansson@arm.com return true; 1629293Sandreas.hansson@arm.com } 1639293Sandreas.hansson@arm.com } 1649293Sandreas.hansson@arm.com return false; 16510070Sandreas.hansson@arm.com} 16610482Sandreas.hansson@arm.com 16710405Sandreas.hansson@arm.comvoid 16810482Sandreas.hansson@arm.comBaseCache::regStats() 16910482Sandreas.hansson@arm.com{ 1708931Sandreas.hansson@arm.com using namespace Stats; 1718931Sandreas.hansson@arm.com 1728931Sandreas.hansson@arm.com // Hit statistics 1739293Sandreas.hansson@arm.com for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1749293Sandreas.hansson@arm.com MemCmd cmd(access_idx); 1759293Sandreas.hansson@arm.com const string &cstr = cmd.toString(); 17610482Sandreas.hansson@arm.com 17710482Sandreas.hansson@arm.com hits[access_idx] 1789293Sandreas.hansson@arm.com .init(system->maxMasters()) 1799293Sandreas.hansson@arm.com .name(name() + "." + cstr + "_hits") 1808931Sandreas.hansson@arm.com .desc("number of " + cstr + " hits") 1818931Sandreas.hansson@arm.com .flags(total | nozero | nonan) 1828931Sandreas.hansson@arm.com ; 1838931Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1849405Sandreas.hansson@arm.com hits[access_idx].subname(i, system->getMasterName(i)); 1858931Sandreas.hansson@arm.com } 18610482Sandreas.hansson@arm.com } 1878931Sandreas.hansson@arm.com 1888931Sandreas.hansson@arm.com// These macros make it easier to sum the right subset of commands and 1898931Sandreas.hansson@arm.com// to change the subset of commands that are considered "demand" vs 1908931Sandreas.hansson@arm.com// "non-demand" 1918931Sandreas.hansson@arm.com#define SUM_DEMAND(s) \ 1928931Sandreas.hansson@arm.com (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + \ 1938851Sandreas.hansson@arm.com s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq]) 1948851Sandreas.hansson@arm.com 1958931Sandreas.hansson@arm.com// should writebacks be included here? prior code was inconsistent... 1965477Snate@binkert.org#define SUM_NON_DEMAND(s) \ 1978931Sandreas.hansson@arm.com (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 1988931Sandreas.hansson@arm.com 1998931Sandreas.hansson@arm.com demandHits 2007730SAli.Saidi@ARM.com .name(name() + ".demand_hits") 2018931Sandreas.hansson@arm.com .desc("number of demand (read+write) hits") 2028931Sandreas.hansson@arm.com .flags(total | nozero | nonan) 2038931Sandreas.hansson@arm.com ; 2048931Sandreas.hansson@arm.com demandHits = SUM_DEMAND(hits); 2058931Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2068931Sandreas.hansson@arm.com demandHits.subname(i, system->getMasterName(i)); 2079413Sandreas.hansson@arm.com } 20810482Sandreas.hansson@arm.com 20910482Sandreas.hansson@arm.com overallHits 2109413Sandreas.hansson@arm.com .name(name() + ".overall_hits") 21110482Sandreas.hansson@arm.com .desc("number of overall hits") 2129413Sandreas.hansson@arm.com .flags(total | nozero | nonan) 2139413Sandreas.hansson@arm.com ; 2149413Sandreas.hansson@arm.com overallHits = demandHits + SUM_NON_DEMAND(hits); 2159413Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21610482Sandreas.hansson@arm.com overallHits.subname(i, system->getMasterName(i)); 2179413Sandreas.hansson@arm.com } 2189413Sandreas.hansson@arm.com 2199413Sandreas.hansson@arm.com // Miss statistics 22010482Sandreas.hansson@arm.com for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2219413Sandreas.hansson@arm.com MemCmd cmd(access_idx); 2229413Sandreas.hansson@arm.com const string &cstr = cmd.toString(); 22310482Sandreas.hansson@arm.com 2249413Sandreas.hansson@arm.com misses[access_idx] 2258931Sandreas.hansson@arm.com .init(system->maxMasters()) 2267730SAli.Saidi@ARM.com .name(name() + "." + cstr + "_misses") 2272391SN/A .desc("number of " + cstr + " misses") 2289413Sandreas.hansson@arm.com .flags(total | nozero | nonan) 2299413Sandreas.hansson@arm.com ; 2309413Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2319413Sandreas.hansson@arm.com misses[access_idx].subname(i, system->getMasterName(i)); 2329413Sandreas.hansson@arm.com } 2339413Sandreas.hansson@arm.com } 2348931Sandreas.hansson@arm.com 2352391SN/A demandMisses 2362391SN/A .name(name() + ".demand_misses") 2372541SN/A .desc("number of demand (read+write) misses") 2388931Sandreas.hansson@arm.com .flags(total | nozero | nonan) 2392541SN/A ; 2408931Sandreas.hansson@arm.com demandMisses = SUM_DEMAND(misses); 2418931Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 24210482Sandreas.hansson@arm.com demandMisses.subname(i, system->getMasterName(i)); 2438931Sandreas.hansson@arm.com } 2448931Sandreas.hansson@arm.com 2452391SN/A overallMisses 2462391SN/A .name(name() + ".overall_misses") 2478719SAli.Saidi@ARM.com .desc("number of overall misses") 2488931Sandreas.hansson@arm.com .flags(total | nozero | nonan) 2498719SAli.Saidi@ARM.com ; 2508931Sandreas.hansson@arm.com overallMisses = demandMisses + SUM_NON_DEMAND(misses); 2518931Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 25210482Sandreas.hansson@arm.com overallMisses.subname(i, system->getMasterName(i)); 2538931Sandreas.hansson@arm.com } 2548931Sandreas.hansson@arm.com 2558719SAli.Saidi@ARM.com // Miss latency statistics 2569293Sandreas.hansson@arm.com for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2579293Sandreas.hansson@arm.com MemCmd cmd(access_idx); 2589293Sandreas.hansson@arm.com const string &cstr = cmd.toString(); 2599293Sandreas.hansson@arm.com 2609293Sandreas.hansson@arm.com missLatency[access_idx] 2619293Sandreas.hansson@arm.com .init(system->maxMasters()) 2629293Sandreas.hansson@arm.com .name(name() + "." + cstr + "_miss_latency") 2639293Sandreas.hansson@arm.com .desc("number of " + cstr + " miss cycles") 26410482Sandreas.hansson@arm.com .flags(total | nozero | nonan) 26510482Sandreas.hansson@arm.com ; 26610482Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 26710482Sandreas.hansson@arm.com missLatency[access_idx].subname(i, system->getMasterName(i)); 26810482Sandreas.hansson@arm.com } 2699293Sandreas.hansson@arm.com } 2709293Sandreas.hansson@arm.com 2719293Sandreas.hansson@arm.com demandMissLatency 2729293Sandreas.hansson@arm.com .name(name() + ".demand_miss_latency") 2739293Sandreas.hansson@arm.com .desc("number of demand (read+write) miss cycles") 2749293Sandreas.hansson@arm.com .flags(total | nozero | nonan) 2759293Sandreas.hansson@arm.com ; 2769293Sandreas.hansson@arm.com demandMissLatency = SUM_DEMAND(missLatency); 2779293Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2789293Sandreas.hansson@arm.com demandMissLatency.subname(i, system->getMasterName(i)); 2799293Sandreas.hansson@arm.com } 2809293Sandreas.hansson@arm.com 28110482Sandreas.hansson@arm.com overallMissLatency 2829293Sandreas.hansson@arm.com .name(name() + ".overall_miss_latency") 28310482Sandreas.hansson@arm.com .desc("number of overall miss cycles") 2849293Sandreas.hansson@arm.com .flags(total | nozero | nonan) 2859293Sandreas.hansson@arm.com ; 2869293Sandreas.hansson@arm.com overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 2879293Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2889293Sandreas.hansson@arm.com overallMissLatency.subname(i, system->getMasterName(i)); 2899293Sandreas.hansson@arm.com } 2909293Sandreas.hansson@arm.com 2919293Sandreas.hansson@arm.com // access formulas 2929293Sandreas.hansson@arm.com for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2939386Sandreas.hansson@arm.com MemCmd cmd(access_idx); 2949293Sandreas.hansson@arm.com const string &cstr = cmd.toString(); 2959293Sandreas.hansson@arm.com 2969293Sandreas.hansson@arm.com accesses[access_idx] 2979293Sandreas.hansson@arm.com .name(name() + "." + cstr + "_accesses") 2989293Sandreas.hansson@arm.com .desc("number of " + cstr + " accesses(hits+misses)") 2999293Sandreas.hansson@arm.com .flags(total | nozero | nonan) 3009293Sandreas.hansson@arm.com ; 3019293Sandreas.hansson@arm.com accesses[access_idx] = hits[access_idx] + misses[access_idx]; 3029293Sandreas.hansson@arm.com 3039293Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3049293Sandreas.hansson@arm.com accesses[access_idx].subname(i, system->getMasterName(i)); 30510412Sandreas.hansson@arm.com } 30610412Sandreas.hansson@arm.com } 3079293Sandreas.hansson@arm.com 3089293Sandreas.hansson@arm.com demandAccesses 3099293Sandreas.hansson@arm.com .name(name() + ".demand_accesses") 3109293Sandreas.hansson@arm.com .desc("number of demand (read+write) accesses") 3119293Sandreas.hansson@arm.com .flags(total | nozero | nonan) 3129293Sandreas.hansson@arm.com ; 3139293Sandreas.hansson@arm.com demandAccesses = demandHits + demandMisses; 3149293Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3159293Sandreas.hansson@arm.com demandAccesses.subname(i, system->getMasterName(i)); 3169293Sandreas.hansson@arm.com } 3179293Sandreas.hansson@arm.com 3189293Sandreas.hansson@arm.com overallAccesses 3199293Sandreas.hansson@arm.com .name(name() + ".overall_accesses") 3209293Sandreas.hansson@arm.com .desc("number of overall (read+write) accesses") 3219293Sandreas.hansson@arm.com .flags(total | nozero | nonan) 3229293Sandreas.hansson@arm.com ; 3239293Sandreas.hansson@arm.com overallAccesses = overallHits + overallMisses; 3249293Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3259293Sandreas.hansson@arm.com overallAccesses.subname(i, system->getMasterName(i)); 3269293Sandreas.hansson@arm.com } 3279293Sandreas.hansson@arm.com 3289293Sandreas.hansson@arm.com // miss rate formulas 3299293Sandreas.hansson@arm.com for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3309293Sandreas.hansson@arm.com MemCmd cmd(access_idx); 3319293Sandreas.hansson@arm.com const string &cstr = cmd.toString(); 3329293Sandreas.hansson@arm.com 3339293Sandreas.hansson@arm.com missRate[access_idx] 3349293Sandreas.hansson@arm.com .name(name() + "." + cstr + "_miss_rate") 3359293Sandreas.hansson@arm.com .desc("miss rate for " + cstr + " accesses") 3369293Sandreas.hansson@arm.com .flags(total | nozero | nonan) 3379293Sandreas.hansson@arm.com ; 3389293Sandreas.hansson@arm.com missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 3399293Sandreas.hansson@arm.com 3409293Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3419293Sandreas.hansson@arm.com missRate[access_idx].subname(i, system->getMasterName(i)); 3429293Sandreas.hansson@arm.com } 34310482Sandreas.hansson@arm.com } 3449293Sandreas.hansson@arm.com 3459293Sandreas.hansson@arm.com demandMissRate 3469293Sandreas.hansson@arm.com .name(name() + ".demand_miss_rate") 3479293Sandreas.hansson@arm.com .desc("miss rate for demand accesses") 3489293Sandreas.hansson@arm.com .flags(total | nozero | nonan) 3499293Sandreas.hansson@arm.com ; 3509293Sandreas.hansson@arm.com demandMissRate = demandMisses / demandAccesses; 3519293Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3529293Sandreas.hansson@arm.com demandMissRate.subname(i, system->getMasterName(i)); 3539293Sandreas.hansson@arm.com } 3549293Sandreas.hansson@arm.com 3559293Sandreas.hansson@arm.com overallMissRate 3569293Sandreas.hansson@arm.com .name(name() + ".overall_miss_rate") 3579293Sandreas.hansson@arm.com .desc("miss rate for overall accesses") 3589293Sandreas.hansson@arm.com .flags(total | nozero | nonan) 3599293Sandreas.hansson@arm.com ; 3609293Sandreas.hansson@arm.com overallMissRate = overallMisses / overallAccesses; 3619293Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3629293Sandreas.hansson@arm.com overallMissRate.subname(i, system->getMasterName(i)); 3639293Sandreas.hansson@arm.com } 3649293Sandreas.hansson@arm.com 3659293Sandreas.hansson@arm.com // miss latency formulas 3669293Sandreas.hansson@arm.com for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3679293Sandreas.hansson@arm.com MemCmd cmd(access_idx); 3689293Sandreas.hansson@arm.com const string &cstr = cmd.toString(); 3699293Sandreas.hansson@arm.com 37010412Sandreas.hansson@arm.com avgMissLatency[access_idx] 37110412Sandreas.hansson@arm.com .name(name() + "." + cstr + "_avg_miss_latency") 3729293Sandreas.hansson@arm.com .desc("average " + cstr + " miss latency") 3739293Sandreas.hansson@arm.com .flags(total | nozero | nonan) 37410070Sandreas.hansson@arm.com ; 3759293Sandreas.hansson@arm.com avgMissLatency[access_idx] = 3769293Sandreas.hansson@arm.com missLatency[access_idx] / misses[access_idx]; 3779293Sandreas.hansson@arm.com 3789293Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3799293Sandreas.hansson@arm.com avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 3809293Sandreas.hansson@arm.com } 3819293Sandreas.hansson@arm.com } 3829293Sandreas.hansson@arm.com 3839293Sandreas.hansson@arm.com demandAvgMissLatency 3849293Sandreas.hansson@arm.com .name(name() + ".demand_avg_miss_latency") 3859293Sandreas.hansson@arm.com .desc("average overall miss latency") 3869293Sandreas.hansson@arm.com .flags(total | nozero | nonan) 3879293Sandreas.hansson@arm.com ; 3889293Sandreas.hansson@arm.com demandAvgMissLatency = demandMissLatency / demandMisses; 3899293Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3909293Sandreas.hansson@arm.com demandAvgMissLatency.subname(i, system->getMasterName(i)); 3919293Sandreas.hansson@arm.com } 3929293Sandreas.hansson@arm.com 3939293Sandreas.hansson@arm.com overallAvgMissLatency 3949293Sandreas.hansson@arm.com .name(name() + ".overall_avg_miss_latency") 3959293Sandreas.hansson@arm.com .desc("average overall miss latency") 3969293Sandreas.hansson@arm.com .flags(total | nozero | nonan) 3979293Sandreas.hansson@arm.com ; 3989293Sandreas.hansson@arm.com overallAvgMissLatency = overallMissLatency / overallMisses; 3999293Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4009293Sandreas.hansson@arm.com overallAvgMissLatency.subname(i, system->getMasterName(i)); 4019293Sandreas.hansson@arm.com } 4029293Sandreas.hansson@arm.com 4039293Sandreas.hansson@arm.com blocked_cycles.init(NUM_BLOCKED_CAUSES); 4049293Sandreas.hansson@arm.com blocked_cycles 4059293Sandreas.hansson@arm.com .name(name() + ".blocked_cycles") 4069293Sandreas.hansson@arm.com .desc("number of cycles access was blocked") 4079293Sandreas.hansson@arm.com .subname(Blocked_NoMSHRs, "no_mshrs") 4089293Sandreas.hansson@arm.com .subname(Blocked_NoTargets, "no_targets") 4099293Sandreas.hansson@arm.com ; 4109293Sandreas.hansson@arm.com 4119293Sandreas.hansson@arm.com 4129293Sandreas.hansson@arm.com blocked_causes.init(NUM_BLOCKED_CAUSES); 4139293Sandreas.hansson@arm.com blocked_causes 4149293Sandreas.hansson@arm.com .name(name() + ".blocked") 4159293Sandreas.hansson@arm.com .desc("number of cycles access was blocked") 416 .subname(Blocked_NoMSHRs, "no_mshrs") 417 .subname(Blocked_NoTargets, "no_targets") 418 ; 419 420 avg_blocked 421 .name(name() + ".avg_blocked_cycles") 422 .desc("average number of cycles each access was blocked") 423 .subname(Blocked_NoMSHRs, "no_mshrs") 424 .subname(Blocked_NoTargets, "no_targets") 425 ; 426 427 avg_blocked = blocked_cycles / blocked_causes; 428 429 fastWrites 430 .name(name() + ".fast_writes") 431 .desc("number of fast writes performed") 432 ; 433 434 cacheCopies 435 .name(name() + ".cache_copies") 436 .desc("number of cache copies performed") 437 ; 438 439 writebacks 440 .init(system->maxMasters()) 441 .name(name() + ".writebacks") 442 .desc("number of writebacks") 443 .flags(total | nozero | nonan) 444 ; 445 for (int i = 0; i < system->maxMasters(); i++) { 446 writebacks.subname(i, system->getMasterName(i)); 447 } 448 449 // MSHR statistics 450 // MSHR hit statistics 451 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 452 MemCmd cmd(access_idx); 453 const string &cstr = cmd.toString(); 454 455 mshr_hits[access_idx] 456 .init(system->maxMasters()) 457 .name(name() + "." + cstr + "_mshr_hits") 458 .desc("number of " + cstr + " MSHR hits") 459 .flags(total | nozero | nonan) 460 ; 461 for (int i = 0; i < system->maxMasters(); i++) { 462 mshr_hits[access_idx].subname(i, system->getMasterName(i)); 463 } 464 } 465 466 demandMshrHits 467 .name(name() + ".demand_mshr_hits") 468 .desc("number of demand (read+write) MSHR hits") 469 .flags(total | nozero | nonan) 470 ; 471 demandMshrHits = SUM_DEMAND(mshr_hits); 472 for (int i = 0; i < system->maxMasters(); i++) { 473 demandMshrHits.subname(i, system->getMasterName(i)); 474 } 475 476 overallMshrHits 477 .name(name() + ".overall_mshr_hits") 478 .desc("number of overall MSHR hits") 479 .flags(total | nozero | nonan) 480 ; 481 overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 482 for (int i = 0; i < system->maxMasters(); i++) { 483 overallMshrHits.subname(i, system->getMasterName(i)); 484 } 485 486 // MSHR miss statistics 487 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 488 MemCmd cmd(access_idx); 489 const string &cstr = cmd.toString(); 490 491 mshr_misses[access_idx] 492 .init(system->maxMasters()) 493 .name(name() + "." + cstr + "_mshr_misses") 494 .desc("number of " + cstr + " MSHR misses") 495 .flags(total | nozero | nonan) 496 ; 497 for (int i = 0; i < system->maxMasters(); i++) { 498 mshr_misses[access_idx].subname(i, system->getMasterName(i)); 499 } 500 } 501 502 demandMshrMisses 503 .name(name() + ".demand_mshr_misses") 504 .desc("number of demand (read+write) MSHR misses") 505 .flags(total | nozero | nonan) 506 ; 507 demandMshrMisses = SUM_DEMAND(mshr_misses); 508 for (int i = 0; i < system->maxMasters(); i++) { 509 demandMshrMisses.subname(i, system->getMasterName(i)); 510 } 511 512 overallMshrMisses 513 .name(name() + ".overall_mshr_misses") 514 .desc("number of overall MSHR misses") 515 .flags(total | nozero | nonan) 516 ; 517 overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 518 for (int i = 0; i < system->maxMasters(); i++) { 519 overallMshrMisses.subname(i, system->getMasterName(i)); 520 } 521 522 // MSHR miss latency statistics 523 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 524 MemCmd cmd(access_idx); 525 const string &cstr = cmd.toString(); 526 527 mshr_miss_latency[access_idx] 528 .init(system->maxMasters()) 529 .name(name() + "." + cstr + "_mshr_miss_latency") 530 .desc("number of " + cstr + " MSHR miss cycles") 531 .flags(total | nozero | nonan) 532 ; 533 for (int i = 0; i < system->maxMasters(); i++) { 534 mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 535 } 536 } 537 538 demandMshrMissLatency 539 .name(name() + ".demand_mshr_miss_latency") 540 .desc("number of demand (read+write) MSHR miss cycles") 541 .flags(total | nozero | nonan) 542 ; 543 demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 544 for (int i = 0; i < system->maxMasters(); i++) { 545 demandMshrMissLatency.subname(i, system->getMasterName(i)); 546 } 547 548 overallMshrMissLatency 549 .name(name() + ".overall_mshr_miss_latency") 550 .desc("number of overall MSHR miss cycles") 551 .flags(total | nozero | nonan) 552 ; 553 overallMshrMissLatency = 554 demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 555 for (int i = 0; i < system->maxMasters(); i++) { 556 overallMshrMissLatency.subname(i, system->getMasterName(i)); 557 } 558 559 // MSHR uncacheable statistics 560 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 561 MemCmd cmd(access_idx); 562 const string &cstr = cmd.toString(); 563 564 mshr_uncacheable[access_idx] 565 .init(system->maxMasters()) 566 .name(name() + "." + cstr + "_mshr_uncacheable") 567 .desc("number of " + cstr + " MSHR uncacheable") 568 .flags(total | nozero | nonan) 569 ; 570 for (int i = 0; i < system->maxMasters(); i++) { 571 mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 572 } 573 } 574 575 overallMshrUncacheable 576 .name(name() + ".overall_mshr_uncacheable_misses") 577 .desc("number of overall MSHR uncacheable misses") 578 .flags(total | nozero | nonan) 579 ; 580 overallMshrUncacheable = 581 SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 582 for (int i = 0; i < system->maxMasters(); i++) { 583 overallMshrUncacheable.subname(i, system->getMasterName(i)); 584 } 585 586 // MSHR miss latency statistics 587 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 588 MemCmd cmd(access_idx); 589 const string &cstr = cmd.toString(); 590 591 mshr_uncacheable_lat[access_idx] 592 .init(system->maxMasters()) 593 .name(name() + "." + cstr + "_mshr_uncacheable_latency") 594 .desc("number of " + cstr + " MSHR uncacheable cycles") 595 .flags(total | nozero | nonan) 596 ; 597 for (int i = 0; i < system->maxMasters(); i++) { 598 mshr_uncacheable_lat[access_idx].subname(i, system->getMasterName(i)); 599 } 600 } 601 602 overallMshrUncacheableLatency 603 .name(name() + ".overall_mshr_uncacheable_latency") 604 .desc("number of overall MSHR uncacheable cycles") 605 .flags(total | nozero | nonan) 606 ; 607 overallMshrUncacheableLatency = 608 SUM_DEMAND(mshr_uncacheable_lat) + 609 SUM_NON_DEMAND(mshr_uncacheable_lat); 610 for (int i = 0; i < system->maxMasters(); i++) { 611 overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 612 } 613 614#if 0 615 // MSHR access formulas 616 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 617 MemCmd cmd(access_idx); 618 const string &cstr = cmd.toString(); 619 620 mshrAccesses[access_idx] 621 .name(name() + "." + cstr + "_mshr_accesses") 622 .desc("number of " + cstr + " mshr accesses(hits+misses)") 623 .flags(total | nozero | nonan) 624 ; 625 mshrAccesses[access_idx] = 626 mshr_hits[access_idx] + mshr_misses[access_idx] 627 + mshr_uncacheable[access_idx]; 628 } 629 630 demandMshrAccesses 631 .name(name() + ".demand_mshr_accesses") 632 .desc("number of demand (read+write) mshr accesses") 633 .flags(total | nozero | nonan) 634 ; 635 demandMshrAccesses = demandMshrHits + demandMshrMisses; 636 637 overallMshrAccesses 638 .name(name() + ".overall_mshr_accesses") 639 .desc("number of overall (read+write) mshr accesses") 640 .flags(total | nozero | nonan) 641 ; 642 overallMshrAccesses = overallMshrHits + overallMshrMisses 643 + overallMshrUncacheable; 644#endif 645 646 // MSHR miss rate formulas 647 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 648 MemCmd cmd(access_idx); 649 const string &cstr = cmd.toString(); 650 651 mshrMissRate[access_idx] 652 .name(name() + "." + cstr + "_mshr_miss_rate") 653 .desc("mshr miss rate for " + cstr + " accesses") 654 .flags(total | nozero | nonan) 655 ; 656 mshrMissRate[access_idx] = 657 mshr_misses[access_idx] / accesses[access_idx]; 658 659 for (int i = 0; i < system->maxMasters(); i++) { 660 mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 661 } 662 } 663 664 demandMshrMissRate 665 .name(name() + ".demand_mshr_miss_rate") 666 .desc("mshr miss rate for demand accesses") 667 .flags(total | nozero | nonan) 668 ; 669 demandMshrMissRate = demandMshrMisses / demandAccesses; 670 for (int i = 0; i < system->maxMasters(); i++) { 671 demandMshrMissRate.subname(i, system->getMasterName(i)); 672 } 673 674 overallMshrMissRate 675 .name(name() + ".overall_mshr_miss_rate") 676 .desc("mshr miss rate for overall accesses") 677 .flags(total | nozero | nonan) 678 ; 679 overallMshrMissRate = overallMshrMisses / overallAccesses; 680 for (int i = 0; i < system->maxMasters(); i++) { 681 overallMshrMissRate.subname(i, system->getMasterName(i)); 682 } 683 684 // mshrMiss latency formulas 685 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 686 MemCmd cmd(access_idx); 687 const string &cstr = cmd.toString(); 688 689 avgMshrMissLatency[access_idx] 690 .name(name() + "." + cstr + "_avg_mshr_miss_latency") 691 .desc("average " + cstr + " mshr miss latency") 692 .flags(total | nozero | nonan) 693 ; 694 avgMshrMissLatency[access_idx] = 695 mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 696 697 for (int i = 0; i < system->maxMasters(); i++) { 698 avgMshrMissLatency[access_idx].subname(i, system->getMasterName(i)); 699 } 700 } 701 702 demandAvgMshrMissLatency 703 .name(name() + ".demand_avg_mshr_miss_latency") 704 .desc("average overall mshr miss latency") 705 .flags(total | nozero | nonan) 706 ; 707 demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 708 for (int i = 0; i < system->maxMasters(); i++) { 709 demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 710 } 711 712 overallAvgMshrMissLatency 713 .name(name() + ".overall_avg_mshr_miss_latency") 714 .desc("average overall mshr miss latency") 715 .flags(total | nozero | nonan) 716 ; 717 overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 718 for (int i = 0; i < system->maxMasters(); i++) { 719 overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 720 } 721 722 // mshrUncacheable latency formulas 723 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 724 MemCmd cmd(access_idx); 725 const string &cstr = cmd.toString(); 726 727 avgMshrUncacheableLatency[access_idx] 728 .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 729 .desc("average " + cstr + " mshr uncacheable latency") 730 .flags(total | nozero | nonan) 731 ; 732 avgMshrUncacheableLatency[access_idx] = 733 mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 734 735 for (int i = 0; i < system->maxMasters(); i++) { 736 avgMshrUncacheableLatency[access_idx].subname(i, system->getMasterName(i)); 737 } 738 } 739 740 overallAvgMshrUncacheableLatency 741 .name(name() + ".overall_avg_mshr_uncacheable_latency") 742 .desc("average overall mshr uncacheable latency") 743 .flags(total | nozero | nonan) 744 ; 745 overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable; 746 for (int i = 0; i < system->maxMasters(); i++) { 747 overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 748 } 749 750 mshr_cap_events 751 .init(system->maxMasters()) 752 .name(name() + ".mshr_cap_events") 753 .desc("number of times MSHR cap was activated") 754 .flags(total | nozero | nonan) 755 ; 756 for (int i = 0; i < system->maxMasters(); i++) { 757 mshr_cap_events.subname(i, system->getMasterName(i)); 758 } 759 760 //software prefetching stats 761 soft_prefetch_mshr_full 762 .init(system->maxMasters()) 763 .name(name() + ".soft_prefetch_mshr_full") 764 .desc("number of mshr full events for SW prefetching instrutions") 765 .flags(total | nozero | nonan) 766 ; 767 for (int i = 0; i < system->maxMasters(); i++) { 768 soft_prefetch_mshr_full.subname(i, system->getMasterName(i)); 769 } 770 771 mshr_no_allocate_misses 772 .name(name() +".no_allocate_misses") 773 .desc("Number of misses that were no-allocate") 774 ; 775 776} 777