base.cc revision 10622
12810SN/A/* 29614Srene.dejong@arm.com * Copyright (c) 2012-2013 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 412810SN/A */ 422810SN/A 432810SN/A/** 442810SN/A * @file 452810SN/A * Definition of BaseCache functions. 462810SN/A */ 472810SN/A 488232Snate@binkert.org#include "debug/Cache.hh" 499152Satgutier@umich.edu#include "debug/Drain.hh" 509795Sandreas.hansson@arm.com#include "mem/cache/tags/fa_lru.hh" 519795Sandreas.hansson@arm.com#include "mem/cache/tags/lru.hh" 5210263Satgutier@umich.edu#include "mem/cache/tags/random_repl.hh" 535338Sstever@gmail.com#include "mem/cache/base.hh" 549795Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 555338Sstever@gmail.com#include "mem/cache/mshr.hh" 568786Sgblack@eecs.umich.edu#include "sim/full_system.hh" 572810SN/A 582810SN/Ausing namespace std; 592810SN/A 608856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 618856Sandreas.hansson@arm.com BaseCache *_cache, 628856Sandreas.hansson@arm.com const std::string &_label) 638922Swilliam.wang@arm.com : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 648914Sandreas.hansson@arm.com blocked(false), mustSendRetry(false), sendRetryEvent(this) 658856Sandreas.hansson@arm.com{ 668856Sandreas.hansson@arm.com} 674475SN/A 685034SN/ABaseCache::BaseCache(const Params *p) 695034SN/A : MemObject(p), 7010360Sandreas.hansson@arm.com cpuSidePort(nullptr), memSidePort(nullptr), 7110622Smitch.hayenga@arm.com mshrQueue("MSHRs", p->mshrs, 4, p->demand_mshr_reserve, MSHRQueue_MSHRs), 7210622Smitch.hayenga@arm.com writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 0, 734628SN/A MSHRQueue_WriteBuffer), 749814Sandreas.hansson@arm.com blkSize(p->system->cacheLineSize()), 759263Smrinmoy.ghosh@arm.com hitLatency(p->hit_latency), 769263Smrinmoy.ghosh@arm.com responseLatency(p->response_latency), 775034SN/A numTarget(p->tgts_per_mshr), 786122SSteve.Reinhardt@amd.com forwardSnoops(p->forward_snoops), 798134SAli.Saidi@ARM.com isTopLevel(p->is_top_level), 804626SN/A blocked(0), 8110360Sandreas.hansson@arm.com order(0), 824626SN/A noTargetMSHR(NULL), 835034SN/A missCount(p->max_miss_count), 848883SAli.Saidi@ARM.com addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 858833Sdam.sunwoo@arm.com system(p->system) 864458SN/A{ 872810SN/A} 882810SN/A 893013SN/Avoid 908856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::setBlocked() 912810SN/A{ 923013SN/A assert(!blocked); 938856Sandreas.hansson@arm.com DPRINTF(CachePort, "Cache port %s blocking new requests\n", name()); 942810SN/A blocked = true; 959614Srene.dejong@arm.com // if we already scheduled a retry in this cycle, but it has not yet 969614Srene.dejong@arm.com // happened, cancel it 979614Srene.dejong@arm.com if (sendRetryEvent.scheduled()) { 9810345SCurtis.Dunham@arm.com owner.deschedule(sendRetryEvent); 9910345SCurtis.Dunham@arm.com DPRINTF(CachePort, "Cache port %s deschedule retry\n", name()); 10010345SCurtis.Dunham@arm.com mustSendRetry = true; 1019614Srene.dejong@arm.com } 1022810SN/A} 1032810SN/A 1042810SN/Avoid 1058856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::clearBlocked() 1062810SN/A{ 1073013SN/A assert(blocked); 1088856Sandreas.hansson@arm.com DPRINTF(CachePort, "Cache port %s accepting new requests\n", name()); 1093013SN/A blocked = false; 1108856Sandreas.hansson@arm.com if (mustSendRetry) { 1114666SN/A // @TODO: need to find a better time (next bus cycle?) 1128922Swilliam.wang@arm.com owner.schedule(sendRetryEvent, curTick() + 1); 1132897SN/A } 1142810SN/A} 1152810SN/A 11610344Sandreas.hansson@arm.comvoid 11710344Sandreas.hansson@arm.comBaseCache::CacheSlavePort::processSendRetry() 11810344Sandreas.hansson@arm.com{ 11910344Sandreas.hansson@arm.com DPRINTF(CachePort, "Cache port %s sending retry\n", name()); 12010344Sandreas.hansson@arm.com 12110344Sandreas.hansson@arm.com // reset the flag and call retry 12210344Sandreas.hansson@arm.com mustSendRetry = false; 12310344Sandreas.hansson@arm.com sendRetry(); 12410344Sandreas.hansson@arm.com} 1252844SN/A 1262810SN/Avoid 1272858SN/ABaseCache::init() 1282858SN/A{ 1298856Sandreas.hansson@arm.com if (!cpuSidePort->isConnected() || !memSidePort->isConnected()) 1308922Swilliam.wang@arm.com fatal("Cache ports on %s are not connected\n", name()); 1318711Sandreas.hansson@arm.com cpuSidePort->sendRangeChange(); 1322858SN/A} 1332858SN/A 1349294Sandreas.hansson@arm.comBaseMasterPort & 1359294Sandreas.hansson@arm.comBaseCache::getMasterPort(const std::string &if_name, PortID idx) 1368922Swilliam.wang@arm.com{ 1378922Swilliam.wang@arm.com if (if_name == "mem_side") { 1388922Swilliam.wang@arm.com return *memSidePort; 1398922Swilliam.wang@arm.com } else { 1408922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1418922Swilliam.wang@arm.com } 1428922Swilliam.wang@arm.com} 1438922Swilliam.wang@arm.com 1449294Sandreas.hansson@arm.comBaseSlavePort & 1459294Sandreas.hansson@arm.comBaseCache::getSlavePort(const std::string &if_name, PortID idx) 1468922Swilliam.wang@arm.com{ 1478922Swilliam.wang@arm.com if (if_name == "cpu_side") { 1488922Swilliam.wang@arm.com return *cpuSidePort; 1498922Swilliam.wang@arm.com } else { 1508922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 1518922Swilliam.wang@arm.com } 1528922Swilliam.wang@arm.com} 1534628SN/A 1542858SN/Avoid 1552810SN/ABaseCache::regStats() 1562810SN/A{ 1572810SN/A using namespace Stats; 1582810SN/A 1592810SN/A // Hit statistics 1604022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1614022SN/A MemCmd cmd(access_idx); 1624022SN/A const string &cstr = cmd.toString(); 1632810SN/A 1642810SN/A hits[access_idx] 1658833Sdam.sunwoo@arm.com .init(system->maxMasters()) 1662810SN/A .name(name() + "." + cstr + "_hits") 1672810SN/A .desc("number of " + cstr + " hits") 1682810SN/A .flags(total | nozero | nonan) 1692810SN/A ; 1708833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1718833Sdam.sunwoo@arm.com hits[access_idx].subname(i, system->getMasterName(i)); 1728833Sdam.sunwoo@arm.com } 1732810SN/A } 1742810SN/A 1754871SN/A// These macros make it easier to sum the right subset of commands and 1764871SN/A// to change the subset of commands that are considered "demand" vs 1774871SN/A// "non-demand" 1784871SN/A#define SUM_DEMAND(s) \ 1794871SN/A (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::ReadExReq]) 1804871SN/A 1814871SN/A// should writebacks be included here? prior code was inconsistent... 1824871SN/A#define SUM_NON_DEMAND(s) \ 1834871SN/A (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 1844871SN/A 1852810SN/A demandHits 1862810SN/A .name(name() + ".demand_hits") 1872810SN/A .desc("number of demand (read+write) hits") 1888833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1892810SN/A ; 1904871SN/A demandHits = SUM_DEMAND(hits); 1918833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1928833Sdam.sunwoo@arm.com demandHits.subname(i, system->getMasterName(i)); 1938833Sdam.sunwoo@arm.com } 1942810SN/A 1952810SN/A overallHits 1962810SN/A .name(name() + ".overall_hits") 1972810SN/A .desc("number of overall hits") 1988833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1992810SN/A ; 2004871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 2018833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2028833Sdam.sunwoo@arm.com overallHits.subname(i, system->getMasterName(i)); 2038833Sdam.sunwoo@arm.com } 2042810SN/A 2052810SN/A // Miss statistics 2064022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2074022SN/A MemCmd cmd(access_idx); 2084022SN/A const string &cstr = cmd.toString(); 2092810SN/A 2102810SN/A misses[access_idx] 2118833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2122810SN/A .name(name() + "." + cstr + "_misses") 2132810SN/A .desc("number of " + cstr + " misses") 2142810SN/A .flags(total | nozero | nonan) 2152810SN/A ; 2168833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2178833Sdam.sunwoo@arm.com misses[access_idx].subname(i, system->getMasterName(i)); 2188833Sdam.sunwoo@arm.com } 2192810SN/A } 2202810SN/A 2212810SN/A demandMisses 2222810SN/A .name(name() + ".demand_misses") 2232810SN/A .desc("number of demand (read+write) misses") 2248833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2252810SN/A ; 2264871SN/A demandMisses = SUM_DEMAND(misses); 2278833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2288833Sdam.sunwoo@arm.com demandMisses.subname(i, system->getMasterName(i)); 2298833Sdam.sunwoo@arm.com } 2302810SN/A 2312810SN/A overallMisses 2322810SN/A .name(name() + ".overall_misses") 2332810SN/A .desc("number of overall misses") 2348833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2352810SN/A ; 2364871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 2378833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2388833Sdam.sunwoo@arm.com overallMisses.subname(i, system->getMasterName(i)); 2398833Sdam.sunwoo@arm.com } 2402810SN/A 2412810SN/A // Miss latency statistics 2424022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2434022SN/A MemCmd cmd(access_idx); 2444022SN/A const string &cstr = cmd.toString(); 2452810SN/A 2462810SN/A missLatency[access_idx] 2478833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2482810SN/A .name(name() + "." + cstr + "_miss_latency") 2492810SN/A .desc("number of " + cstr + " miss cycles") 2502810SN/A .flags(total | nozero | nonan) 2512810SN/A ; 2528833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2538833Sdam.sunwoo@arm.com missLatency[access_idx].subname(i, system->getMasterName(i)); 2548833Sdam.sunwoo@arm.com } 2552810SN/A } 2562810SN/A 2572810SN/A demandMissLatency 2582810SN/A .name(name() + ".demand_miss_latency") 2592810SN/A .desc("number of demand (read+write) miss cycles") 2608833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2612810SN/A ; 2624871SN/A demandMissLatency = SUM_DEMAND(missLatency); 2638833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2648833Sdam.sunwoo@arm.com demandMissLatency.subname(i, system->getMasterName(i)); 2658833Sdam.sunwoo@arm.com } 2662810SN/A 2672810SN/A overallMissLatency 2682810SN/A .name(name() + ".overall_miss_latency") 2692810SN/A .desc("number of overall miss cycles") 2708833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2712810SN/A ; 2724871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 2738833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2748833Sdam.sunwoo@arm.com overallMissLatency.subname(i, system->getMasterName(i)); 2758833Sdam.sunwoo@arm.com } 2762810SN/A 2772810SN/A // access formulas 2784022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2794022SN/A MemCmd cmd(access_idx); 2804022SN/A const string &cstr = cmd.toString(); 2812810SN/A 2822810SN/A accesses[access_idx] 2832810SN/A .name(name() + "." + cstr + "_accesses") 2842810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 2852810SN/A .flags(total | nozero | nonan) 2862810SN/A ; 2878833Sdam.sunwoo@arm.com accesses[access_idx] = hits[access_idx] + misses[access_idx]; 2882810SN/A 2898833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2908833Sdam.sunwoo@arm.com accesses[access_idx].subname(i, system->getMasterName(i)); 2918833Sdam.sunwoo@arm.com } 2922810SN/A } 2932810SN/A 2942810SN/A demandAccesses 2952810SN/A .name(name() + ".demand_accesses") 2962810SN/A .desc("number of demand (read+write) accesses") 2978833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2982810SN/A ; 2992810SN/A demandAccesses = demandHits + demandMisses; 3008833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3018833Sdam.sunwoo@arm.com demandAccesses.subname(i, system->getMasterName(i)); 3028833Sdam.sunwoo@arm.com } 3032810SN/A 3042810SN/A overallAccesses 3052810SN/A .name(name() + ".overall_accesses") 3062810SN/A .desc("number of overall (read+write) accesses") 3078833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3082810SN/A ; 3092810SN/A overallAccesses = overallHits + overallMisses; 3108833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3118833Sdam.sunwoo@arm.com overallAccesses.subname(i, system->getMasterName(i)); 3128833Sdam.sunwoo@arm.com } 3132810SN/A 3142810SN/A // miss rate formulas 3154022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3164022SN/A MemCmd cmd(access_idx); 3174022SN/A const string &cstr = cmd.toString(); 3182810SN/A 3192810SN/A missRate[access_idx] 3202810SN/A .name(name() + "." + cstr + "_miss_rate") 3212810SN/A .desc("miss rate for " + cstr + " accesses") 3222810SN/A .flags(total | nozero | nonan) 3232810SN/A ; 3248833Sdam.sunwoo@arm.com missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 3252810SN/A 3268833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3278833Sdam.sunwoo@arm.com missRate[access_idx].subname(i, system->getMasterName(i)); 3288833Sdam.sunwoo@arm.com } 3292810SN/A } 3302810SN/A 3312810SN/A demandMissRate 3322810SN/A .name(name() + ".demand_miss_rate") 3332810SN/A .desc("miss rate for demand accesses") 3348833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3352810SN/A ; 3362810SN/A demandMissRate = demandMisses / demandAccesses; 3378833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3388833Sdam.sunwoo@arm.com demandMissRate.subname(i, system->getMasterName(i)); 3398833Sdam.sunwoo@arm.com } 3402810SN/A 3412810SN/A overallMissRate 3422810SN/A .name(name() + ".overall_miss_rate") 3432810SN/A .desc("miss rate for overall accesses") 3448833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3452810SN/A ; 3462810SN/A overallMissRate = overallMisses / overallAccesses; 3478833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3488833Sdam.sunwoo@arm.com overallMissRate.subname(i, system->getMasterName(i)); 3498833Sdam.sunwoo@arm.com } 3502810SN/A 3512810SN/A // miss latency formulas 3524022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3534022SN/A MemCmd cmd(access_idx); 3544022SN/A const string &cstr = cmd.toString(); 3552810SN/A 3562810SN/A avgMissLatency[access_idx] 3572810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 3582810SN/A .desc("average " + cstr + " miss latency") 3592810SN/A .flags(total | nozero | nonan) 3602810SN/A ; 3612810SN/A avgMissLatency[access_idx] = 3622810SN/A missLatency[access_idx] / misses[access_idx]; 3638833Sdam.sunwoo@arm.com 3648833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3658833Sdam.sunwoo@arm.com avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 3668833Sdam.sunwoo@arm.com } 3672810SN/A } 3682810SN/A 3692810SN/A demandAvgMissLatency 3702810SN/A .name(name() + ".demand_avg_miss_latency") 3712810SN/A .desc("average overall miss latency") 3728833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3732810SN/A ; 3742810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 3758833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3768833Sdam.sunwoo@arm.com demandAvgMissLatency.subname(i, system->getMasterName(i)); 3778833Sdam.sunwoo@arm.com } 3782810SN/A 3792810SN/A overallAvgMissLatency 3802810SN/A .name(name() + ".overall_avg_miss_latency") 3812810SN/A .desc("average overall miss latency") 3828833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3832810SN/A ; 3842810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 3858833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3868833Sdam.sunwoo@arm.com overallAvgMissLatency.subname(i, system->getMasterName(i)); 3878833Sdam.sunwoo@arm.com } 3882810SN/A 3892810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 3902810SN/A blocked_cycles 3912810SN/A .name(name() + ".blocked_cycles") 3922810SN/A .desc("number of cycles access was blocked") 3932810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3942810SN/A .subname(Blocked_NoTargets, "no_targets") 3952810SN/A ; 3962810SN/A 3972810SN/A 3982810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 3992810SN/A blocked_causes 4002810SN/A .name(name() + ".blocked") 4012810SN/A .desc("number of cycles access was blocked") 4022810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4032810SN/A .subname(Blocked_NoTargets, "no_targets") 4042810SN/A ; 4052810SN/A 4062810SN/A avg_blocked 4072810SN/A .name(name() + ".avg_blocked_cycles") 4082810SN/A .desc("average number of cycles each access was blocked") 4092810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4102810SN/A .subname(Blocked_NoTargets, "no_targets") 4112810SN/A ; 4122810SN/A 4132810SN/A avg_blocked = blocked_cycles / blocked_causes; 4142810SN/A 4152810SN/A fastWrites 4162810SN/A .name(name() + ".fast_writes") 4172810SN/A .desc("number of fast writes performed") 4182810SN/A ; 4192810SN/A 4202810SN/A cacheCopies 4212810SN/A .name(name() + ".cache_copies") 4222810SN/A .desc("number of cache copies performed") 4232810SN/A ; 4242826SN/A 4254626SN/A writebacks 4268833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4274626SN/A .name(name() + ".writebacks") 4284626SN/A .desc("number of writebacks") 4298833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4304626SN/A ; 4318833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4328833Sdam.sunwoo@arm.com writebacks.subname(i, system->getMasterName(i)); 4338833Sdam.sunwoo@arm.com } 4344626SN/A 4354626SN/A // MSHR statistics 4364626SN/A // MSHR hit statistics 4374626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4384626SN/A MemCmd cmd(access_idx); 4394626SN/A const string &cstr = cmd.toString(); 4404626SN/A 4414626SN/A mshr_hits[access_idx] 4428833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4434626SN/A .name(name() + "." + cstr + "_mshr_hits") 4444626SN/A .desc("number of " + cstr + " MSHR hits") 4454626SN/A .flags(total | nozero | nonan) 4464626SN/A ; 4478833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4488833Sdam.sunwoo@arm.com mshr_hits[access_idx].subname(i, system->getMasterName(i)); 4498833Sdam.sunwoo@arm.com } 4504626SN/A } 4514626SN/A 4524626SN/A demandMshrHits 4534626SN/A .name(name() + ".demand_mshr_hits") 4544626SN/A .desc("number of demand (read+write) MSHR hits") 4558833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4564626SN/A ; 4574871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 4588833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4598833Sdam.sunwoo@arm.com demandMshrHits.subname(i, system->getMasterName(i)); 4608833Sdam.sunwoo@arm.com } 4614626SN/A 4624626SN/A overallMshrHits 4634626SN/A .name(name() + ".overall_mshr_hits") 4644626SN/A .desc("number of overall MSHR hits") 4658833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4664626SN/A ; 4674871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 4688833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4698833Sdam.sunwoo@arm.com overallMshrHits.subname(i, system->getMasterName(i)); 4708833Sdam.sunwoo@arm.com } 4714626SN/A 4724626SN/A // MSHR miss statistics 4734626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4744626SN/A MemCmd cmd(access_idx); 4754626SN/A const string &cstr = cmd.toString(); 4764626SN/A 4774626SN/A mshr_misses[access_idx] 4788833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4794626SN/A .name(name() + "." + cstr + "_mshr_misses") 4804626SN/A .desc("number of " + cstr + " MSHR misses") 4814626SN/A .flags(total | nozero | nonan) 4824626SN/A ; 4838833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4848833Sdam.sunwoo@arm.com mshr_misses[access_idx].subname(i, system->getMasterName(i)); 4858833Sdam.sunwoo@arm.com } 4864626SN/A } 4874626SN/A 4884626SN/A demandMshrMisses 4894626SN/A .name(name() + ".demand_mshr_misses") 4904626SN/A .desc("number of demand (read+write) MSHR misses") 4918833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4924626SN/A ; 4934871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 4948833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4958833Sdam.sunwoo@arm.com demandMshrMisses.subname(i, system->getMasterName(i)); 4968833Sdam.sunwoo@arm.com } 4974626SN/A 4984626SN/A overallMshrMisses 4994626SN/A .name(name() + ".overall_mshr_misses") 5004626SN/A .desc("number of overall MSHR misses") 5018833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5024626SN/A ; 5034871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 5048833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5058833Sdam.sunwoo@arm.com overallMshrMisses.subname(i, system->getMasterName(i)); 5068833Sdam.sunwoo@arm.com } 5074626SN/A 5084626SN/A // MSHR miss latency statistics 5094626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5104626SN/A MemCmd cmd(access_idx); 5114626SN/A const string &cstr = cmd.toString(); 5124626SN/A 5134626SN/A mshr_miss_latency[access_idx] 5148833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5154626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 5164626SN/A .desc("number of " + cstr + " MSHR miss cycles") 5174626SN/A .flags(total | nozero | nonan) 5184626SN/A ; 5198833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5208833Sdam.sunwoo@arm.com mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 5218833Sdam.sunwoo@arm.com } 5224626SN/A } 5234626SN/A 5244626SN/A demandMshrMissLatency 5254626SN/A .name(name() + ".demand_mshr_miss_latency") 5264626SN/A .desc("number of demand (read+write) MSHR miss cycles") 5278833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5284626SN/A ; 5294871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 5308833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5318833Sdam.sunwoo@arm.com demandMshrMissLatency.subname(i, system->getMasterName(i)); 5328833Sdam.sunwoo@arm.com } 5334626SN/A 5344626SN/A overallMshrMissLatency 5354626SN/A .name(name() + ".overall_mshr_miss_latency") 5364626SN/A .desc("number of overall MSHR miss cycles") 5378833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5384626SN/A ; 5394871SN/A overallMshrMissLatency = 5404871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 5418833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5428833Sdam.sunwoo@arm.com overallMshrMissLatency.subname(i, system->getMasterName(i)); 5438833Sdam.sunwoo@arm.com } 5444626SN/A 5454626SN/A // MSHR uncacheable statistics 5464626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5474626SN/A MemCmd cmd(access_idx); 5484626SN/A const string &cstr = cmd.toString(); 5494626SN/A 5504626SN/A mshr_uncacheable[access_idx] 5518833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5524626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 5534626SN/A .desc("number of " + cstr + " MSHR uncacheable") 5544626SN/A .flags(total | nozero | nonan) 5554626SN/A ; 5568833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5578833Sdam.sunwoo@arm.com mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 5588833Sdam.sunwoo@arm.com } 5594626SN/A } 5604626SN/A 5614626SN/A overallMshrUncacheable 5624626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 5634626SN/A .desc("number of overall MSHR uncacheable misses") 5648833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5654626SN/A ; 5664871SN/A overallMshrUncacheable = 5674871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 5688833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5698833Sdam.sunwoo@arm.com overallMshrUncacheable.subname(i, system->getMasterName(i)); 5708833Sdam.sunwoo@arm.com } 5714626SN/A 5724626SN/A // MSHR miss latency statistics 5734626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5744626SN/A MemCmd cmd(access_idx); 5754626SN/A const string &cstr = cmd.toString(); 5764626SN/A 5774626SN/A mshr_uncacheable_lat[access_idx] 5788833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5794626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 5804626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 5814626SN/A .flags(total | nozero | nonan) 5824626SN/A ; 5838833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5848833Sdam.sunwoo@arm.com mshr_uncacheable_lat[access_idx].subname(i, system->getMasterName(i)); 5858833Sdam.sunwoo@arm.com } 5864626SN/A } 5874626SN/A 5884626SN/A overallMshrUncacheableLatency 5894626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 5904626SN/A .desc("number of overall MSHR uncacheable cycles") 5918833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5924626SN/A ; 5934871SN/A overallMshrUncacheableLatency = 5944871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 5954871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 5968833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5978833Sdam.sunwoo@arm.com overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 5988833Sdam.sunwoo@arm.com } 5994626SN/A 6004626SN/A#if 0 6014626SN/A // MSHR access formulas 6024626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6034626SN/A MemCmd cmd(access_idx); 6044626SN/A const string &cstr = cmd.toString(); 6054626SN/A 6064626SN/A mshrAccesses[access_idx] 6074626SN/A .name(name() + "." + cstr + "_mshr_accesses") 6084626SN/A .desc("number of " + cstr + " mshr accesses(hits+misses)") 6094626SN/A .flags(total | nozero | nonan) 6104626SN/A ; 6114626SN/A mshrAccesses[access_idx] = 6124626SN/A mshr_hits[access_idx] + mshr_misses[access_idx] 6134626SN/A + mshr_uncacheable[access_idx]; 6144626SN/A } 6154626SN/A 6164626SN/A demandMshrAccesses 6174626SN/A .name(name() + ".demand_mshr_accesses") 6184626SN/A .desc("number of demand (read+write) mshr accesses") 6194626SN/A .flags(total | nozero | nonan) 6204626SN/A ; 6214626SN/A demandMshrAccesses = demandMshrHits + demandMshrMisses; 6224626SN/A 6234626SN/A overallMshrAccesses 6244626SN/A .name(name() + ".overall_mshr_accesses") 6254626SN/A .desc("number of overall (read+write) mshr accesses") 6264626SN/A .flags(total | nozero | nonan) 6274626SN/A ; 6284626SN/A overallMshrAccesses = overallMshrHits + overallMshrMisses 6294626SN/A + overallMshrUncacheable; 6304626SN/A#endif 6314626SN/A 6324626SN/A // MSHR miss rate formulas 6334626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6344626SN/A MemCmd cmd(access_idx); 6354626SN/A const string &cstr = cmd.toString(); 6364626SN/A 6374626SN/A mshrMissRate[access_idx] 6384626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 6394626SN/A .desc("mshr miss rate for " + cstr + " accesses") 6404626SN/A .flags(total | nozero | nonan) 6414626SN/A ; 6424626SN/A mshrMissRate[access_idx] = 6434626SN/A mshr_misses[access_idx] / accesses[access_idx]; 6448833Sdam.sunwoo@arm.com 6458833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6468833Sdam.sunwoo@arm.com mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 6478833Sdam.sunwoo@arm.com } 6484626SN/A } 6494626SN/A 6504626SN/A demandMshrMissRate 6514626SN/A .name(name() + ".demand_mshr_miss_rate") 6524626SN/A .desc("mshr miss rate for demand accesses") 6538833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6544626SN/A ; 6554626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 6568833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6578833Sdam.sunwoo@arm.com demandMshrMissRate.subname(i, system->getMasterName(i)); 6588833Sdam.sunwoo@arm.com } 6594626SN/A 6604626SN/A overallMshrMissRate 6614626SN/A .name(name() + ".overall_mshr_miss_rate") 6624626SN/A .desc("mshr miss rate for overall accesses") 6638833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6644626SN/A ; 6654626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 6668833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6678833Sdam.sunwoo@arm.com overallMshrMissRate.subname(i, system->getMasterName(i)); 6688833Sdam.sunwoo@arm.com } 6694626SN/A 6704626SN/A // mshrMiss latency formulas 6714626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6724626SN/A MemCmd cmd(access_idx); 6734626SN/A const string &cstr = cmd.toString(); 6744626SN/A 6754626SN/A avgMshrMissLatency[access_idx] 6764626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 6774626SN/A .desc("average " + cstr + " mshr miss latency") 6784626SN/A .flags(total | nozero | nonan) 6794626SN/A ; 6804626SN/A avgMshrMissLatency[access_idx] = 6814626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 6828833Sdam.sunwoo@arm.com 6838833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6848833Sdam.sunwoo@arm.com avgMshrMissLatency[access_idx].subname(i, system->getMasterName(i)); 6858833Sdam.sunwoo@arm.com } 6864626SN/A } 6874626SN/A 6884626SN/A demandAvgMshrMissLatency 6894626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 6904626SN/A .desc("average overall mshr miss latency") 6918833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6924626SN/A ; 6934626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 6948833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6958833Sdam.sunwoo@arm.com demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 6968833Sdam.sunwoo@arm.com } 6974626SN/A 6984626SN/A overallAvgMshrMissLatency 6994626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 7004626SN/A .desc("average overall mshr miss latency") 7018833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7024626SN/A ; 7034626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 7048833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7058833Sdam.sunwoo@arm.com overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 7068833Sdam.sunwoo@arm.com } 7074626SN/A 7084626SN/A // mshrUncacheable latency formulas 7094626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 7104626SN/A MemCmd cmd(access_idx); 7114626SN/A const string &cstr = cmd.toString(); 7124626SN/A 7134626SN/A avgMshrUncacheableLatency[access_idx] 7144626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 7154626SN/A .desc("average " + cstr + " mshr uncacheable latency") 7164626SN/A .flags(total | nozero | nonan) 7174626SN/A ; 7184626SN/A avgMshrUncacheableLatency[access_idx] = 7194626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 7208833Sdam.sunwoo@arm.com 7218833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7228833Sdam.sunwoo@arm.com avgMshrUncacheableLatency[access_idx].subname(i, system->getMasterName(i)); 7238833Sdam.sunwoo@arm.com } 7244626SN/A } 7254626SN/A 7264626SN/A overallAvgMshrUncacheableLatency 7274626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 7284626SN/A .desc("average overall mshr uncacheable latency") 7298833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7304626SN/A ; 7314626SN/A overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable; 7328833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7338833Sdam.sunwoo@arm.com overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 7348833Sdam.sunwoo@arm.com } 7354626SN/A 7364626SN/A mshr_cap_events 7378833Sdam.sunwoo@arm.com .init(system->maxMasters()) 7384626SN/A .name(name() + ".mshr_cap_events") 7394626SN/A .desc("number of times MSHR cap was activated") 7408833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7414626SN/A ; 7428833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7438833Sdam.sunwoo@arm.com mshr_cap_events.subname(i, system->getMasterName(i)); 7448833Sdam.sunwoo@arm.com } 7454626SN/A 7464626SN/A //software prefetching stats 7474626SN/A soft_prefetch_mshr_full 7488833Sdam.sunwoo@arm.com .init(system->maxMasters()) 7494626SN/A .name(name() + ".soft_prefetch_mshr_full") 7504626SN/A .desc("number of mshr full events for SW prefetching instrutions") 7518833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7524626SN/A ; 7538833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7548833Sdam.sunwoo@arm.com soft_prefetch_mshr_full.subname(i, system->getMasterName(i)); 7558833Sdam.sunwoo@arm.com } 7564626SN/A 7574626SN/A mshr_no_allocate_misses 7584626SN/A .name(name() +".no_allocate_misses") 7594626SN/A .desc("Number of misses that were no-allocate") 7604626SN/A ; 7614626SN/A 7622810SN/A} 7633503SN/A 7643503SN/Aunsigned int 7659342SAndreas.Sandberg@arm.comBaseCache::drain(DrainManager *dm) 7663503SN/A{ 7679347SAndreas.Sandberg@arm.com int count = memSidePort->drain(dm) + cpuSidePort->drain(dm) + 7689347SAndreas.Sandberg@arm.com mshrQueue.drain(dm) + writeBuffer.drain(dm); 7694626SN/A 7703503SN/A // Set status 7714626SN/A if (count != 0) { 7729342SAndreas.Sandberg@arm.com setDrainState(Drainable::Draining); 7739152Satgutier@umich.edu DPRINTF(Drain, "Cache not drained\n"); 7744626SN/A return count; 7753503SN/A } 7763503SN/A 7779342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 7783503SN/A return 0; 7793503SN/A} 7809795Sandreas.hansson@arm.com 7819795Sandreas.hansson@arm.comBaseCache * 7829795Sandreas.hansson@arm.comBaseCacheParams::create() 7839795Sandreas.hansson@arm.com{ 7849814Sandreas.hansson@arm.com unsigned numSets = size / (assoc * system->cacheLineSize()); 7859795Sandreas.hansson@arm.com 7869796Sprakash.ramrakhyani@arm.com assert(tags); 7879796Sprakash.ramrakhyani@arm.com 7889796Sprakash.ramrakhyani@arm.com if (dynamic_cast<FALRU*>(tags)) { 7899796Sprakash.ramrakhyani@arm.com if (numSets != 1) 7909796Sprakash.ramrakhyani@arm.com fatal("Got FALRU tags with more than one set\n"); 7919796Sprakash.ramrakhyani@arm.com return new Cache<FALRU>(this); 7929796Sprakash.ramrakhyani@arm.com } else if (dynamic_cast<LRU*>(tags)) { 7939796Sprakash.ramrakhyani@arm.com if (numSets == 1) 7949796Sprakash.ramrakhyani@arm.com warn("Consider using FALRU tags for a fully associative cache\n"); 7959796Sprakash.ramrakhyani@arm.com return new Cache<LRU>(this); 79610263Satgutier@umich.edu } else if (dynamic_cast<RandomRepl*>(tags)) { 79710263Satgutier@umich.edu return new Cache<RandomRepl>(this); 7989795Sandreas.hansson@arm.com } else { 7999796Sprakash.ramrakhyani@arm.com fatal("No suitable tags selected\n"); 8009795Sandreas.hansson@arm.com } 8019795Sandreas.hansson@arm.com} 802