base.cc revision 10344
12810SN/A/* 29614Srene.dejong@arm.com * Copyright (c) 2012-2013 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 412810SN/A */ 422810SN/A 432810SN/A/** 442810SN/A * @file 452810SN/A * Definition of BaseCache functions. 462810SN/A */ 472810SN/A 488232Snate@binkert.org#include "debug/Cache.hh" 499152Satgutier@umich.edu#include "debug/Drain.hh" 509795Sandreas.hansson@arm.com#include "mem/cache/tags/fa_lru.hh" 519795Sandreas.hansson@arm.com#include "mem/cache/tags/lru.hh" 5210263Satgutier@umich.edu#include "mem/cache/tags/random_repl.hh" 535338Sstever@gmail.com#include "mem/cache/base.hh" 549795Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 555338Sstever@gmail.com#include "mem/cache/mshr.hh" 568786Sgblack@eecs.umich.edu#include "sim/full_system.hh" 572810SN/A 582810SN/Ausing namespace std; 592810SN/A 608856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 618856Sandreas.hansson@arm.com BaseCache *_cache, 628856Sandreas.hansson@arm.com const std::string &_label) 638922Swilliam.wang@arm.com : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 648914Sandreas.hansson@arm.com blocked(false), mustSendRetry(false), sendRetryEvent(this) 658856Sandreas.hansson@arm.com{ 668856Sandreas.hansson@arm.com} 674475SN/A 685034SN/ABaseCache::BaseCache(const Params *p) 695034SN/A : MemObject(p), 705314SN/A mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs), 715314SN/A writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 724628SN/A MSHRQueue_WriteBuffer), 739814Sandreas.hansson@arm.com blkSize(p->system->cacheLineSize()), 749263Smrinmoy.ghosh@arm.com hitLatency(p->hit_latency), 759263Smrinmoy.ghosh@arm.com responseLatency(p->response_latency), 765034SN/A numTarget(p->tgts_per_mshr), 776122SSteve.Reinhardt@amd.com forwardSnoops(p->forward_snoops), 788134SAli.Saidi@ARM.com isTopLevel(p->is_top_level), 794626SN/A blocked(0), 804626SN/A noTargetMSHR(NULL), 815034SN/A missCount(p->max_miss_count), 828883SAli.Saidi@ARM.com addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 838833Sdam.sunwoo@arm.com system(p->system) 844458SN/A{ 852810SN/A} 862810SN/A 873013SN/Avoid 888856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::setBlocked() 892810SN/A{ 903013SN/A assert(!blocked); 918856Sandreas.hansson@arm.com DPRINTF(CachePort, "Cache port %s blocking new requests\n", name()); 922810SN/A blocked = true; 939614Srene.dejong@arm.com // if we already scheduled a retry in this cycle, but it has not yet 949614Srene.dejong@arm.com // happened, cancel it 959614Srene.dejong@arm.com if (sendRetryEvent.scheduled()) { 969614Srene.dejong@arm.com owner.deschedule(sendRetryEvent); 979614Srene.dejong@arm.com DPRINTF(CachePort, "Cache port %s deschedule retry\n", name()); 989614Srene.dejong@arm.com mustSendRetry = true; 999614Srene.dejong@arm.com } 1002810SN/A} 1012810SN/A 1022810SN/Avoid 1038856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::clearBlocked() 1042810SN/A{ 1053013SN/A assert(blocked); 1068856Sandreas.hansson@arm.com DPRINTF(CachePort, "Cache port %s accepting new requests\n", name()); 1073013SN/A blocked = false; 1088856Sandreas.hansson@arm.com if (mustSendRetry) { 1094666SN/A // @TODO: need to find a better time (next bus cycle?) 1108922Swilliam.wang@arm.com owner.schedule(sendRetryEvent, curTick() + 1); 1112897SN/A } 1122810SN/A} 1132810SN/A 11410344Sandreas.hansson@arm.comvoid 11510344Sandreas.hansson@arm.comBaseCache::CacheSlavePort::processSendRetry() 11610344Sandreas.hansson@arm.com{ 11710344Sandreas.hansson@arm.com DPRINTF(CachePort, "Cache port %s sending retry\n", name()); 11810344Sandreas.hansson@arm.com 11910344Sandreas.hansson@arm.com // reset the flag and call retry 12010344Sandreas.hansson@arm.com mustSendRetry = false; 12110344Sandreas.hansson@arm.com sendRetry(); 12210344Sandreas.hansson@arm.com} 1232844SN/A 1242810SN/Avoid 1252858SN/ABaseCache::init() 1262858SN/A{ 1278856Sandreas.hansson@arm.com if (!cpuSidePort->isConnected() || !memSidePort->isConnected()) 1288922Swilliam.wang@arm.com fatal("Cache ports on %s are not connected\n", name()); 1298711Sandreas.hansson@arm.com cpuSidePort->sendRangeChange(); 1302858SN/A} 1312858SN/A 1329294Sandreas.hansson@arm.comBaseMasterPort & 1339294Sandreas.hansson@arm.comBaseCache::getMasterPort(const std::string &if_name, PortID idx) 1348922Swilliam.wang@arm.com{ 1358922Swilliam.wang@arm.com if (if_name == "mem_side") { 1368922Swilliam.wang@arm.com return *memSidePort; 1378922Swilliam.wang@arm.com } else { 1388922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1398922Swilliam.wang@arm.com } 1408922Swilliam.wang@arm.com} 1418922Swilliam.wang@arm.com 1429294Sandreas.hansson@arm.comBaseSlavePort & 1439294Sandreas.hansson@arm.comBaseCache::getSlavePort(const std::string &if_name, PortID idx) 1448922Swilliam.wang@arm.com{ 1458922Swilliam.wang@arm.com if (if_name == "cpu_side") { 1468922Swilliam.wang@arm.com return *cpuSidePort; 1478922Swilliam.wang@arm.com } else { 1488922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 1498922Swilliam.wang@arm.com } 1508922Swilliam.wang@arm.com} 1514628SN/A 1522858SN/Avoid 1532810SN/ABaseCache::regStats() 1542810SN/A{ 1552810SN/A using namespace Stats; 1562810SN/A 1572810SN/A // Hit statistics 1584022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1594022SN/A MemCmd cmd(access_idx); 1604022SN/A const string &cstr = cmd.toString(); 1612810SN/A 1622810SN/A hits[access_idx] 1638833Sdam.sunwoo@arm.com .init(system->maxMasters()) 1642810SN/A .name(name() + "." + cstr + "_hits") 1652810SN/A .desc("number of " + cstr + " hits") 1662810SN/A .flags(total | nozero | nonan) 1672810SN/A ; 1688833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1698833Sdam.sunwoo@arm.com hits[access_idx].subname(i, system->getMasterName(i)); 1708833Sdam.sunwoo@arm.com } 1712810SN/A } 1722810SN/A 1734871SN/A// These macros make it easier to sum the right subset of commands and 1744871SN/A// to change the subset of commands that are considered "demand" vs 1754871SN/A// "non-demand" 1764871SN/A#define SUM_DEMAND(s) \ 1774871SN/A (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::ReadExReq]) 1784871SN/A 1794871SN/A// should writebacks be included here? prior code was inconsistent... 1804871SN/A#define SUM_NON_DEMAND(s) \ 1814871SN/A (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 1824871SN/A 1832810SN/A demandHits 1842810SN/A .name(name() + ".demand_hits") 1852810SN/A .desc("number of demand (read+write) hits") 1868833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1872810SN/A ; 1884871SN/A demandHits = SUM_DEMAND(hits); 1898833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1908833Sdam.sunwoo@arm.com demandHits.subname(i, system->getMasterName(i)); 1918833Sdam.sunwoo@arm.com } 1922810SN/A 1932810SN/A overallHits 1942810SN/A .name(name() + ".overall_hits") 1952810SN/A .desc("number of overall hits") 1968833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1972810SN/A ; 1984871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 1998833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2008833Sdam.sunwoo@arm.com overallHits.subname(i, system->getMasterName(i)); 2018833Sdam.sunwoo@arm.com } 2022810SN/A 2032810SN/A // Miss statistics 2044022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2054022SN/A MemCmd cmd(access_idx); 2064022SN/A const string &cstr = cmd.toString(); 2072810SN/A 2082810SN/A misses[access_idx] 2098833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2102810SN/A .name(name() + "." + cstr + "_misses") 2112810SN/A .desc("number of " + cstr + " misses") 2122810SN/A .flags(total | nozero | nonan) 2132810SN/A ; 2148833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2158833Sdam.sunwoo@arm.com misses[access_idx].subname(i, system->getMasterName(i)); 2168833Sdam.sunwoo@arm.com } 2172810SN/A } 2182810SN/A 2192810SN/A demandMisses 2202810SN/A .name(name() + ".demand_misses") 2212810SN/A .desc("number of demand (read+write) misses") 2228833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2232810SN/A ; 2244871SN/A demandMisses = SUM_DEMAND(misses); 2258833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2268833Sdam.sunwoo@arm.com demandMisses.subname(i, system->getMasterName(i)); 2278833Sdam.sunwoo@arm.com } 2282810SN/A 2292810SN/A overallMisses 2302810SN/A .name(name() + ".overall_misses") 2312810SN/A .desc("number of overall misses") 2328833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2332810SN/A ; 2344871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 2358833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2368833Sdam.sunwoo@arm.com overallMisses.subname(i, system->getMasterName(i)); 2378833Sdam.sunwoo@arm.com } 2382810SN/A 2392810SN/A // Miss latency statistics 2404022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2414022SN/A MemCmd cmd(access_idx); 2424022SN/A const string &cstr = cmd.toString(); 2432810SN/A 2442810SN/A missLatency[access_idx] 2458833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2462810SN/A .name(name() + "." + cstr + "_miss_latency") 2472810SN/A .desc("number of " + cstr + " miss cycles") 2482810SN/A .flags(total | nozero | nonan) 2492810SN/A ; 2508833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2518833Sdam.sunwoo@arm.com missLatency[access_idx].subname(i, system->getMasterName(i)); 2528833Sdam.sunwoo@arm.com } 2532810SN/A } 2542810SN/A 2552810SN/A demandMissLatency 2562810SN/A .name(name() + ".demand_miss_latency") 2572810SN/A .desc("number of demand (read+write) miss cycles") 2588833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2592810SN/A ; 2604871SN/A demandMissLatency = SUM_DEMAND(missLatency); 2618833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2628833Sdam.sunwoo@arm.com demandMissLatency.subname(i, system->getMasterName(i)); 2638833Sdam.sunwoo@arm.com } 2642810SN/A 2652810SN/A overallMissLatency 2662810SN/A .name(name() + ".overall_miss_latency") 2672810SN/A .desc("number of overall miss cycles") 2688833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2692810SN/A ; 2704871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 2718833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2728833Sdam.sunwoo@arm.com overallMissLatency.subname(i, system->getMasterName(i)); 2738833Sdam.sunwoo@arm.com } 2742810SN/A 2752810SN/A // access formulas 2764022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2774022SN/A MemCmd cmd(access_idx); 2784022SN/A const string &cstr = cmd.toString(); 2792810SN/A 2802810SN/A accesses[access_idx] 2812810SN/A .name(name() + "." + cstr + "_accesses") 2822810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 2832810SN/A .flags(total | nozero | nonan) 2842810SN/A ; 2858833Sdam.sunwoo@arm.com accesses[access_idx] = hits[access_idx] + misses[access_idx]; 2862810SN/A 2878833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2888833Sdam.sunwoo@arm.com accesses[access_idx].subname(i, system->getMasterName(i)); 2898833Sdam.sunwoo@arm.com } 2902810SN/A } 2912810SN/A 2922810SN/A demandAccesses 2932810SN/A .name(name() + ".demand_accesses") 2942810SN/A .desc("number of demand (read+write) accesses") 2958833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2962810SN/A ; 2972810SN/A demandAccesses = demandHits + demandMisses; 2988833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2998833Sdam.sunwoo@arm.com demandAccesses.subname(i, system->getMasterName(i)); 3008833Sdam.sunwoo@arm.com } 3012810SN/A 3022810SN/A overallAccesses 3032810SN/A .name(name() + ".overall_accesses") 3042810SN/A .desc("number of overall (read+write) accesses") 3058833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3062810SN/A ; 3072810SN/A overallAccesses = overallHits + overallMisses; 3088833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3098833Sdam.sunwoo@arm.com overallAccesses.subname(i, system->getMasterName(i)); 3108833Sdam.sunwoo@arm.com } 3112810SN/A 3122810SN/A // miss rate formulas 3134022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3144022SN/A MemCmd cmd(access_idx); 3154022SN/A const string &cstr = cmd.toString(); 3162810SN/A 3172810SN/A missRate[access_idx] 3182810SN/A .name(name() + "." + cstr + "_miss_rate") 3192810SN/A .desc("miss rate for " + cstr + " accesses") 3202810SN/A .flags(total | nozero | nonan) 3212810SN/A ; 3228833Sdam.sunwoo@arm.com missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 3232810SN/A 3248833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3258833Sdam.sunwoo@arm.com missRate[access_idx].subname(i, system->getMasterName(i)); 3268833Sdam.sunwoo@arm.com } 3272810SN/A } 3282810SN/A 3292810SN/A demandMissRate 3302810SN/A .name(name() + ".demand_miss_rate") 3312810SN/A .desc("miss rate for demand accesses") 3328833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3332810SN/A ; 3342810SN/A demandMissRate = demandMisses / demandAccesses; 3358833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3368833Sdam.sunwoo@arm.com demandMissRate.subname(i, system->getMasterName(i)); 3378833Sdam.sunwoo@arm.com } 3382810SN/A 3392810SN/A overallMissRate 3402810SN/A .name(name() + ".overall_miss_rate") 3412810SN/A .desc("miss rate for overall accesses") 3428833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3432810SN/A ; 3442810SN/A overallMissRate = overallMisses / overallAccesses; 3458833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3468833Sdam.sunwoo@arm.com overallMissRate.subname(i, system->getMasterName(i)); 3478833Sdam.sunwoo@arm.com } 3482810SN/A 3492810SN/A // miss latency formulas 3504022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3514022SN/A MemCmd cmd(access_idx); 3524022SN/A const string &cstr = cmd.toString(); 3532810SN/A 3542810SN/A avgMissLatency[access_idx] 3552810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 3562810SN/A .desc("average " + cstr + " miss latency") 3572810SN/A .flags(total | nozero | nonan) 3582810SN/A ; 3592810SN/A avgMissLatency[access_idx] = 3602810SN/A missLatency[access_idx] / misses[access_idx]; 3618833Sdam.sunwoo@arm.com 3628833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3638833Sdam.sunwoo@arm.com avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 3648833Sdam.sunwoo@arm.com } 3652810SN/A } 3662810SN/A 3672810SN/A demandAvgMissLatency 3682810SN/A .name(name() + ".demand_avg_miss_latency") 3692810SN/A .desc("average overall miss latency") 3708833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3712810SN/A ; 3722810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 3738833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3748833Sdam.sunwoo@arm.com demandAvgMissLatency.subname(i, system->getMasterName(i)); 3758833Sdam.sunwoo@arm.com } 3762810SN/A 3772810SN/A overallAvgMissLatency 3782810SN/A .name(name() + ".overall_avg_miss_latency") 3792810SN/A .desc("average overall miss latency") 3808833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3812810SN/A ; 3822810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 3838833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3848833Sdam.sunwoo@arm.com overallAvgMissLatency.subname(i, system->getMasterName(i)); 3858833Sdam.sunwoo@arm.com } 3862810SN/A 3872810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 3882810SN/A blocked_cycles 3892810SN/A .name(name() + ".blocked_cycles") 3902810SN/A .desc("number of cycles access was blocked") 3912810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3922810SN/A .subname(Blocked_NoTargets, "no_targets") 3932810SN/A ; 3942810SN/A 3952810SN/A 3962810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 3972810SN/A blocked_causes 3982810SN/A .name(name() + ".blocked") 3992810SN/A .desc("number of cycles access was blocked") 4002810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4012810SN/A .subname(Blocked_NoTargets, "no_targets") 4022810SN/A ; 4032810SN/A 4042810SN/A avg_blocked 4052810SN/A .name(name() + ".avg_blocked_cycles") 4062810SN/A .desc("average number of cycles each access was blocked") 4072810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4082810SN/A .subname(Blocked_NoTargets, "no_targets") 4092810SN/A ; 4102810SN/A 4112810SN/A avg_blocked = blocked_cycles / blocked_causes; 4122810SN/A 4132810SN/A fastWrites 4142810SN/A .name(name() + ".fast_writes") 4152810SN/A .desc("number of fast writes performed") 4162810SN/A ; 4172810SN/A 4182810SN/A cacheCopies 4192810SN/A .name(name() + ".cache_copies") 4202810SN/A .desc("number of cache copies performed") 4212810SN/A ; 4222826SN/A 4234626SN/A writebacks 4248833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4254626SN/A .name(name() + ".writebacks") 4264626SN/A .desc("number of writebacks") 4278833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4284626SN/A ; 4298833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4308833Sdam.sunwoo@arm.com writebacks.subname(i, system->getMasterName(i)); 4318833Sdam.sunwoo@arm.com } 4324626SN/A 4334626SN/A // MSHR statistics 4344626SN/A // MSHR hit statistics 4354626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4364626SN/A MemCmd cmd(access_idx); 4374626SN/A const string &cstr = cmd.toString(); 4384626SN/A 4394626SN/A mshr_hits[access_idx] 4408833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4414626SN/A .name(name() + "." + cstr + "_mshr_hits") 4424626SN/A .desc("number of " + cstr + " MSHR hits") 4434626SN/A .flags(total | nozero | nonan) 4444626SN/A ; 4458833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4468833Sdam.sunwoo@arm.com mshr_hits[access_idx].subname(i, system->getMasterName(i)); 4478833Sdam.sunwoo@arm.com } 4484626SN/A } 4494626SN/A 4504626SN/A demandMshrHits 4514626SN/A .name(name() + ".demand_mshr_hits") 4524626SN/A .desc("number of demand (read+write) MSHR hits") 4538833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4544626SN/A ; 4554871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 4568833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4578833Sdam.sunwoo@arm.com demandMshrHits.subname(i, system->getMasterName(i)); 4588833Sdam.sunwoo@arm.com } 4594626SN/A 4604626SN/A overallMshrHits 4614626SN/A .name(name() + ".overall_mshr_hits") 4624626SN/A .desc("number of overall MSHR hits") 4638833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4644626SN/A ; 4654871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 4668833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4678833Sdam.sunwoo@arm.com overallMshrHits.subname(i, system->getMasterName(i)); 4688833Sdam.sunwoo@arm.com } 4694626SN/A 4704626SN/A // MSHR miss statistics 4714626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4724626SN/A MemCmd cmd(access_idx); 4734626SN/A const string &cstr = cmd.toString(); 4744626SN/A 4754626SN/A mshr_misses[access_idx] 4768833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4774626SN/A .name(name() + "." + cstr + "_mshr_misses") 4784626SN/A .desc("number of " + cstr + " MSHR misses") 4794626SN/A .flags(total | nozero | nonan) 4804626SN/A ; 4818833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4828833Sdam.sunwoo@arm.com mshr_misses[access_idx].subname(i, system->getMasterName(i)); 4838833Sdam.sunwoo@arm.com } 4844626SN/A } 4854626SN/A 4864626SN/A demandMshrMisses 4874626SN/A .name(name() + ".demand_mshr_misses") 4884626SN/A .desc("number of demand (read+write) MSHR misses") 4898833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4904626SN/A ; 4914871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 4928833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4938833Sdam.sunwoo@arm.com demandMshrMisses.subname(i, system->getMasterName(i)); 4948833Sdam.sunwoo@arm.com } 4954626SN/A 4964626SN/A overallMshrMisses 4974626SN/A .name(name() + ".overall_mshr_misses") 4984626SN/A .desc("number of overall MSHR misses") 4998833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5004626SN/A ; 5014871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 5028833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5038833Sdam.sunwoo@arm.com overallMshrMisses.subname(i, system->getMasterName(i)); 5048833Sdam.sunwoo@arm.com } 5054626SN/A 5064626SN/A // MSHR miss latency statistics 5074626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5084626SN/A MemCmd cmd(access_idx); 5094626SN/A const string &cstr = cmd.toString(); 5104626SN/A 5114626SN/A mshr_miss_latency[access_idx] 5128833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5134626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 5144626SN/A .desc("number of " + cstr + " MSHR miss cycles") 5154626SN/A .flags(total | nozero | nonan) 5164626SN/A ; 5178833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5188833Sdam.sunwoo@arm.com mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 5198833Sdam.sunwoo@arm.com } 5204626SN/A } 5214626SN/A 5224626SN/A demandMshrMissLatency 5234626SN/A .name(name() + ".demand_mshr_miss_latency") 5244626SN/A .desc("number of demand (read+write) MSHR miss cycles") 5258833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5264626SN/A ; 5274871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 5288833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5298833Sdam.sunwoo@arm.com demandMshrMissLatency.subname(i, system->getMasterName(i)); 5308833Sdam.sunwoo@arm.com } 5314626SN/A 5324626SN/A overallMshrMissLatency 5334626SN/A .name(name() + ".overall_mshr_miss_latency") 5344626SN/A .desc("number of overall MSHR miss cycles") 5358833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5364626SN/A ; 5374871SN/A overallMshrMissLatency = 5384871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 5398833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5408833Sdam.sunwoo@arm.com overallMshrMissLatency.subname(i, system->getMasterName(i)); 5418833Sdam.sunwoo@arm.com } 5424626SN/A 5434626SN/A // MSHR uncacheable statistics 5444626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5454626SN/A MemCmd cmd(access_idx); 5464626SN/A const string &cstr = cmd.toString(); 5474626SN/A 5484626SN/A mshr_uncacheable[access_idx] 5498833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5504626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 5514626SN/A .desc("number of " + cstr + " MSHR uncacheable") 5524626SN/A .flags(total | nozero | nonan) 5534626SN/A ; 5548833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5558833Sdam.sunwoo@arm.com mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 5568833Sdam.sunwoo@arm.com } 5574626SN/A } 5584626SN/A 5594626SN/A overallMshrUncacheable 5604626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 5614626SN/A .desc("number of overall MSHR uncacheable misses") 5628833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5634626SN/A ; 5644871SN/A overallMshrUncacheable = 5654871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 5668833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5678833Sdam.sunwoo@arm.com overallMshrUncacheable.subname(i, system->getMasterName(i)); 5688833Sdam.sunwoo@arm.com } 5694626SN/A 5704626SN/A // MSHR miss latency statistics 5714626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5724626SN/A MemCmd cmd(access_idx); 5734626SN/A const string &cstr = cmd.toString(); 5744626SN/A 5754626SN/A mshr_uncacheable_lat[access_idx] 5768833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5774626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 5784626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 5794626SN/A .flags(total | nozero | nonan) 5804626SN/A ; 5818833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5828833Sdam.sunwoo@arm.com mshr_uncacheable_lat[access_idx].subname(i, system->getMasterName(i)); 5838833Sdam.sunwoo@arm.com } 5844626SN/A } 5854626SN/A 5864626SN/A overallMshrUncacheableLatency 5874626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 5884626SN/A .desc("number of overall MSHR uncacheable cycles") 5898833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5904626SN/A ; 5914871SN/A overallMshrUncacheableLatency = 5924871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 5934871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 5948833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5958833Sdam.sunwoo@arm.com overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 5968833Sdam.sunwoo@arm.com } 5974626SN/A 5984626SN/A#if 0 5994626SN/A // MSHR access formulas 6004626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6014626SN/A MemCmd cmd(access_idx); 6024626SN/A const string &cstr = cmd.toString(); 6034626SN/A 6044626SN/A mshrAccesses[access_idx] 6054626SN/A .name(name() + "." + cstr + "_mshr_accesses") 6064626SN/A .desc("number of " + cstr + " mshr accesses(hits+misses)") 6074626SN/A .flags(total | nozero | nonan) 6084626SN/A ; 6094626SN/A mshrAccesses[access_idx] = 6104626SN/A mshr_hits[access_idx] + mshr_misses[access_idx] 6114626SN/A + mshr_uncacheable[access_idx]; 6124626SN/A } 6134626SN/A 6144626SN/A demandMshrAccesses 6154626SN/A .name(name() + ".demand_mshr_accesses") 6164626SN/A .desc("number of demand (read+write) mshr accesses") 6174626SN/A .flags(total | nozero | nonan) 6184626SN/A ; 6194626SN/A demandMshrAccesses = demandMshrHits + demandMshrMisses; 6204626SN/A 6214626SN/A overallMshrAccesses 6224626SN/A .name(name() + ".overall_mshr_accesses") 6234626SN/A .desc("number of overall (read+write) mshr accesses") 6244626SN/A .flags(total | nozero | nonan) 6254626SN/A ; 6264626SN/A overallMshrAccesses = overallMshrHits + overallMshrMisses 6274626SN/A + overallMshrUncacheable; 6284626SN/A#endif 6294626SN/A 6304626SN/A // MSHR miss rate formulas 6314626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6324626SN/A MemCmd cmd(access_idx); 6334626SN/A const string &cstr = cmd.toString(); 6344626SN/A 6354626SN/A mshrMissRate[access_idx] 6364626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 6374626SN/A .desc("mshr miss rate for " + cstr + " accesses") 6384626SN/A .flags(total | nozero | nonan) 6394626SN/A ; 6404626SN/A mshrMissRate[access_idx] = 6414626SN/A mshr_misses[access_idx] / accesses[access_idx]; 6428833Sdam.sunwoo@arm.com 6438833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6448833Sdam.sunwoo@arm.com mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 6458833Sdam.sunwoo@arm.com } 6464626SN/A } 6474626SN/A 6484626SN/A demandMshrMissRate 6494626SN/A .name(name() + ".demand_mshr_miss_rate") 6504626SN/A .desc("mshr miss rate for demand accesses") 6518833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6524626SN/A ; 6534626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 6548833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6558833Sdam.sunwoo@arm.com demandMshrMissRate.subname(i, system->getMasterName(i)); 6568833Sdam.sunwoo@arm.com } 6574626SN/A 6584626SN/A overallMshrMissRate 6594626SN/A .name(name() + ".overall_mshr_miss_rate") 6604626SN/A .desc("mshr miss rate for overall accesses") 6618833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6624626SN/A ; 6634626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 6648833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6658833Sdam.sunwoo@arm.com overallMshrMissRate.subname(i, system->getMasterName(i)); 6668833Sdam.sunwoo@arm.com } 6674626SN/A 6684626SN/A // mshrMiss latency formulas 6694626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6704626SN/A MemCmd cmd(access_idx); 6714626SN/A const string &cstr = cmd.toString(); 6724626SN/A 6734626SN/A avgMshrMissLatency[access_idx] 6744626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 6754626SN/A .desc("average " + cstr + " mshr miss latency") 6764626SN/A .flags(total | nozero | nonan) 6774626SN/A ; 6784626SN/A avgMshrMissLatency[access_idx] = 6794626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 6808833Sdam.sunwoo@arm.com 6818833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6828833Sdam.sunwoo@arm.com avgMshrMissLatency[access_idx].subname(i, system->getMasterName(i)); 6838833Sdam.sunwoo@arm.com } 6844626SN/A } 6854626SN/A 6864626SN/A demandAvgMshrMissLatency 6874626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 6884626SN/A .desc("average overall mshr miss latency") 6898833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6904626SN/A ; 6914626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 6928833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6938833Sdam.sunwoo@arm.com demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 6948833Sdam.sunwoo@arm.com } 6954626SN/A 6964626SN/A overallAvgMshrMissLatency 6974626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 6984626SN/A .desc("average overall mshr miss latency") 6998833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7004626SN/A ; 7014626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 7028833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7038833Sdam.sunwoo@arm.com overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 7048833Sdam.sunwoo@arm.com } 7054626SN/A 7064626SN/A // mshrUncacheable latency formulas 7074626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 7084626SN/A MemCmd cmd(access_idx); 7094626SN/A const string &cstr = cmd.toString(); 7104626SN/A 7114626SN/A avgMshrUncacheableLatency[access_idx] 7124626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 7134626SN/A .desc("average " + cstr + " mshr uncacheable latency") 7144626SN/A .flags(total | nozero | nonan) 7154626SN/A ; 7164626SN/A avgMshrUncacheableLatency[access_idx] = 7174626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 7188833Sdam.sunwoo@arm.com 7198833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7208833Sdam.sunwoo@arm.com avgMshrUncacheableLatency[access_idx].subname(i, system->getMasterName(i)); 7218833Sdam.sunwoo@arm.com } 7224626SN/A } 7234626SN/A 7244626SN/A overallAvgMshrUncacheableLatency 7254626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 7264626SN/A .desc("average overall mshr uncacheable latency") 7278833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7284626SN/A ; 7294626SN/A overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable; 7308833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7318833Sdam.sunwoo@arm.com overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 7328833Sdam.sunwoo@arm.com } 7334626SN/A 7344626SN/A mshr_cap_events 7358833Sdam.sunwoo@arm.com .init(system->maxMasters()) 7364626SN/A .name(name() + ".mshr_cap_events") 7374626SN/A .desc("number of times MSHR cap was activated") 7388833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7394626SN/A ; 7408833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7418833Sdam.sunwoo@arm.com mshr_cap_events.subname(i, system->getMasterName(i)); 7428833Sdam.sunwoo@arm.com } 7434626SN/A 7444626SN/A //software prefetching stats 7454626SN/A soft_prefetch_mshr_full 7468833Sdam.sunwoo@arm.com .init(system->maxMasters()) 7474626SN/A .name(name() + ".soft_prefetch_mshr_full") 7484626SN/A .desc("number of mshr full events for SW prefetching instrutions") 7498833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7504626SN/A ; 7518833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7528833Sdam.sunwoo@arm.com soft_prefetch_mshr_full.subname(i, system->getMasterName(i)); 7538833Sdam.sunwoo@arm.com } 7544626SN/A 7554626SN/A mshr_no_allocate_misses 7564626SN/A .name(name() +".no_allocate_misses") 7574626SN/A .desc("Number of misses that were no-allocate") 7584626SN/A ; 7594626SN/A 7602810SN/A} 7613503SN/A 7623503SN/Aunsigned int 7639342SAndreas.Sandberg@arm.comBaseCache::drain(DrainManager *dm) 7643503SN/A{ 7659347SAndreas.Sandberg@arm.com int count = memSidePort->drain(dm) + cpuSidePort->drain(dm) + 7669347SAndreas.Sandberg@arm.com mshrQueue.drain(dm) + writeBuffer.drain(dm); 7674626SN/A 7683503SN/A // Set status 7694626SN/A if (count != 0) { 7709342SAndreas.Sandberg@arm.com setDrainState(Drainable::Draining); 7719152Satgutier@umich.edu DPRINTF(Drain, "Cache not drained\n"); 7724626SN/A return count; 7733503SN/A } 7743503SN/A 7759342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 7763503SN/A return 0; 7773503SN/A} 7789795Sandreas.hansson@arm.com 7799795Sandreas.hansson@arm.comBaseCache * 7809795Sandreas.hansson@arm.comBaseCacheParams::create() 7819795Sandreas.hansson@arm.com{ 7829814Sandreas.hansson@arm.com unsigned numSets = size / (assoc * system->cacheLineSize()); 7839795Sandreas.hansson@arm.com 7849796Sprakash.ramrakhyani@arm.com assert(tags); 7859796Sprakash.ramrakhyani@arm.com 7869796Sprakash.ramrakhyani@arm.com if (dynamic_cast<FALRU*>(tags)) { 7879796Sprakash.ramrakhyani@arm.com if (numSets != 1) 7889796Sprakash.ramrakhyani@arm.com fatal("Got FALRU tags with more than one set\n"); 7899796Sprakash.ramrakhyani@arm.com return new Cache<FALRU>(this); 7909796Sprakash.ramrakhyani@arm.com } else if (dynamic_cast<LRU*>(tags)) { 7919796Sprakash.ramrakhyani@arm.com if (numSets == 1) 7929796Sprakash.ramrakhyani@arm.com warn("Consider using FALRU tags for a fully associative cache\n"); 7939796Sprakash.ramrakhyani@arm.com return new Cache<LRU>(this); 79410263Satgutier@umich.edu } else if (dynamic_cast<RandomRepl*>(tags)) { 79510263Satgutier@umich.edu return new Cache<RandomRepl>(this); 7969795Sandreas.hansson@arm.com } else { 7979796Sprakash.ramrakhyani@arm.com fatal("No suitable tags selected\n"); 7989795Sandreas.hansson@arm.com } 7999795Sandreas.hansson@arm.com} 800