base.cc revision 10263
12810SN/A/* 29614Srene.dejong@arm.com * Copyright (c) 2012-2013 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 412810SN/A */ 422810SN/A 432810SN/A/** 442810SN/A * @file 452810SN/A * Definition of BaseCache functions. 462810SN/A */ 472810SN/A 488232Snate@binkert.org#include "debug/Cache.hh" 499152Satgutier@umich.edu#include "debug/Drain.hh" 509795Sandreas.hansson@arm.com#include "mem/cache/tags/fa_lru.hh" 519795Sandreas.hansson@arm.com#include "mem/cache/tags/lru.hh" 5210263Satgutier@umich.edu#include "mem/cache/tags/random_repl.hh" 535338Sstever@gmail.com#include "mem/cache/base.hh" 549795Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 555338Sstever@gmail.com#include "mem/cache/mshr.hh" 568786Sgblack@eecs.umich.edu#include "sim/full_system.hh" 572810SN/A 582810SN/Ausing namespace std; 592810SN/A 608856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 618856Sandreas.hansson@arm.com BaseCache *_cache, 628856Sandreas.hansson@arm.com const std::string &_label) 638922Swilliam.wang@arm.com : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 648914Sandreas.hansson@arm.com blocked(false), mustSendRetry(false), sendRetryEvent(this) 658856Sandreas.hansson@arm.com{ 668856Sandreas.hansson@arm.com} 674475SN/A 685034SN/ABaseCache::BaseCache(const Params *p) 695034SN/A : MemObject(p), 705314SN/A mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs), 715314SN/A writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 724628SN/A MSHRQueue_WriteBuffer), 739814Sandreas.hansson@arm.com blkSize(p->system->cacheLineSize()), 749263Smrinmoy.ghosh@arm.com hitLatency(p->hit_latency), 759263Smrinmoy.ghosh@arm.com responseLatency(p->response_latency), 765034SN/A numTarget(p->tgts_per_mshr), 776122SSteve.Reinhardt@amd.com forwardSnoops(p->forward_snoops), 788134SAli.Saidi@ARM.com isTopLevel(p->is_top_level), 794626SN/A blocked(0), 804626SN/A noTargetMSHR(NULL), 815034SN/A missCount(p->max_miss_count), 828883SAli.Saidi@ARM.com addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 838833Sdam.sunwoo@arm.com system(p->system) 844458SN/A{ 852810SN/A} 862810SN/A 873013SN/Avoid 888856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::setBlocked() 892810SN/A{ 903013SN/A assert(!blocked); 918856Sandreas.hansson@arm.com DPRINTF(CachePort, "Cache port %s blocking new requests\n", name()); 922810SN/A blocked = true; 939614Srene.dejong@arm.com // if we already scheduled a retry in this cycle, but it has not yet 949614Srene.dejong@arm.com // happened, cancel it 959614Srene.dejong@arm.com if (sendRetryEvent.scheduled()) { 969614Srene.dejong@arm.com owner.deschedule(sendRetryEvent); 979614Srene.dejong@arm.com DPRINTF(CachePort, "Cache port %s deschedule retry\n", name()); 989614Srene.dejong@arm.com mustSendRetry = true; 999614Srene.dejong@arm.com } 1002810SN/A} 1012810SN/A 1022810SN/Avoid 1038856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::clearBlocked() 1042810SN/A{ 1053013SN/A assert(blocked); 1068856Sandreas.hansson@arm.com DPRINTF(CachePort, "Cache port %s accepting new requests\n", name()); 1073013SN/A blocked = false; 1088856Sandreas.hansson@arm.com if (mustSendRetry) { 1098856Sandreas.hansson@arm.com DPRINTF(CachePort, "Cache port %s sending retry\n", name()); 1102897SN/A mustSendRetry = false; 1114666SN/A // @TODO: need to find a better time (next bus cycle?) 1128922Swilliam.wang@arm.com owner.schedule(sendRetryEvent, curTick() + 1); 1132897SN/A } 1142810SN/A} 1152810SN/A 1162844SN/A 1172810SN/Avoid 1182858SN/ABaseCache::init() 1192858SN/A{ 1208856Sandreas.hansson@arm.com if (!cpuSidePort->isConnected() || !memSidePort->isConnected()) 1218922Swilliam.wang@arm.com fatal("Cache ports on %s are not connected\n", name()); 1228711Sandreas.hansson@arm.com cpuSidePort->sendRangeChange(); 1232858SN/A} 1242858SN/A 1259294Sandreas.hansson@arm.comBaseMasterPort & 1269294Sandreas.hansson@arm.comBaseCache::getMasterPort(const std::string &if_name, PortID idx) 1278922Swilliam.wang@arm.com{ 1288922Swilliam.wang@arm.com if (if_name == "mem_side") { 1298922Swilliam.wang@arm.com return *memSidePort; 1308922Swilliam.wang@arm.com } else { 1318922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1328922Swilliam.wang@arm.com } 1338922Swilliam.wang@arm.com} 1348922Swilliam.wang@arm.com 1359294Sandreas.hansson@arm.comBaseSlavePort & 1369294Sandreas.hansson@arm.comBaseCache::getSlavePort(const std::string &if_name, PortID idx) 1378922Swilliam.wang@arm.com{ 1388922Swilliam.wang@arm.com if (if_name == "cpu_side") { 1398922Swilliam.wang@arm.com return *cpuSidePort; 1408922Swilliam.wang@arm.com } else { 1418922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 1428922Swilliam.wang@arm.com } 1438922Swilliam.wang@arm.com} 1444628SN/A 1452858SN/Avoid 1462810SN/ABaseCache::regStats() 1472810SN/A{ 1482810SN/A using namespace Stats; 1492810SN/A 1502810SN/A // Hit statistics 1514022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1524022SN/A MemCmd cmd(access_idx); 1534022SN/A const string &cstr = cmd.toString(); 1542810SN/A 1552810SN/A hits[access_idx] 1568833Sdam.sunwoo@arm.com .init(system->maxMasters()) 1572810SN/A .name(name() + "." + cstr + "_hits") 1582810SN/A .desc("number of " + cstr + " hits") 1592810SN/A .flags(total | nozero | nonan) 1602810SN/A ; 1618833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1628833Sdam.sunwoo@arm.com hits[access_idx].subname(i, system->getMasterName(i)); 1638833Sdam.sunwoo@arm.com } 1642810SN/A } 1652810SN/A 1664871SN/A// These macros make it easier to sum the right subset of commands and 1674871SN/A// to change the subset of commands that are considered "demand" vs 1684871SN/A// "non-demand" 1694871SN/A#define SUM_DEMAND(s) \ 1704871SN/A (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::ReadExReq]) 1714871SN/A 1724871SN/A// should writebacks be included here? prior code was inconsistent... 1734871SN/A#define SUM_NON_DEMAND(s) \ 1744871SN/A (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 1754871SN/A 1762810SN/A demandHits 1772810SN/A .name(name() + ".demand_hits") 1782810SN/A .desc("number of demand (read+write) hits") 1798833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1802810SN/A ; 1814871SN/A demandHits = SUM_DEMAND(hits); 1828833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1838833Sdam.sunwoo@arm.com demandHits.subname(i, system->getMasterName(i)); 1848833Sdam.sunwoo@arm.com } 1852810SN/A 1862810SN/A overallHits 1872810SN/A .name(name() + ".overall_hits") 1882810SN/A .desc("number of overall hits") 1898833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1902810SN/A ; 1914871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 1928833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1938833Sdam.sunwoo@arm.com overallHits.subname(i, system->getMasterName(i)); 1948833Sdam.sunwoo@arm.com } 1952810SN/A 1962810SN/A // Miss statistics 1974022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1984022SN/A MemCmd cmd(access_idx); 1994022SN/A const string &cstr = cmd.toString(); 2002810SN/A 2012810SN/A misses[access_idx] 2028833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2032810SN/A .name(name() + "." + cstr + "_misses") 2042810SN/A .desc("number of " + cstr + " misses") 2052810SN/A .flags(total | nozero | nonan) 2062810SN/A ; 2078833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2088833Sdam.sunwoo@arm.com misses[access_idx].subname(i, system->getMasterName(i)); 2098833Sdam.sunwoo@arm.com } 2102810SN/A } 2112810SN/A 2122810SN/A demandMisses 2132810SN/A .name(name() + ".demand_misses") 2142810SN/A .desc("number of demand (read+write) misses") 2158833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2162810SN/A ; 2174871SN/A demandMisses = SUM_DEMAND(misses); 2188833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2198833Sdam.sunwoo@arm.com demandMisses.subname(i, system->getMasterName(i)); 2208833Sdam.sunwoo@arm.com } 2212810SN/A 2222810SN/A overallMisses 2232810SN/A .name(name() + ".overall_misses") 2242810SN/A .desc("number of overall misses") 2258833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2262810SN/A ; 2274871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 2288833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2298833Sdam.sunwoo@arm.com overallMisses.subname(i, system->getMasterName(i)); 2308833Sdam.sunwoo@arm.com } 2312810SN/A 2322810SN/A // Miss latency statistics 2334022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2344022SN/A MemCmd cmd(access_idx); 2354022SN/A const string &cstr = cmd.toString(); 2362810SN/A 2372810SN/A missLatency[access_idx] 2388833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2392810SN/A .name(name() + "." + cstr + "_miss_latency") 2402810SN/A .desc("number of " + cstr + " miss cycles") 2412810SN/A .flags(total | nozero | nonan) 2422810SN/A ; 2438833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2448833Sdam.sunwoo@arm.com missLatency[access_idx].subname(i, system->getMasterName(i)); 2458833Sdam.sunwoo@arm.com } 2462810SN/A } 2472810SN/A 2482810SN/A demandMissLatency 2492810SN/A .name(name() + ".demand_miss_latency") 2502810SN/A .desc("number of demand (read+write) miss cycles") 2518833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2522810SN/A ; 2534871SN/A demandMissLatency = SUM_DEMAND(missLatency); 2548833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2558833Sdam.sunwoo@arm.com demandMissLatency.subname(i, system->getMasterName(i)); 2568833Sdam.sunwoo@arm.com } 2572810SN/A 2582810SN/A overallMissLatency 2592810SN/A .name(name() + ".overall_miss_latency") 2602810SN/A .desc("number of overall miss cycles") 2618833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2622810SN/A ; 2634871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 2648833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2658833Sdam.sunwoo@arm.com overallMissLatency.subname(i, system->getMasterName(i)); 2668833Sdam.sunwoo@arm.com } 2672810SN/A 2682810SN/A // access formulas 2694022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2704022SN/A MemCmd cmd(access_idx); 2714022SN/A const string &cstr = cmd.toString(); 2722810SN/A 2732810SN/A accesses[access_idx] 2742810SN/A .name(name() + "." + cstr + "_accesses") 2752810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 2762810SN/A .flags(total | nozero | nonan) 2772810SN/A ; 2788833Sdam.sunwoo@arm.com accesses[access_idx] = hits[access_idx] + misses[access_idx]; 2792810SN/A 2808833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2818833Sdam.sunwoo@arm.com accesses[access_idx].subname(i, system->getMasterName(i)); 2828833Sdam.sunwoo@arm.com } 2832810SN/A } 2842810SN/A 2852810SN/A demandAccesses 2862810SN/A .name(name() + ".demand_accesses") 2872810SN/A .desc("number of demand (read+write) accesses") 2888833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2892810SN/A ; 2902810SN/A demandAccesses = demandHits + demandMisses; 2918833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2928833Sdam.sunwoo@arm.com demandAccesses.subname(i, system->getMasterName(i)); 2938833Sdam.sunwoo@arm.com } 2942810SN/A 2952810SN/A overallAccesses 2962810SN/A .name(name() + ".overall_accesses") 2972810SN/A .desc("number of overall (read+write) accesses") 2988833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2992810SN/A ; 3002810SN/A overallAccesses = overallHits + overallMisses; 3018833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3028833Sdam.sunwoo@arm.com overallAccesses.subname(i, system->getMasterName(i)); 3038833Sdam.sunwoo@arm.com } 3042810SN/A 3052810SN/A // miss rate formulas 3064022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3074022SN/A MemCmd cmd(access_idx); 3084022SN/A const string &cstr = cmd.toString(); 3092810SN/A 3102810SN/A missRate[access_idx] 3112810SN/A .name(name() + "." + cstr + "_miss_rate") 3122810SN/A .desc("miss rate for " + cstr + " accesses") 3132810SN/A .flags(total | nozero | nonan) 3142810SN/A ; 3158833Sdam.sunwoo@arm.com missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 3162810SN/A 3178833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3188833Sdam.sunwoo@arm.com missRate[access_idx].subname(i, system->getMasterName(i)); 3198833Sdam.sunwoo@arm.com } 3202810SN/A } 3212810SN/A 3222810SN/A demandMissRate 3232810SN/A .name(name() + ".demand_miss_rate") 3242810SN/A .desc("miss rate for demand accesses") 3258833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3262810SN/A ; 3272810SN/A demandMissRate = demandMisses / demandAccesses; 3288833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3298833Sdam.sunwoo@arm.com demandMissRate.subname(i, system->getMasterName(i)); 3308833Sdam.sunwoo@arm.com } 3312810SN/A 3322810SN/A overallMissRate 3332810SN/A .name(name() + ".overall_miss_rate") 3342810SN/A .desc("miss rate for overall accesses") 3358833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3362810SN/A ; 3372810SN/A overallMissRate = overallMisses / overallAccesses; 3388833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3398833Sdam.sunwoo@arm.com overallMissRate.subname(i, system->getMasterName(i)); 3408833Sdam.sunwoo@arm.com } 3412810SN/A 3422810SN/A // miss latency formulas 3434022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3444022SN/A MemCmd cmd(access_idx); 3454022SN/A const string &cstr = cmd.toString(); 3462810SN/A 3472810SN/A avgMissLatency[access_idx] 3482810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 3492810SN/A .desc("average " + cstr + " miss latency") 3502810SN/A .flags(total | nozero | nonan) 3512810SN/A ; 3522810SN/A avgMissLatency[access_idx] = 3532810SN/A missLatency[access_idx] / misses[access_idx]; 3548833Sdam.sunwoo@arm.com 3558833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3568833Sdam.sunwoo@arm.com avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 3578833Sdam.sunwoo@arm.com } 3582810SN/A } 3592810SN/A 3602810SN/A demandAvgMissLatency 3612810SN/A .name(name() + ".demand_avg_miss_latency") 3622810SN/A .desc("average overall miss latency") 3638833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3642810SN/A ; 3652810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 3668833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3678833Sdam.sunwoo@arm.com demandAvgMissLatency.subname(i, system->getMasterName(i)); 3688833Sdam.sunwoo@arm.com } 3692810SN/A 3702810SN/A overallAvgMissLatency 3712810SN/A .name(name() + ".overall_avg_miss_latency") 3722810SN/A .desc("average overall miss latency") 3738833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3742810SN/A ; 3752810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 3768833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3778833Sdam.sunwoo@arm.com overallAvgMissLatency.subname(i, system->getMasterName(i)); 3788833Sdam.sunwoo@arm.com } 3792810SN/A 3802810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 3812810SN/A blocked_cycles 3822810SN/A .name(name() + ".blocked_cycles") 3832810SN/A .desc("number of cycles access was blocked") 3842810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3852810SN/A .subname(Blocked_NoTargets, "no_targets") 3862810SN/A ; 3872810SN/A 3882810SN/A 3892810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 3902810SN/A blocked_causes 3912810SN/A .name(name() + ".blocked") 3922810SN/A .desc("number of cycles access was blocked") 3932810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3942810SN/A .subname(Blocked_NoTargets, "no_targets") 3952810SN/A ; 3962810SN/A 3972810SN/A avg_blocked 3982810SN/A .name(name() + ".avg_blocked_cycles") 3992810SN/A .desc("average number of cycles each access was blocked") 4002810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4012810SN/A .subname(Blocked_NoTargets, "no_targets") 4022810SN/A ; 4032810SN/A 4042810SN/A avg_blocked = blocked_cycles / blocked_causes; 4052810SN/A 4062810SN/A fastWrites 4072810SN/A .name(name() + ".fast_writes") 4082810SN/A .desc("number of fast writes performed") 4092810SN/A ; 4102810SN/A 4112810SN/A cacheCopies 4122810SN/A .name(name() + ".cache_copies") 4132810SN/A .desc("number of cache copies performed") 4142810SN/A ; 4152826SN/A 4164626SN/A writebacks 4178833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4184626SN/A .name(name() + ".writebacks") 4194626SN/A .desc("number of writebacks") 4208833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4214626SN/A ; 4228833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4238833Sdam.sunwoo@arm.com writebacks.subname(i, system->getMasterName(i)); 4248833Sdam.sunwoo@arm.com } 4254626SN/A 4264626SN/A // MSHR statistics 4274626SN/A // MSHR hit statistics 4284626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4294626SN/A MemCmd cmd(access_idx); 4304626SN/A const string &cstr = cmd.toString(); 4314626SN/A 4324626SN/A mshr_hits[access_idx] 4338833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4344626SN/A .name(name() + "." + cstr + "_mshr_hits") 4354626SN/A .desc("number of " + cstr + " MSHR hits") 4364626SN/A .flags(total | nozero | nonan) 4374626SN/A ; 4388833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4398833Sdam.sunwoo@arm.com mshr_hits[access_idx].subname(i, system->getMasterName(i)); 4408833Sdam.sunwoo@arm.com } 4414626SN/A } 4424626SN/A 4434626SN/A demandMshrHits 4444626SN/A .name(name() + ".demand_mshr_hits") 4454626SN/A .desc("number of demand (read+write) MSHR hits") 4468833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4474626SN/A ; 4484871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 4498833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4508833Sdam.sunwoo@arm.com demandMshrHits.subname(i, system->getMasterName(i)); 4518833Sdam.sunwoo@arm.com } 4524626SN/A 4534626SN/A overallMshrHits 4544626SN/A .name(name() + ".overall_mshr_hits") 4554626SN/A .desc("number of overall MSHR hits") 4568833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4574626SN/A ; 4584871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 4598833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4608833Sdam.sunwoo@arm.com overallMshrHits.subname(i, system->getMasterName(i)); 4618833Sdam.sunwoo@arm.com } 4624626SN/A 4634626SN/A // MSHR miss statistics 4644626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4654626SN/A MemCmd cmd(access_idx); 4664626SN/A const string &cstr = cmd.toString(); 4674626SN/A 4684626SN/A mshr_misses[access_idx] 4698833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4704626SN/A .name(name() + "." + cstr + "_mshr_misses") 4714626SN/A .desc("number of " + cstr + " MSHR misses") 4724626SN/A .flags(total | nozero | nonan) 4734626SN/A ; 4748833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4758833Sdam.sunwoo@arm.com mshr_misses[access_idx].subname(i, system->getMasterName(i)); 4768833Sdam.sunwoo@arm.com } 4774626SN/A } 4784626SN/A 4794626SN/A demandMshrMisses 4804626SN/A .name(name() + ".demand_mshr_misses") 4814626SN/A .desc("number of demand (read+write) MSHR misses") 4828833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4834626SN/A ; 4844871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 4858833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4868833Sdam.sunwoo@arm.com demandMshrMisses.subname(i, system->getMasterName(i)); 4878833Sdam.sunwoo@arm.com } 4884626SN/A 4894626SN/A overallMshrMisses 4904626SN/A .name(name() + ".overall_mshr_misses") 4914626SN/A .desc("number of overall MSHR misses") 4928833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4934626SN/A ; 4944871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 4958833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4968833Sdam.sunwoo@arm.com overallMshrMisses.subname(i, system->getMasterName(i)); 4978833Sdam.sunwoo@arm.com } 4984626SN/A 4994626SN/A // MSHR miss latency statistics 5004626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5014626SN/A MemCmd cmd(access_idx); 5024626SN/A const string &cstr = cmd.toString(); 5034626SN/A 5044626SN/A mshr_miss_latency[access_idx] 5058833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5064626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 5074626SN/A .desc("number of " + cstr + " MSHR miss cycles") 5084626SN/A .flags(total | nozero | nonan) 5094626SN/A ; 5108833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5118833Sdam.sunwoo@arm.com mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 5128833Sdam.sunwoo@arm.com } 5134626SN/A } 5144626SN/A 5154626SN/A demandMshrMissLatency 5164626SN/A .name(name() + ".demand_mshr_miss_latency") 5174626SN/A .desc("number of demand (read+write) MSHR miss cycles") 5188833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5194626SN/A ; 5204871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 5218833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5228833Sdam.sunwoo@arm.com demandMshrMissLatency.subname(i, system->getMasterName(i)); 5238833Sdam.sunwoo@arm.com } 5244626SN/A 5254626SN/A overallMshrMissLatency 5264626SN/A .name(name() + ".overall_mshr_miss_latency") 5274626SN/A .desc("number of overall MSHR miss cycles") 5288833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5294626SN/A ; 5304871SN/A overallMshrMissLatency = 5314871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 5328833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5338833Sdam.sunwoo@arm.com overallMshrMissLatency.subname(i, system->getMasterName(i)); 5348833Sdam.sunwoo@arm.com } 5354626SN/A 5364626SN/A // MSHR uncacheable statistics 5374626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5384626SN/A MemCmd cmd(access_idx); 5394626SN/A const string &cstr = cmd.toString(); 5404626SN/A 5414626SN/A mshr_uncacheable[access_idx] 5428833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5434626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 5444626SN/A .desc("number of " + cstr + " MSHR uncacheable") 5454626SN/A .flags(total | nozero | nonan) 5464626SN/A ; 5478833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5488833Sdam.sunwoo@arm.com mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 5498833Sdam.sunwoo@arm.com } 5504626SN/A } 5514626SN/A 5524626SN/A overallMshrUncacheable 5534626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 5544626SN/A .desc("number of overall MSHR uncacheable misses") 5558833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5564626SN/A ; 5574871SN/A overallMshrUncacheable = 5584871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 5598833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5608833Sdam.sunwoo@arm.com overallMshrUncacheable.subname(i, system->getMasterName(i)); 5618833Sdam.sunwoo@arm.com } 5624626SN/A 5634626SN/A // MSHR miss latency statistics 5644626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5654626SN/A MemCmd cmd(access_idx); 5664626SN/A const string &cstr = cmd.toString(); 5674626SN/A 5684626SN/A mshr_uncacheable_lat[access_idx] 5698833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5704626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 5714626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 5724626SN/A .flags(total | nozero | nonan) 5734626SN/A ; 5748833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5758833Sdam.sunwoo@arm.com mshr_uncacheable_lat[access_idx].subname(i, system->getMasterName(i)); 5768833Sdam.sunwoo@arm.com } 5774626SN/A } 5784626SN/A 5794626SN/A overallMshrUncacheableLatency 5804626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 5814626SN/A .desc("number of overall MSHR uncacheable cycles") 5828833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5834626SN/A ; 5844871SN/A overallMshrUncacheableLatency = 5854871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 5864871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 5878833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5888833Sdam.sunwoo@arm.com overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 5898833Sdam.sunwoo@arm.com } 5904626SN/A 5914626SN/A#if 0 5924626SN/A // MSHR access formulas 5934626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5944626SN/A MemCmd cmd(access_idx); 5954626SN/A const string &cstr = cmd.toString(); 5964626SN/A 5974626SN/A mshrAccesses[access_idx] 5984626SN/A .name(name() + "." + cstr + "_mshr_accesses") 5994626SN/A .desc("number of " + cstr + " mshr accesses(hits+misses)") 6004626SN/A .flags(total | nozero | nonan) 6014626SN/A ; 6024626SN/A mshrAccesses[access_idx] = 6034626SN/A mshr_hits[access_idx] + mshr_misses[access_idx] 6044626SN/A + mshr_uncacheable[access_idx]; 6054626SN/A } 6064626SN/A 6074626SN/A demandMshrAccesses 6084626SN/A .name(name() + ".demand_mshr_accesses") 6094626SN/A .desc("number of demand (read+write) mshr accesses") 6104626SN/A .flags(total | nozero | nonan) 6114626SN/A ; 6124626SN/A demandMshrAccesses = demandMshrHits + demandMshrMisses; 6134626SN/A 6144626SN/A overallMshrAccesses 6154626SN/A .name(name() + ".overall_mshr_accesses") 6164626SN/A .desc("number of overall (read+write) mshr accesses") 6174626SN/A .flags(total | nozero | nonan) 6184626SN/A ; 6194626SN/A overallMshrAccesses = overallMshrHits + overallMshrMisses 6204626SN/A + overallMshrUncacheable; 6214626SN/A#endif 6224626SN/A 6234626SN/A // MSHR miss rate formulas 6244626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6254626SN/A MemCmd cmd(access_idx); 6264626SN/A const string &cstr = cmd.toString(); 6274626SN/A 6284626SN/A mshrMissRate[access_idx] 6294626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 6304626SN/A .desc("mshr miss rate for " + cstr + " accesses") 6314626SN/A .flags(total | nozero | nonan) 6324626SN/A ; 6334626SN/A mshrMissRate[access_idx] = 6344626SN/A mshr_misses[access_idx] / accesses[access_idx]; 6358833Sdam.sunwoo@arm.com 6368833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6378833Sdam.sunwoo@arm.com mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 6388833Sdam.sunwoo@arm.com } 6394626SN/A } 6404626SN/A 6414626SN/A demandMshrMissRate 6424626SN/A .name(name() + ".demand_mshr_miss_rate") 6434626SN/A .desc("mshr miss rate for demand accesses") 6448833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6454626SN/A ; 6464626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 6478833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6488833Sdam.sunwoo@arm.com demandMshrMissRate.subname(i, system->getMasterName(i)); 6498833Sdam.sunwoo@arm.com } 6504626SN/A 6514626SN/A overallMshrMissRate 6524626SN/A .name(name() + ".overall_mshr_miss_rate") 6534626SN/A .desc("mshr miss rate for overall accesses") 6548833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6554626SN/A ; 6564626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 6578833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6588833Sdam.sunwoo@arm.com overallMshrMissRate.subname(i, system->getMasterName(i)); 6598833Sdam.sunwoo@arm.com } 6604626SN/A 6614626SN/A // mshrMiss latency formulas 6624626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6634626SN/A MemCmd cmd(access_idx); 6644626SN/A const string &cstr = cmd.toString(); 6654626SN/A 6664626SN/A avgMshrMissLatency[access_idx] 6674626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 6684626SN/A .desc("average " + cstr + " mshr miss latency") 6694626SN/A .flags(total | nozero | nonan) 6704626SN/A ; 6714626SN/A avgMshrMissLatency[access_idx] = 6724626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 6738833Sdam.sunwoo@arm.com 6748833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6758833Sdam.sunwoo@arm.com avgMshrMissLatency[access_idx].subname(i, system->getMasterName(i)); 6768833Sdam.sunwoo@arm.com } 6774626SN/A } 6784626SN/A 6794626SN/A demandAvgMshrMissLatency 6804626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 6814626SN/A .desc("average overall mshr miss latency") 6828833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6834626SN/A ; 6844626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 6858833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6868833Sdam.sunwoo@arm.com demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 6878833Sdam.sunwoo@arm.com } 6884626SN/A 6894626SN/A overallAvgMshrMissLatency 6904626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 6914626SN/A .desc("average overall mshr miss latency") 6928833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6934626SN/A ; 6944626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 6958833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6968833Sdam.sunwoo@arm.com overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 6978833Sdam.sunwoo@arm.com } 6984626SN/A 6994626SN/A // mshrUncacheable latency formulas 7004626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 7014626SN/A MemCmd cmd(access_idx); 7024626SN/A const string &cstr = cmd.toString(); 7034626SN/A 7044626SN/A avgMshrUncacheableLatency[access_idx] 7054626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 7064626SN/A .desc("average " + cstr + " mshr uncacheable latency") 7074626SN/A .flags(total | nozero | nonan) 7084626SN/A ; 7094626SN/A avgMshrUncacheableLatency[access_idx] = 7104626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 7118833Sdam.sunwoo@arm.com 7128833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7138833Sdam.sunwoo@arm.com avgMshrUncacheableLatency[access_idx].subname(i, system->getMasterName(i)); 7148833Sdam.sunwoo@arm.com } 7154626SN/A } 7164626SN/A 7174626SN/A overallAvgMshrUncacheableLatency 7184626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 7194626SN/A .desc("average overall mshr uncacheable latency") 7208833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7214626SN/A ; 7224626SN/A overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable; 7238833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7248833Sdam.sunwoo@arm.com overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 7258833Sdam.sunwoo@arm.com } 7264626SN/A 7274626SN/A mshr_cap_events 7288833Sdam.sunwoo@arm.com .init(system->maxMasters()) 7294626SN/A .name(name() + ".mshr_cap_events") 7304626SN/A .desc("number of times MSHR cap was activated") 7318833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7324626SN/A ; 7338833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7348833Sdam.sunwoo@arm.com mshr_cap_events.subname(i, system->getMasterName(i)); 7358833Sdam.sunwoo@arm.com } 7364626SN/A 7374626SN/A //software prefetching stats 7384626SN/A soft_prefetch_mshr_full 7398833Sdam.sunwoo@arm.com .init(system->maxMasters()) 7404626SN/A .name(name() + ".soft_prefetch_mshr_full") 7414626SN/A .desc("number of mshr full events for SW prefetching instrutions") 7428833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7434626SN/A ; 7448833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7458833Sdam.sunwoo@arm.com soft_prefetch_mshr_full.subname(i, system->getMasterName(i)); 7468833Sdam.sunwoo@arm.com } 7474626SN/A 7484626SN/A mshr_no_allocate_misses 7494626SN/A .name(name() +".no_allocate_misses") 7504626SN/A .desc("Number of misses that were no-allocate") 7514626SN/A ; 7524626SN/A 7532810SN/A} 7543503SN/A 7553503SN/Aunsigned int 7569342SAndreas.Sandberg@arm.comBaseCache::drain(DrainManager *dm) 7573503SN/A{ 7589347SAndreas.Sandberg@arm.com int count = memSidePort->drain(dm) + cpuSidePort->drain(dm) + 7599347SAndreas.Sandberg@arm.com mshrQueue.drain(dm) + writeBuffer.drain(dm); 7604626SN/A 7613503SN/A // Set status 7624626SN/A if (count != 0) { 7639342SAndreas.Sandberg@arm.com setDrainState(Drainable::Draining); 7649152Satgutier@umich.edu DPRINTF(Drain, "Cache not drained\n"); 7654626SN/A return count; 7663503SN/A } 7673503SN/A 7689342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 7693503SN/A return 0; 7703503SN/A} 7719795Sandreas.hansson@arm.com 7729795Sandreas.hansson@arm.comBaseCache * 7739795Sandreas.hansson@arm.comBaseCacheParams::create() 7749795Sandreas.hansson@arm.com{ 7759814Sandreas.hansson@arm.com unsigned numSets = size / (assoc * system->cacheLineSize()); 7769795Sandreas.hansson@arm.com 7779796Sprakash.ramrakhyani@arm.com assert(tags); 7789796Sprakash.ramrakhyani@arm.com 7799796Sprakash.ramrakhyani@arm.com if (dynamic_cast<FALRU*>(tags)) { 7809796Sprakash.ramrakhyani@arm.com if (numSets != 1) 7819796Sprakash.ramrakhyani@arm.com fatal("Got FALRU tags with more than one set\n"); 7829796Sprakash.ramrakhyani@arm.com return new Cache<FALRU>(this); 7839796Sprakash.ramrakhyani@arm.com } else if (dynamic_cast<LRU*>(tags)) { 7849796Sprakash.ramrakhyani@arm.com if (numSets == 1) 7859796Sprakash.ramrakhyani@arm.com warn("Consider using FALRU tags for a fully associative cache\n"); 7869796Sprakash.ramrakhyani@arm.com return new Cache<LRU>(this); 78710263Satgutier@umich.edu } else if (dynamic_cast<RandomRepl*>(tags)) { 78810263Satgutier@umich.edu return new Cache<RandomRepl>(this); 7899795Sandreas.hansson@arm.com } else { 7909796Sprakash.ramrakhyani@arm.com fatal("No suitable tags selected\n"); 7919795Sandreas.hansson@arm.com } 7929795Sandreas.hansson@arm.com} 793