Cache.py revision 12513:4dfc54394b5a 
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39# Authors: Nathan Binkert
40#          Andreas Hansson
41
42from m5.params import *
43from m5.proxy import *
44from MemObject import MemObject
45from Prefetcher import BasePrefetcher
46from Tags import *
47
48class BaseCache(MemObject):
49    type = 'BaseCache'
50    abstract = True
51    cxx_header = "mem/cache/base.hh"
52
53    size = Param.MemorySize("Capacity")
54    assoc = Param.Unsigned("Associativity")
55
56    tag_latency = Param.Cycles("Tag lookup latency")
57    data_latency = Param.Cycles("Data access latency")
58    response_latency = Param.Cycles("Latency for the return path on a miss");
59
60    warmup_percentage = Param.Percent(0,
61        "Percentage of tags to be touched to warm up the cache")
62
63    max_miss_count = Param.Counter(0,
64        "Number of misses to handle before calling exit")
65
66    mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)")
67    demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access")
68    tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR")
69    write_buffers = Param.Unsigned(8, "Number of write buffers")
70
71    is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)")
72
73    prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
74    prefetch_on_access = Param.Bool(False,
75         "Notify the hardware prefetcher on every access (not just misses)")
76
77    tags = Param.BaseTags(LRU(), "Tag store (replacement policy)")
78    sequential_access = Param.Bool(False,
79        "Whether to access tags and data sequentially")
80
81    cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
82    mem_side = MasterPort("Downstream port closer to memory")
83
84    addr_ranges = VectorParam.AddrRange([AllMemory],
85         "Address range for the CPU-side port (to allow striping)")
86
87    system = Param.System(Parent.any, "System we belong to")
88
89# Enum for cache clusivity, currently mostly inclusive or mostly
90# exclusive.
91class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl']
92
93class Cache(BaseCache):
94    type = 'Cache'
95    cxx_header = 'mem/cache/cache.hh'
96
97    # Control whether this cache should be mostly inclusive or mostly
98    # exclusive with respect to upstream caches. The behaviour on a
99    # fill is determined accordingly. For a mostly inclusive cache,
100    # blocks are allocated on all fill operations. Thus, L1 caches
101    # should be set as mostly inclusive even if they have no upstream
102    # caches. In the case of a mostly exclusive cache, fills are not
103    # allocating unless they came directly from a non-caching source,
104    # e.g. a table walker. Additionally, on a hit from an upstream
105    # cache a line is dropped for a mostly exclusive cache.
106    clusivity = Param.Clusivity('mostly_incl',
107                                "Clusivity with upstream cache")
108
109    # Determine if this cache sends out writebacks for clean lines, or
110    # simply clean evicts. In cases where a downstream cache is mostly
111    # exclusive with respect to this cache (acting as a victim cache),
112    # the clean writebacks are essential for performance. In general
113    # this should be set to True for anything but the last-level
114    # cache.
115    writeback_clean = Param.Bool(False, "Writeback clean lines")
116