Cache.py revision 9288 
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39# Authors: Nathan Binkert
40
41from m5.params import *
42from m5.proxy import *
43from MemObject import MemObject
44from Prefetcher import BasePrefetcher
45
46
47class BaseCache(MemObject):
48    type = 'BaseCache'
49    assoc = Param.Int("associativity")
50    block_size = Param.Int("block size in bytes")
51    hit_latency = Param.Cycles("The hit latency for this cache")
52    response_latency = Param.Cycles(
53            "Additional cache latency for the return path to core on a miss");
54    hash_delay = Param.Cycles(1, "time in cycles of hash access")
55    max_miss_count = Param.Counter(0,
56        "number of misses to handle before calling exit")
57    mshrs = Param.Int("number of MSHRs (max outstanding requests)")
58    prioritizeRequests = Param.Bool(False,
59        "always service demand misses first")
60    repl = Param.Repl(NULL, "replacement policy")
61    size = Param.MemorySize("capacity in bytes")
62    forward_snoops = Param.Bool(True,
63        "forward snoops from mem side to cpu side")
64    is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)")
65    subblock_size = Param.Int(0,
66        "Size of subblock in IIC used for compression")
67    tgts_per_mshr = Param.Int("max number of accesses per MSHR")
68    trace_addr = Param.Addr(0, "address to trace")
69    two_queue = Param.Bool(False,
70        "whether the lifo should have two queue replacement")
71    write_buffers = Param.Int(8, "number of write buffers")
72    prefetch_on_access = Param.Bool(False,
73         "notify the hardware prefetcher on every access (not just misses)")
74    prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
75    cpu_side = SlavePort("Port on side closer to CPU")
76    mem_side = MasterPort("Port on side closer to MEM")
77    addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port")
78    system = Param.System(Parent.any, "System we belong to")
79