Cache.py revision 8833 
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
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15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Nathan Binkert
28
29from m5.params import *
30from m5.proxy import *
31from MemObject import MemObject
32from Prefetcher import BasePrefetcher
33
34
35class BaseCache(MemObject):
36    type = 'BaseCache'
37    assoc = Param.Int("associativity")
38    block_size = Param.Int("block size in bytes")
39    latency = Param.Latency("Latency")
40    hash_delay = Param.Int(1, "time in cycles of hash access")
41    max_miss_count = Param.Counter(0,
42        "number of misses to handle before calling exit")
43    mshrs = Param.Int("number of MSHRs (max outstanding requests)")
44    prioritizeRequests = Param.Bool(False,
45        "always service demand misses first")
46    repl = Param.Repl(NULL, "replacement policy")
47    size = Param.MemorySize("capacity in bytes")
48    forward_snoops = Param.Bool(True,
49        "forward snoops from mem side to cpu side")
50    is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)")
51    subblock_size = Param.Int(0,
52        "Size of subblock in IIC used for compression")
53    tgts_per_mshr = Param.Int("max number of accesses per MSHR")
54    trace_addr = Param.Addr(0, "address to trace")
55    two_queue = Param.Bool(False,
56        "whether the lifo should have two queue replacement")
57    write_buffers = Param.Int(8, "number of write buffers")
58    prefetch_on_access = Param.Bool(False,
59         "notify the hardware prefetcher on every access (not just misses)")
60    prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
61    cpu_side = Port("Port on side closer to CPU")
62    mem_side = Port("Port on side closer to MEM")
63    addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port")
64    system = Param.System(Parent.any, "System we belong to")
65