Cache.py revision 3102
1from m5.params import *
2from MemObject import MemObject
3
4class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
5
6class BaseCache(MemObject):
7    type = 'BaseCache'
8    adaptive_compression = Param.Bool(False,
9        "Use an adaptive compression scheme")
10    assoc = Param.Int("associativity")
11    block_size = Param.Int("block size in bytes")
12    latency = Param.Int("Latency")
13    compressed_bus = Param.Bool(False,
14        "This cache connects to a compressed memory")
15    compression_latency = Param.Latency('0ns',
16        "Latency in cycles of compression algorithm")
17    do_copy = Param.Bool(False, "perform fast copies in the cache")
18    hash_delay = Param.Int(1, "time in cycles of hash access")
19    lifo = Param.Bool(False,
20        "whether this NIC partition should use LIFO repl. policy")
21    max_miss_count = Param.Counter(0,
22        "number of misses to handle before calling exit")
23    mshrs = Param.Int("number of MSHRs (max outstanding requests)")
24    prioritizeRequests = Param.Bool(False,
25        "always service demand misses first")
26    protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
27    repl = Param.Repl(NULL, "replacement policy")
28    size = Param.MemorySize("capacity in bytes")
29    split = Param.Bool(False, "whether or not this cache is split")
30    split_size = Param.Int(0,
31        "How many ways of the cache belong to CPU/LRU partition")
32    store_compressed = Param.Bool(False,
33        "Store compressed data in the cache")
34    subblock_size = Param.Int(0,
35        "Size of subblock in IIC used for compression")
36    tgts_per_mshr = Param.Int("max number of accesses per MSHR")
37    trace_addr = Param.Addr(0, "address to trace")
38    two_queue = Param.Bool(False,
39        "whether the lifo should have two queue replacement")
40    write_buffers = Param.Int(8, "number of write buffers")
41    prefetch_miss = Param.Bool(False,
42         "wheter you are using the hardware prefetcher from Miss stream")
43    prefetch_access = Param.Bool(False,
44         "wheter you are using the hardware prefetcher from Access stream")
45    prefetcher_size = Param.Int(100,
46         "Number of entries in the harware prefetch queue")
47    prefetch_past_page = Param.Bool(False,
48         "Allow prefetches to cross virtual page boundaries")
49    prefetch_serial_squash = Param.Bool(False,
50         "Squash prefetches with a later time on a subsequent miss")
51    prefetch_degree = Param.Int(1,
52         "Degree of the prefetch depth")
53    prefetch_latency = Param.Tick(10,
54         "Latency of the prefetcher")
55    prefetch_policy = Param.Prefetch('none',
56         "Type of prefetcher to use")
57    prefetch_cache_check_push = Param.Bool(True,
58         "Check if in cash on push or pop of prefetch queue")
59    prefetch_use_cpu_id = Param.Bool(True,
60         "Use the CPU ID to seperate calculations of prefetches")
61    prefetch_data_accesses_only = Param.Bool(False,
62         "Only prefetch on data not on instruction accesses")
63    hit_latency = Param.Int(1,"Hit Latency of the cache")
64    cpu_side = Port("Port on side closer to CPU")
65    mem_side = Port("Port on side closer to MEM")
66