bridge.hh revision 9294
12568SN/A/* 28922Swilliam.wang@arm.com * Copyright (c) 2011-2012 ARM Limited 38713Sandreas.hansson@arm.com * All rights reserved 48713Sandreas.hansson@arm.com * 58713Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68713Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78713Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88713Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98713Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108713Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118713Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128713Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138713Sandreas.hansson@arm.com * 142568SN/A * Copyright (c) 2006 The Regents of The University of Michigan 152568SN/A * All rights reserved. 162568SN/A * 172568SN/A * Redistribution and use in source and binary forms, with or without 182568SN/A * modification, are permitted provided that the following conditions are 192568SN/A * met: redistributions of source code must retain the above copyright 202568SN/A * notice, this list of conditions and the following disclaimer; 212568SN/A * redistributions in binary form must reproduce the above copyright 222568SN/A * notice, this list of conditions and the following disclaimer in the 232568SN/A * documentation and/or other materials provided with the distribution; 242568SN/A * neither the name of the copyright holders nor the names of its 252568SN/A * contributors may be used to endorse or promote products derived from 262568SN/A * this software without specific prior written permission. 272568SN/A * 282568SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292568SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302568SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312568SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322568SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332568SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342568SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352568SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362568SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372568SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382568SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 412665Ssaidi@eecs.umich.edu * Steve Reinhardt 428713Sandreas.hansson@arm.com * Andreas Hansson 432568SN/A */ 442568SN/A 452568SN/A/** 462982Sstever@eecs.umich.edu * @file 478713Sandreas.hansson@arm.com * Declaration of a memory-mapped bus bridge that connects a master 488713Sandreas.hansson@arm.com * and a slave through a request and response queue. 492568SN/A */ 502568SN/A 512568SN/A#ifndef __MEM_BRIDGE_HH__ 522568SN/A#define __MEM_BRIDGE_HH__ 532568SN/A 542568SN/A#include <list> 552568SN/A 566215Snate@binkert.org#include "base/types.hh" 572568SN/A#include "mem/mem_object.hh" 584762Snate@binkert.org#include "params/Bridge.hh" 592568SN/A 608713Sandreas.hansson@arm.com/** 618713Sandreas.hansson@arm.com * A bridge is used to interface two different busses (or in general a 628713Sandreas.hansson@arm.com * memory-mapped master and slave), with buffering for requests and 638713Sandreas.hansson@arm.com * responses. The bridge has a fixed delay for packets passing through 648713Sandreas.hansson@arm.com * it and responds to a fixed set of address ranges. 658713Sandreas.hansson@arm.com * 668713Sandreas.hansson@arm.com * The bridge comprises a slave port and a master port, that buffer 678713Sandreas.hansson@arm.com * outgoing responses and requests respectively. Buffer space is 688713Sandreas.hansson@arm.com * reserved when a request arrives, also reserving response space 699164Sandreas.hansson@arm.com * before forwarding the request. If there is no space present, then 709164Sandreas.hansson@arm.com * the bridge will delay accepting the packet until space becomes 719164Sandreas.hansson@arm.com * available. 728713Sandreas.hansson@arm.com */ 732568SN/Aclass Bridge : public MemObject 742568SN/A{ 752568SN/A protected: 768713Sandreas.hansson@arm.com 778713Sandreas.hansson@arm.com /** 789029Sandreas.hansson@arm.com * A bridge request state stores packets along with their sender 799029Sandreas.hansson@arm.com * state and original source. It has enough information to also 809029Sandreas.hansson@arm.com * restore the response once it comes back to the bridge. 818713Sandreas.hansson@arm.com */ 829044SAli.Saidi@ARM.com class RequestState : public Packet::SenderState 839029Sandreas.hansson@arm.com { 848713Sandreas.hansson@arm.com 858713Sandreas.hansson@arm.com public: 869029Sandreas.hansson@arm.com 878713Sandreas.hansson@arm.com Packet::SenderState *origSenderState; 889031Sandreas.hansson@arm.com PortID origSrc; 898713Sandreas.hansson@arm.com 909029Sandreas.hansson@arm.com RequestState(PacketPtr _pkt) 919029Sandreas.hansson@arm.com : origSenderState(_pkt->senderState), 929029Sandreas.hansson@arm.com origSrc(_pkt->getSrc()) 939029Sandreas.hansson@arm.com { } 948713Sandreas.hansson@arm.com 958713Sandreas.hansson@arm.com void fixResponse(PacketPtr pkt) 968713Sandreas.hansson@arm.com { 978713Sandreas.hansson@arm.com assert(pkt->senderState == this); 988713Sandreas.hansson@arm.com pkt->setDest(origSrc); 998713Sandreas.hansson@arm.com pkt->senderState = origSenderState; 1008713Sandreas.hansson@arm.com } 1018713Sandreas.hansson@arm.com }; 1028713Sandreas.hansson@arm.com 1039029Sandreas.hansson@arm.com /** 1049164Sandreas.hansson@arm.com * A deferred packet stores a packet along with its scheduled 1059164Sandreas.hansson@arm.com * transmission time 1069029Sandreas.hansson@arm.com */ 1079164Sandreas.hansson@arm.com class DeferredPacket 1089029Sandreas.hansson@arm.com { 1099029Sandreas.hansson@arm.com 1109029Sandreas.hansson@arm.com public: 1119029Sandreas.hansson@arm.com 1129164Sandreas.hansson@arm.com Tick tick; 1139029Sandreas.hansson@arm.com PacketPtr pkt; 1149029Sandreas.hansson@arm.com 1159164Sandreas.hansson@arm.com DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt) 1169029Sandreas.hansson@arm.com { } 1179029Sandreas.hansson@arm.com }; 1189029Sandreas.hansson@arm.com 1198713Sandreas.hansson@arm.com // Forward declaration to allow the slave port to have a pointer 1208713Sandreas.hansson@arm.com class BridgeMasterPort; 1218713Sandreas.hansson@arm.com 1228713Sandreas.hansson@arm.com /** 1238713Sandreas.hansson@arm.com * The port on the side that receives requests and sends 1248713Sandreas.hansson@arm.com * responses. The slave port has a set of address ranges that it 1258713Sandreas.hansson@arm.com * is responsible for. The slave port also has a buffer for the 1268713Sandreas.hansson@arm.com * responses not yet sent. 1278713Sandreas.hansson@arm.com */ 1288922Swilliam.wang@arm.com class BridgeSlavePort : public SlavePort 1292568SN/A { 1308713Sandreas.hansson@arm.com 1318713Sandreas.hansson@arm.com private: 1328713Sandreas.hansson@arm.com 1339164Sandreas.hansson@arm.com /** The bridge to which this port belongs. */ 1349164Sandreas.hansson@arm.com Bridge& bridge; 1352568SN/A 1362643Sstever@eecs.umich.edu /** 1379164Sandreas.hansson@arm.com * Master port on the other side of the bridge (connected to 1389164Sandreas.hansson@arm.com * the other bus). 1392643Sstever@eecs.umich.edu */ 1408851Sandreas.hansson@arm.com BridgeMasterPort& masterPort; 1418713Sandreas.hansson@arm.com 1428713Sandreas.hansson@arm.com /** Minimum request delay though this bridge. */ 1439180Sandreas.hansson@arm.com Cycles delay; 1448713Sandreas.hansson@arm.com 1458713Sandreas.hansson@arm.com /** Address ranges to pass through the bridge */ 1468713Sandreas.hansson@arm.com AddrRangeList ranges; 1478713Sandreas.hansson@arm.com 1488713Sandreas.hansson@arm.com /** 1498713Sandreas.hansson@arm.com * Response packet queue. Response packets are held in this 1508713Sandreas.hansson@arm.com * queue for a specified delay to model the processing delay 1518713Sandreas.hansson@arm.com * of the bridge. 1528713Sandreas.hansson@arm.com */ 1539164Sandreas.hansson@arm.com std::list<DeferredPacket> transmitList; 1548713Sandreas.hansson@arm.com 1558713Sandreas.hansson@arm.com /** Counter to track the outstanding responses. */ 1568713Sandreas.hansson@arm.com unsigned int outstandingResponses; 1578713Sandreas.hansson@arm.com 1589164Sandreas.hansson@arm.com /** If we should send a retry when space becomes available. */ 1599164Sandreas.hansson@arm.com bool retryReq; 1608713Sandreas.hansson@arm.com 1618713Sandreas.hansson@arm.com /** Max queue size for reserved responses. */ 1628713Sandreas.hansson@arm.com unsigned int respQueueLimit; 1638713Sandreas.hansson@arm.com 1648713Sandreas.hansson@arm.com /** 1658713Sandreas.hansson@arm.com * Is this side blocked from accepting new response packets. 1668713Sandreas.hansson@arm.com * 1678713Sandreas.hansson@arm.com * @return true if the reserved space has reached the set limit 1688713Sandreas.hansson@arm.com */ 1698713Sandreas.hansson@arm.com bool respQueueFull(); 1708713Sandreas.hansson@arm.com 1718713Sandreas.hansson@arm.com /** 1728713Sandreas.hansson@arm.com * Handle send event, scheduled when the packet at the head of 1738713Sandreas.hansson@arm.com * the response queue is ready to transmit (for timing 1748713Sandreas.hansson@arm.com * accesses only). 1758713Sandreas.hansson@arm.com */ 1769164Sandreas.hansson@arm.com void trySendTiming(); 1778713Sandreas.hansson@arm.com 1788713Sandreas.hansson@arm.com /** Send event for the response queue. */ 1799164Sandreas.hansson@arm.com EventWrapper<BridgeSlavePort, 1809164Sandreas.hansson@arm.com &BridgeSlavePort::trySendTiming> sendEvent; 1818713Sandreas.hansson@arm.com 1828713Sandreas.hansson@arm.com public: 1838713Sandreas.hansson@arm.com 1848713Sandreas.hansson@arm.com /** 1858713Sandreas.hansson@arm.com * Constructor for the BridgeSlavePort. 1868713Sandreas.hansson@arm.com * 1878713Sandreas.hansson@arm.com * @param _name the port name including the owner 1888713Sandreas.hansson@arm.com * @param _bridge the structural owner 1898713Sandreas.hansson@arm.com * @param _masterPort the master port on the other side of the bridge 1909180Sandreas.hansson@arm.com * @param _delay the delay in cycles from receiving to sending 1918713Sandreas.hansson@arm.com * @param _resp_limit the size of the response queue 1928713Sandreas.hansson@arm.com * @param _ranges a number of address ranges to forward 1938713Sandreas.hansson@arm.com */ 1949164Sandreas.hansson@arm.com BridgeSlavePort(const std::string& _name, Bridge& _bridge, 1959180Sandreas.hansson@arm.com BridgeMasterPort& _masterPort, Cycles _delay, 1969235Sandreas.hansson@arm.com int _resp_limit, std::vector<AddrRange> _ranges); 1978713Sandreas.hansson@arm.com 1988713Sandreas.hansson@arm.com /** 1998713Sandreas.hansson@arm.com * Queue a response packet to be sent out later and also schedule 2008713Sandreas.hansson@arm.com * a send if necessary. 2018713Sandreas.hansson@arm.com * 2028713Sandreas.hansson@arm.com * @param pkt a response to send out after a delay 2039164Sandreas.hansson@arm.com * @param when tick when response packet should be sent 2048713Sandreas.hansson@arm.com */ 2059164Sandreas.hansson@arm.com void schedTimingResp(PacketPtr pkt, Tick when); 2069164Sandreas.hansson@arm.com 2079164Sandreas.hansson@arm.com /** 2089164Sandreas.hansson@arm.com * Retry any stalled request that we have failed to accept at 2099164Sandreas.hansson@arm.com * an earlier point in time. This call will do nothing if no 2109164Sandreas.hansson@arm.com * request is waiting. 2119164Sandreas.hansson@arm.com */ 2129164Sandreas.hansson@arm.com void retryStalledReq(); 2138713Sandreas.hansson@arm.com 2148713Sandreas.hansson@arm.com protected: 2158713Sandreas.hansson@arm.com 2168713Sandreas.hansson@arm.com /** When receiving a timing request from the peer port, 2178713Sandreas.hansson@arm.com pass it to the bridge. */ 2189164Sandreas.hansson@arm.com bool recvTimingReq(PacketPtr pkt); 2198713Sandreas.hansson@arm.com 2208713Sandreas.hansson@arm.com /** When receiving a retry request from the peer port, 2218713Sandreas.hansson@arm.com pass it to the bridge. */ 2229164Sandreas.hansson@arm.com void recvRetry(); 2238713Sandreas.hansson@arm.com 2248713Sandreas.hansson@arm.com /** When receiving a Atomic requestfrom the peer port, 2258713Sandreas.hansson@arm.com pass it to the bridge. */ 2269164Sandreas.hansson@arm.com Tick recvAtomic(PacketPtr pkt); 2278713Sandreas.hansson@arm.com 2288713Sandreas.hansson@arm.com /** When receiving a Functional request from the peer port, 2298713Sandreas.hansson@arm.com pass it to the bridge. */ 2309164Sandreas.hansson@arm.com void recvFunctional(PacketPtr pkt); 2318713Sandreas.hansson@arm.com 2328713Sandreas.hansson@arm.com /** When receiving a address range request the peer port, 2338713Sandreas.hansson@arm.com pass it to the bridge. */ 2349164Sandreas.hansson@arm.com AddrRangeList getAddrRanges() const; 2358713Sandreas.hansson@arm.com }; 2368713Sandreas.hansson@arm.com 2378713Sandreas.hansson@arm.com 2388713Sandreas.hansson@arm.com /** 2398713Sandreas.hansson@arm.com * Port on the side that forwards requests and receives 2408713Sandreas.hansson@arm.com * responses. The master port has a buffer for the requests not 2418713Sandreas.hansson@arm.com * yet sent. 2428713Sandreas.hansson@arm.com */ 2438922Swilliam.wang@arm.com class BridgeMasterPort : public MasterPort 2448713Sandreas.hansson@arm.com { 2458713Sandreas.hansson@arm.com 2468713Sandreas.hansson@arm.com private: 2478713Sandreas.hansson@arm.com 2489164Sandreas.hansson@arm.com /** The bridge to which this port belongs. */ 2499164Sandreas.hansson@arm.com Bridge& bridge; 2508713Sandreas.hansson@arm.com 2518713Sandreas.hansson@arm.com /** 2529164Sandreas.hansson@arm.com * The slave port on the other side of the bridge (connected 2539164Sandreas.hansson@arm.com * to the other bus). 2548713Sandreas.hansson@arm.com */ 2558851Sandreas.hansson@arm.com BridgeSlavePort& slavePort; 2562643Sstever@eecs.umich.edu 2572643Sstever@eecs.umich.edu /** Minimum delay though this bridge. */ 2589180Sandreas.hansson@arm.com Cycles delay; 2592643Sstever@eecs.umich.edu 2608713Sandreas.hansson@arm.com /** 2618713Sandreas.hansson@arm.com * Request packet queue. Request packets are held in this 2628713Sandreas.hansson@arm.com * queue for a specified delay to model the processing delay 2638713Sandreas.hansson@arm.com * of the bridge. 2648713Sandreas.hansson@arm.com */ 2659164Sandreas.hansson@arm.com std::list<DeferredPacket> transmitList; 2664435Ssaidi@eecs.umich.edu 2678713Sandreas.hansson@arm.com /** Max queue size for request packets */ 2688713Sandreas.hansson@arm.com unsigned int reqQueueLimit; 2694433Ssaidi@eecs.umich.edu 2702643Sstever@eecs.umich.edu /** 2712643Sstever@eecs.umich.edu * Handle send event, scheduled when the packet at the head of 2722643Sstever@eecs.umich.edu * the outbound queue is ready to transmit (for timing 2732643Sstever@eecs.umich.edu * accesses only). 2742643Sstever@eecs.umich.edu */ 2759164Sandreas.hansson@arm.com void trySendTiming(); 2762643Sstever@eecs.umich.edu 2778713Sandreas.hansson@arm.com /** Send event for the request queue. */ 2789164Sandreas.hansson@arm.com EventWrapper<BridgeMasterPort, 2799164Sandreas.hansson@arm.com &BridgeMasterPort::trySendTiming> sendEvent; 2802568SN/A 2812568SN/A public: 2828713Sandreas.hansson@arm.com 2838713Sandreas.hansson@arm.com /** 2848713Sandreas.hansson@arm.com * Constructor for the BridgeMasterPort. 2858713Sandreas.hansson@arm.com * 2868713Sandreas.hansson@arm.com * @param _name the port name including the owner 2878713Sandreas.hansson@arm.com * @param _bridge the structural owner 2888713Sandreas.hansson@arm.com * @param _slavePort the slave port on the other side of the bridge 2899180Sandreas.hansson@arm.com * @param _delay the delay in cycles from receiving to sending 2908713Sandreas.hansson@arm.com * @param _req_limit the size of the request queue 2918713Sandreas.hansson@arm.com */ 2929164Sandreas.hansson@arm.com BridgeMasterPort(const std::string& _name, Bridge& _bridge, 2939180Sandreas.hansson@arm.com BridgeSlavePort& _slavePort, Cycles _delay, 2948713Sandreas.hansson@arm.com int _req_limit); 2958713Sandreas.hansson@arm.com 2968713Sandreas.hansson@arm.com /** 2978713Sandreas.hansson@arm.com * Is this side blocked from accepting new request packets. 2988713Sandreas.hansson@arm.com * 2998713Sandreas.hansson@arm.com * @return true if the occupied space has reached the set limit 3008713Sandreas.hansson@arm.com */ 3018713Sandreas.hansson@arm.com bool reqQueueFull(); 3028713Sandreas.hansson@arm.com 3038713Sandreas.hansson@arm.com /** 3048713Sandreas.hansson@arm.com * Queue a request packet to be sent out later and also schedule 3058713Sandreas.hansson@arm.com * a send if necessary. 3068713Sandreas.hansson@arm.com * 3078713Sandreas.hansson@arm.com * @param pkt a request to send out after a delay 3089164Sandreas.hansson@arm.com * @param when tick when response packet should be sent 3098713Sandreas.hansson@arm.com */ 3109164Sandreas.hansson@arm.com void schedTimingReq(PacketPtr pkt, Tick when); 3118713Sandreas.hansson@arm.com 3128713Sandreas.hansson@arm.com /** 3138713Sandreas.hansson@arm.com * Check a functional request against the packets in our 3148713Sandreas.hansson@arm.com * request queue. 3158713Sandreas.hansson@arm.com * 3168713Sandreas.hansson@arm.com * @param pkt packet to check against 3178713Sandreas.hansson@arm.com * 3188713Sandreas.hansson@arm.com * @return true if we find a match 3198713Sandreas.hansson@arm.com */ 3208713Sandreas.hansson@arm.com bool checkFunctional(PacketPtr pkt); 3212568SN/A 3222568SN/A protected: 3232568SN/A 3242643Sstever@eecs.umich.edu /** When receiving a timing request from the peer port, 3252643Sstever@eecs.umich.edu pass it to the bridge. */ 3269164Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt); 3272568SN/A 3282643Sstever@eecs.umich.edu /** When receiving a retry request from the peer port, 3292568SN/A pass it to the bridge. */ 3309164Sandreas.hansson@arm.com void recvRetry(); 3312568SN/A }; 3322568SN/A 3338713Sandreas.hansson@arm.com /** Slave port of the bridge. */ 3348713Sandreas.hansson@arm.com BridgeSlavePort slavePort; 3358713Sandreas.hansson@arm.com 3368713Sandreas.hansson@arm.com /** Master port of the bridge. */ 3378713Sandreas.hansson@arm.com BridgeMasterPort masterPort; 3382568SN/A 3392568SN/A public: 3402568SN/A 3419294Sandreas.hansson@arm.com virtual BaseMasterPort& getMasterPort(const std::string& if_name, 3429294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 3439294Sandreas.hansson@arm.com virtual BaseSlavePort& getSlavePort(const std::string& if_name, 3449294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 3452568SN/A 3462568SN/A virtual void init(); 3472568SN/A 3489164Sandreas.hansson@arm.com typedef BridgeParams Params; 3499164Sandreas.hansson@arm.com 3504435Ssaidi@eecs.umich.edu Bridge(Params *p); 3512568SN/A}; 3522568SN/A 3532568SN/A#endif //__MEM_BUS_HH__ 354