bridge.hh revision 9029
12568SN/A/* 28922Swilliam.wang@arm.com * Copyright (c) 2011-2012 ARM Limited 38713Sandreas.hansson@arm.com * All rights reserved 48713Sandreas.hansson@arm.com * 58713Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68713Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78713Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88713Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98713Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108713Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118713Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128713Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138713Sandreas.hansson@arm.com * 142568SN/A * Copyright (c) 2006 The Regents of The University of Michigan 152568SN/A * All rights reserved. 162568SN/A * 172568SN/A * Redistribution and use in source and binary forms, with or without 182568SN/A * modification, are permitted provided that the following conditions are 192568SN/A * met: redistributions of source code must retain the above copyright 202568SN/A * notice, this list of conditions and the following disclaimer; 212568SN/A * redistributions in binary form must reproduce the above copyright 222568SN/A * notice, this list of conditions and the following disclaimer in the 232568SN/A * documentation and/or other materials provided with the distribution; 242568SN/A * neither the name of the copyright holders nor the names of its 252568SN/A * contributors may be used to endorse or promote products derived from 262568SN/A * this software without specific prior written permission. 272568SN/A * 282568SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292568SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302568SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312568SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322568SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332568SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342568SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352568SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362568SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372568SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382568SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 412665Ssaidi@eecs.umich.edu * Steve Reinhardt 428713Sandreas.hansson@arm.com * Andreas Hansson 432568SN/A */ 442568SN/A 452568SN/A/** 462982Sstever@eecs.umich.edu * @file 478713Sandreas.hansson@arm.com * Declaration of a memory-mapped bus bridge that connects a master 488713Sandreas.hansson@arm.com * and a slave through a request and response queue. 492568SN/A */ 502568SN/A 512568SN/A#ifndef __MEM_BRIDGE_HH__ 522568SN/A#define __MEM_BRIDGE_HH__ 532568SN/A 542568SN/A#include <list> 552568SN/A#include <queue> 568229Snate@binkert.org#include <string> 572568SN/A 585386Sstever@gmail.com#include "base/fast_alloc.hh" 596215Snate@binkert.org#include "base/types.hh" 602568SN/A#include "mem/mem_object.hh" 612568SN/A#include "mem/packet.hh" 622568SN/A#include "mem/port.hh" 634762Snate@binkert.org#include "params/Bridge.hh" 642568SN/A#include "sim/eventq.hh" 652568SN/A 668713Sandreas.hansson@arm.com/** 678713Sandreas.hansson@arm.com * A bridge is used to interface two different busses (or in general a 688713Sandreas.hansson@arm.com * memory-mapped master and slave), with buffering for requests and 698713Sandreas.hansson@arm.com * responses. The bridge has a fixed delay for packets passing through 708713Sandreas.hansson@arm.com * it and responds to a fixed set of address ranges. 718713Sandreas.hansson@arm.com * 728713Sandreas.hansson@arm.com * The bridge comprises a slave port and a master port, that buffer 738713Sandreas.hansson@arm.com * outgoing responses and requests respectively. Buffer space is 748713Sandreas.hansson@arm.com * reserved when a request arrives, also reserving response space 758713Sandreas.hansson@arm.com * before forwarding the request. An incoming request is always 768713Sandreas.hansson@arm.com * accepted (recvTiming returns true), but is potentially NACKed if 778713Sandreas.hansson@arm.com * there is no request space or response space. 788713Sandreas.hansson@arm.com */ 792568SN/Aclass Bridge : public MemObject 802568SN/A{ 812568SN/A protected: 828713Sandreas.hansson@arm.com 838713Sandreas.hansson@arm.com /** 849029Sandreas.hansson@arm.com * A bridge request state stores packets along with their sender 859029Sandreas.hansson@arm.com * state and original source. It has enough information to also 869029Sandreas.hansson@arm.com * restore the response once it comes back to the bridge. 878713Sandreas.hansson@arm.com */ 889029Sandreas.hansson@arm.com class RequestState : public Packet::SenderState, public FastAlloc 899029Sandreas.hansson@arm.com { 908713Sandreas.hansson@arm.com 918713Sandreas.hansson@arm.com public: 929029Sandreas.hansson@arm.com 938713Sandreas.hansson@arm.com Packet::SenderState *origSenderState; 948949Sandreas.hansson@arm.com Packet::NodeID origSrc; 958713Sandreas.hansson@arm.com 969029Sandreas.hansson@arm.com RequestState(PacketPtr _pkt) 979029Sandreas.hansson@arm.com : origSenderState(_pkt->senderState), 989029Sandreas.hansson@arm.com origSrc(_pkt->getSrc()) 999029Sandreas.hansson@arm.com { } 1008713Sandreas.hansson@arm.com 1018713Sandreas.hansson@arm.com void fixResponse(PacketPtr pkt) 1028713Sandreas.hansson@arm.com { 1038713Sandreas.hansson@arm.com assert(pkt->senderState == this); 1048713Sandreas.hansson@arm.com pkt->setDest(origSrc); 1058713Sandreas.hansson@arm.com pkt->senderState = origSenderState; 1068713Sandreas.hansson@arm.com } 1078713Sandreas.hansson@arm.com }; 1088713Sandreas.hansson@arm.com 1099029Sandreas.hansson@arm.com /** 1109029Sandreas.hansson@arm.com * A deferred request stores a packet along with its scheduled 1119029Sandreas.hansson@arm.com * transmission time, and whether we can expect to see a response 1129029Sandreas.hansson@arm.com * or not. 1139029Sandreas.hansson@arm.com */ 1149029Sandreas.hansson@arm.com class DeferredRequest 1159029Sandreas.hansson@arm.com { 1169029Sandreas.hansson@arm.com 1179029Sandreas.hansson@arm.com public: 1189029Sandreas.hansson@arm.com 1199029Sandreas.hansson@arm.com Tick ready; 1209029Sandreas.hansson@arm.com PacketPtr pkt; 1219029Sandreas.hansson@arm.com bool expectResponse; 1229029Sandreas.hansson@arm.com 1239029Sandreas.hansson@arm.com DeferredRequest(PacketPtr _pkt, Tick t) 1249029Sandreas.hansson@arm.com : ready(t), pkt(_pkt), expectResponse(_pkt->needsResponse()) 1259029Sandreas.hansson@arm.com { } 1269029Sandreas.hansson@arm.com }; 1279029Sandreas.hansson@arm.com 1289029Sandreas.hansson@arm.com /** 1299029Sandreas.hansson@arm.com * A deferred response stores a packet along with its scheduled 1309029Sandreas.hansson@arm.com * transmission time. It also contains information of whether the 1319029Sandreas.hansson@arm.com * bridge NACKed the packet to be able to correctly maintain 1329029Sandreas.hansson@arm.com * counters of outstanding responses. 1339029Sandreas.hansson@arm.com */ 1349029Sandreas.hansson@arm.com class DeferredResponse { 1359029Sandreas.hansson@arm.com 1369029Sandreas.hansson@arm.com public: 1379029Sandreas.hansson@arm.com 1389029Sandreas.hansson@arm.com Tick ready; 1399029Sandreas.hansson@arm.com PacketPtr pkt; 1409029Sandreas.hansson@arm.com bool nackedHere; 1419029Sandreas.hansson@arm.com 1429029Sandreas.hansson@arm.com DeferredResponse(PacketPtr _pkt, Tick t, bool nack = false) 1439029Sandreas.hansson@arm.com : ready(t), pkt(_pkt), nackedHere(nack) 1449029Sandreas.hansson@arm.com { } 1459029Sandreas.hansson@arm.com }; 1469029Sandreas.hansson@arm.com 1478713Sandreas.hansson@arm.com // Forward declaration to allow the slave port to have a pointer 1488713Sandreas.hansson@arm.com class BridgeMasterPort; 1498713Sandreas.hansson@arm.com 1508713Sandreas.hansson@arm.com /** 1518713Sandreas.hansson@arm.com * The port on the side that receives requests and sends 1528713Sandreas.hansson@arm.com * responses. The slave port has a set of address ranges that it 1538713Sandreas.hansson@arm.com * is responsible for. The slave port also has a buffer for the 1548713Sandreas.hansson@arm.com * responses not yet sent. 1558713Sandreas.hansson@arm.com */ 1568922Swilliam.wang@arm.com class BridgeSlavePort : public SlavePort 1572568SN/A { 1588713Sandreas.hansson@arm.com 1598713Sandreas.hansson@arm.com private: 1608713Sandreas.hansson@arm.com 1612643Sstever@eecs.umich.edu /** A pointer to the bridge to which this port belongs. */ 1622568SN/A Bridge *bridge; 1632568SN/A 1642643Sstever@eecs.umich.edu /** 1658851Sandreas.hansson@arm.com * Master port on the other side of the bridge 1662643Sstever@eecs.umich.edu * (connected to the other bus). 1672643Sstever@eecs.umich.edu */ 1688851Sandreas.hansson@arm.com BridgeMasterPort& masterPort; 1698713Sandreas.hansson@arm.com 1708713Sandreas.hansson@arm.com /** Minimum request delay though this bridge. */ 1718713Sandreas.hansson@arm.com Tick delay; 1728713Sandreas.hansson@arm.com 1738713Sandreas.hansson@arm.com /** Min delay to respond with a nack. */ 1748713Sandreas.hansson@arm.com Tick nackDelay; 1758713Sandreas.hansson@arm.com 1768713Sandreas.hansson@arm.com /** Address ranges to pass through the bridge */ 1778713Sandreas.hansson@arm.com AddrRangeList ranges; 1788713Sandreas.hansson@arm.com 1798713Sandreas.hansson@arm.com /** 1808713Sandreas.hansson@arm.com * Response packet queue. Response packets are held in this 1818713Sandreas.hansson@arm.com * queue for a specified delay to model the processing delay 1828713Sandreas.hansson@arm.com * of the bridge. 1838713Sandreas.hansson@arm.com */ 1849029Sandreas.hansson@arm.com std::list<DeferredResponse> responseQueue; 1858713Sandreas.hansson@arm.com 1868713Sandreas.hansson@arm.com /** Counter to track the outstanding responses. */ 1878713Sandreas.hansson@arm.com unsigned int outstandingResponses; 1888713Sandreas.hansson@arm.com 1898713Sandreas.hansson@arm.com /** If we're waiting for a retry to happen. */ 1908713Sandreas.hansson@arm.com bool inRetry; 1918713Sandreas.hansson@arm.com 1928713Sandreas.hansson@arm.com /** Max queue size for reserved responses. */ 1938713Sandreas.hansson@arm.com unsigned int respQueueLimit; 1948713Sandreas.hansson@arm.com 1958713Sandreas.hansson@arm.com /** 1968713Sandreas.hansson@arm.com * Is this side blocked from accepting new response packets. 1978713Sandreas.hansson@arm.com * 1988713Sandreas.hansson@arm.com * @return true if the reserved space has reached the set limit 1998713Sandreas.hansson@arm.com */ 2008713Sandreas.hansson@arm.com bool respQueueFull(); 2018713Sandreas.hansson@arm.com 2028713Sandreas.hansson@arm.com /** 2038713Sandreas.hansson@arm.com * Turn the request packet into a NACK response and put it in 2048713Sandreas.hansson@arm.com * the response queue and schedule its transmission. 2058713Sandreas.hansson@arm.com * 2068713Sandreas.hansson@arm.com * @param pkt the request packet to NACK 2078713Sandreas.hansson@arm.com */ 2088713Sandreas.hansson@arm.com void nackRequest(PacketPtr pkt); 2098713Sandreas.hansson@arm.com 2108713Sandreas.hansson@arm.com /** 2118713Sandreas.hansson@arm.com * Handle send event, scheduled when the packet at the head of 2128713Sandreas.hansson@arm.com * the response queue is ready to transmit (for timing 2138713Sandreas.hansson@arm.com * accesses only). 2148713Sandreas.hansson@arm.com */ 2158713Sandreas.hansson@arm.com void trySend(); 2168713Sandreas.hansson@arm.com 2178713Sandreas.hansson@arm.com /** 2188713Sandreas.hansson@arm.com * Private class for scheduling sending of responses from the 2198713Sandreas.hansson@arm.com * response queue. 2208713Sandreas.hansson@arm.com */ 2218713Sandreas.hansson@arm.com class SendEvent : public Event 2228713Sandreas.hansson@arm.com { 2238851Sandreas.hansson@arm.com BridgeSlavePort& port; 2248713Sandreas.hansson@arm.com 2258713Sandreas.hansson@arm.com public: 2268851Sandreas.hansson@arm.com SendEvent(BridgeSlavePort& p) : port(p) {} 2278851Sandreas.hansson@arm.com virtual void process() { port.trySend(); } 2288713Sandreas.hansson@arm.com virtual const char *description() const { return "bridge send"; } 2298713Sandreas.hansson@arm.com }; 2308713Sandreas.hansson@arm.com 2318713Sandreas.hansson@arm.com /** Send event for the response queue. */ 2328713Sandreas.hansson@arm.com SendEvent sendEvent; 2338713Sandreas.hansson@arm.com 2348713Sandreas.hansson@arm.com public: 2358713Sandreas.hansson@arm.com 2368713Sandreas.hansson@arm.com /** 2378713Sandreas.hansson@arm.com * Constructor for the BridgeSlavePort. 2388713Sandreas.hansson@arm.com * 2398713Sandreas.hansson@arm.com * @param _name the port name including the owner 2408713Sandreas.hansson@arm.com * @param _bridge the structural owner 2418713Sandreas.hansson@arm.com * @param _masterPort the master port on the other side of the bridge 2428713Sandreas.hansson@arm.com * @param _delay the delay from seeing a response to sending it 2438713Sandreas.hansson@arm.com * @param _nack_delay the delay from a NACK to sending the response 2448713Sandreas.hansson@arm.com * @param _resp_limit the size of the response queue 2458713Sandreas.hansson@arm.com * @param _ranges a number of address ranges to forward 2468713Sandreas.hansson@arm.com */ 2478713Sandreas.hansson@arm.com BridgeSlavePort(const std::string &_name, Bridge *_bridge, 2488851Sandreas.hansson@arm.com BridgeMasterPort& _masterPort, int _delay, 2498713Sandreas.hansson@arm.com int _nack_delay, int _resp_limit, 2508713Sandreas.hansson@arm.com std::vector<Range<Addr> > _ranges); 2518713Sandreas.hansson@arm.com 2528713Sandreas.hansson@arm.com /** 2538713Sandreas.hansson@arm.com * Queue a response packet to be sent out later and also schedule 2548713Sandreas.hansson@arm.com * a send if necessary. 2558713Sandreas.hansson@arm.com * 2568713Sandreas.hansson@arm.com * @param pkt a response to send out after a delay 2578713Sandreas.hansson@arm.com */ 2588713Sandreas.hansson@arm.com void queueForSendTiming(PacketPtr pkt); 2598713Sandreas.hansson@arm.com 2608713Sandreas.hansson@arm.com protected: 2618713Sandreas.hansson@arm.com 2628713Sandreas.hansson@arm.com /** When receiving a timing request from the peer port, 2638713Sandreas.hansson@arm.com pass it to the bridge. */ 2648975Sandreas.hansson@arm.com virtual bool recvTimingReq(PacketPtr pkt); 2658713Sandreas.hansson@arm.com 2668713Sandreas.hansson@arm.com /** When receiving a retry request from the peer port, 2678713Sandreas.hansson@arm.com pass it to the bridge. */ 2688713Sandreas.hansson@arm.com virtual void recvRetry(); 2698713Sandreas.hansson@arm.com 2708713Sandreas.hansson@arm.com /** When receiving a Atomic requestfrom the peer port, 2718713Sandreas.hansson@arm.com pass it to the bridge. */ 2728713Sandreas.hansson@arm.com virtual Tick recvAtomic(PacketPtr pkt); 2738713Sandreas.hansson@arm.com 2748713Sandreas.hansson@arm.com /** When receiving a Functional request from the peer port, 2758713Sandreas.hansson@arm.com pass it to the bridge. */ 2768713Sandreas.hansson@arm.com virtual void recvFunctional(PacketPtr pkt); 2778713Sandreas.hansson@arm.com 2788713Sandreas.hansson@arm.com /** When receiving a address range request the peer port, 2798713Sandreas.hansson@arm.com pass it to the bridge. */ 2808713Sandreas.hansson@arm.com virtual AddrRangeList getAddrRanges(); 2818713Sandreas.hansson@arm.com }; 2828713Sandreas.hansson@arm.com 2838713Sandreas.hansson@arm.com 2848713Sandreas.hansson@arm.com /** 2858713Sandreas.hansson@arm.com * Port on the side that forwards requests and receives 2868713Sandreas.hansson@arm.com * responses. The master port has a buffer for the requests not 2878713Sandreas.hansson@arm.com * yet sent. 2888713Sandreas.hansson@arm.com */ 2898922Swilliam.wang@arm.com class BridgeMasterPort : public MasterPort 2908713Sandreas.hansson@arm.com { 2918713Sandreas.hansson@arm.com 2928713Sandreas.hansson@arm.com private: 2938713Sandreas.hansson@arm.com 2948713Sandreas.hansson@arm.com /** A pointer to the bridge to which this port belongs. */ 2958713Sandreas.hansson@arm.com Bridge* bridge; 2968713Sandreas.hansson@arm.com 2978713Sandreas.hansson@arm.com /** 2988713Sandreas.hansson@arm.com * Pointer to the slave port on the other side of the bridge 2998713Sandreas.hansson@arm.com * (connected to the other bus). 3008713Sandreas.hansson@arm.com */ 3018851Sandreas.hansson@arm.com BridgeSlavePort& slavePort; 3022643Sstever@eecs.umich.edu 3032643Sstever@eecs.umich.edu /** Minimum delay though this bridge. */ 3042643Sstever@eecs.umich.edu Tick delay; 3052643Sstever@eecs.umich.edu 3068713Sandreas.hansson@arm.com /** 3078713Sandreas.hansson@arm.com * Request packet queue. Request packets are held in this 3088713Sandreas.hansson@arm.com * queue for a specified delay to model the processing delay 3098713Sandreas.hansson@arm.com * of the bridge. 3108713Sandreas.hansson@arm.com */ 3119029Sandreas.hansson@arm.com std::list<DeferredRequest> requestQueue; 3124435Ssaidi@eecs.umich.edu 3138713Sandreas.hansson@arm.com /** If we're waiting for a retry to happen. */ 3144435Ssaidi@eecs.umich.edu bool inRetry; 3154435Ssaidi@eecs.umich.edu 3168713Sandreas.hansson@arm.com /** Max queue size for request packets */ 3178713Sandreas.hansson@arm.com unsigned int reqQueueLimit; 3184433Ssaidi@eecs.umich.edu 3192643Sstever@eecs.umich.edu /** 3202643Sstever@eecs.umich.edu * Handle send event, scheduled when the packet at the head of 3212643Sstever@eecs.umich.edu * the outbound queue is ready to transmit (for timing 3222643Sstever@eecs.umich.edu * accesses only). 3232643Sstever@eecs.umich.edu */ 3242643Sstever@eecs.umich.edu void trySend(); 3252643Sstever@eecs.umich.edu 3268713Sandreas.hansson@arm.com /** 3278713Sandreas.hansson@arm.com * Private class for scheduling sending of requests from the 3288713Sandreas.hansson@arm.com * request queue. 3298713Sandreas.hansson@arm.com */ 3302643Sstever@eecs.umich.edu class SendEvent : public Event 3312643Sstever@eecs.umich.edu { 3328851Sandreas.hansson@arm.com BridgeMasterPort& port; 3332643Sstever@eecs.umich.edu 3342643Sstever@eecs.umich.edu public: 3358851Sandreas.hansson@arm.com SendEvent(BridgeMasterPort& p) : port(p) {} 3368851Sandreas.hansson@arm.com virtual void process() { port.trySend(); } 3375336Shines@cs.fsu.edu virtual const char *description() const { return "bridge send"; } 3382643Sstever@eecs.umich.edu }; 3392643Sstever@eecs.umich.edu 3408713Sandreas.hansson@arm.com /** Send event for the request queue. */ 3412643Sstever@eecs.umich.edu SendEvent sendEvent; 3422568SN/A 3432568SN/A public: 3448713Sandreas.hansson@arm.com 3458713Sandreas.hansson@arm.com /** 3468713Sandreas.hansson@arm.com * Constructor for the BridgeMasterPort. 3478713Sandreas.hansson@arm.com * 3488713Sandreas.hansson@arm.com * @param _name the port name including the owner 3498713Sandreas.hansson@arm.com * @param _bridge the structural owner 3508713Sandreas.hansson@arm.com * @param _slavePort the slave port on the other side of the bridge 3518713Sandreas.hansson@arm.com * @param _delay the delay from seeing a request to sending it 3528713Sandreas.hansson@arm.com * @param _req_limit the size of the request queue 3538713Sandreas.hansson@arm.com */ 3548713Sandreas.hansson@arm.com BridgeMasterPort(const std::string &_name, Bridge *_bridge, 3558851Sandreas.hansson@arm.com BridgeSlavePort& _slavePort, int _delay, 3568713Sandreas.hansson@arm.com int _req_limit); 3578713Sandreas.hansson@arm.com 3588713Sandreas.hansson@arm.com /** 3598713Sandreas.hansson@arm.com * Is this side blocked from accepting new request packets. 3608713Sandreas.hansson@arm.com * 3618713Sandreas.hansson@arm.com * @return true if the occupied space has reached the set limit 3628713Sandreas.hansson@arm.com */ 3638713Sandreas.hansson@arm.com bool reqQueueFull(); 3648713Sandreas.hansson@arm.com 3658713Sandreas.hansson@arm.com /** 3668713Sandreas.hansson@arm.com * Queue a request packet to be sent out later and also schedule 3678713Sandreas.hansson@arm.com * a send if necessary. 3688713Sandreas.hansson@arm.com * 3698713Sandreas.hansson@arm.com * @param pkt a request to send out after a delay 3708713Sandreas.hansson@arm.com */ 3718713Sandreas.hansson@arm.com void queueForSendTiming(PacketPtr pkt); 3728713Sandreas.hansson@arm.com 3738713Sandreas.hansson@arm.com /** 3748713Sandreas.hansson@arm.com * Check a functional request against the packets in our 3758713Sandreas.hansson@arm.com * request queue. 3768713Sandreas.hansson@arm.com * 3778713Sandreas.hansson@arm.com * @param pkt packet to check against 3788713Sandreas.hansson@arm.com * 3798713Sandreas.hansson@arm.com * @return true if we find a match 3808713Sandreas.hansson@arm.com */ 3818713Sandreas.hansson@arm.com bool checkFunctional(PacketPtr pkt); 3822568SN/A 3832568SN/A protected: 3842568SN/A 3852643Sstever@eecs.umich.edu /** When receiving a timing request from the peer port, 3862643Sstever@eecs.umich.edu pass it to the bridge. */ 3878975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 3882568SN/A 3892643Sstever@eecs.umich.edu /** When receiving a retry request from the peer port, 3902568SN/A pass it to the bridge. */ 3912657Ssaidi@eecs.umich.edu virtual void recvRetry(); 3922568SN/A }; 3932568SN/A 3948713Sandreas.hansson@arm.com /** Slave port of the bridge. */ 3958713Sandreas.hansson@arm.com BridgeSlavePort slavePort; 3968713Sandreas.hansson@arm.com 3978713Sandreas.hansson@arm.com /** Master port of the bridge. */ 3988713Sandreas.hansson@arm.com BridgeMasterPort masterPort; 3992568SN/A 4002568SN/A /** If this bridge should acknowledge writes. */ 4012568SN/A bool ackWrites; 4022568SN/A 4032568SN/A public: 4044762Snate@binkert.org typedef BridgeParams Params; 4054435Ssaidi@eecs.umich.edu 4064435Ssaidi@eecs.umich.edu protected: 4074435Ssaidi@eecs.umich.edu Params *_params; 4084435Ssaidi@eecs.umich.edu 4094435Ssaidi@eecs.umich.edu public: 4104435Ssaidi@eecs.umich.edu const Params *params() const { return _params; } 4112568SN/A 4128922Swilliam.wang@arm.com virtual MasterPort& getMasterPort(const std::string& if_name, 4138922Swilliam.wang@arm.com int idx = -1); 4148922Swilliam.wang@arm.com virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1); 4152568SN/A 4162568SN/A virtual void init(); 4172568SN/A 4184435Ssaidi@eecs.umich.edu Bridge(Params *p); 4192568SN/A}; 4202568SN/A 4212568SN/A#endif //__MEM_BUS_HH__ 422