abstract_mem.hh revision 13892
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ron Dreslinski 41 * Andreas Hansson 42 */ 43 44/** 45 * @file 46 * AbstractMemory declaration 47 */ 48 49#ifndef __MEM_ABSTRACT_MEMORY_HH__ 50#define __MEM_ABSTRACT_MEMORY_HH__ 51 52#include "mem/backdoor.hh" 53#include "mem/port.hh" 54#include "params/AbstractMemory.hh" 55#include "sim/clocked_object.hh" 56#include "sim/stats.hh" 57 58 59class System; 60 61/** 62 * Locked address class that represents a physical address and a 63 * context id. 64 */ 65class LockedAddr { 66 67 private: 68 69 // on alpha, minimum LL/SC granularity is 16 bytes, so lower 70 // bits need to masked off. 71 static const Addr Addr_Mask = 0xf; 72 73 public: 74 75 // locked address 76 Addr addr; 77 78 // locking hw context 79 const ContextID contextId; 80 81 static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); } 82 83 // check for matching execution context 84 bool matchesContext(const RequestPtr &req) const 85 { 86 return (contextId == req->contextId()); 87 } 88 89 LockedAddr(const RequestPtr &req) : addr(mask(req->getPaddr())), 90 contextId(req->contextId()) 91 {} 92 93 // constructor for unserialization use 94 LockedAddr(Addr _addr, int _cid) : addr(_addr), contextId(_cid) 95 {} 96}; 97 98/** 99 * An abstract memory represents a contiguous block of physical 100 * memory, with an associated address range, and also provides basic 101 * functionality for reading and writing this memory without any 102 * timing information. It is a ClockedObject since subclasses may need timing 103 * information. 104 */ 105class AbstractMemory : public ClockedObject 106{ 107 protected: 108 109 // Address range of this memory 110 AddrRange range; 111 112 // Pointer to host memory used to implement this memory 113 uint8_t* pmemAddr; 114 115 // Backdoor to access this memory. 116 MemBackdoor backdoor; 117 118 // Enable specific memories to be reported to the configuration table 119 const bool confTableReported; 120 121 // Should the memory appear in the global address map 122 const bool inAddrMap; 123 124 // Should KVM map this memory for the guest 125 const bool kvmMap; 126 127 std::list<LockedAddr> lockedAddrList; 128 129 // helper function for checkLockedAddrs(): we really want to 130 // inline a quick check for an empty locked addr list (hopefully 131 // the common case), and do the full list search (if necessary) in 132 // this out-of-line function 133 bool checkLockedAddrList(PacketPtr pkt); 134 135 // Record the address of a load-locked operation so that we can 136 // clear the execution context's lock flag if a matching store is 137 // performed 138 void trackLoadLocked(PacketPtr pkt); 139 140 // Compare a store address with any locked addresses so we can 141 // clear the lock flag appropriately. Return value set to 'false' 142 // if store operation should be suppressed (because it was a 143 // conditional store and the address was no longer locked by the 144 // requesting execution context), 'true' otherwise. Note that 145 // this method must be called on *all* stores since even 146 // non-conditional stores must clear any matching lock addresses. 147 bool writeOK(PacketPtr pkt) { 148 const RequestPtr &req = pkt->req; 149 if (lockedAddrList.empty()) { 150 // no locked addrs: nothing to check, store_conditional fails 151 bool isLLSC = pkt->isLLSC(); 152 if (isLLSC) { 153 req->setExtraData(0); 154 } 155 return !isLLSC; // only do write if not an sc 156 } else { 157 // iterate over list... 158 return checkLockedAddrList(pkt); 159 } 160 } 161 162 /** Number of total bytes read from this memory */ 163 Stats::Vector bytesRead; 164 /** Number of instruction bytes read from this memory */ 165 Stats::Vector bytesInstRead; 166 /** Number of bytes written to this memory */ 167 Stats::Vector bytesWritten; 168 /** Number of read requests */ 169 Stats::Vector numReads; 170 /** Number of write requests */ 171 Stats::Vector numWrites; 172 /** Number of other requests */ 173 Stats::Vector numOther; 174 /** Read bandwidth from this memory */ 175 Stats::Formula bwRead; 176 /** Read bandwidth from this memory */ 177 Stats::Formula bwInstRead; 178 /** Write bandwidth from this memory */ 179 Stats::Formula bwWrite; 180 /** Total bandwidth from this memory */ 181 Stats::Formula bwTotal; 182 183 /** Pointor to the System object. 184 * This is used for getting the number of masters in the system which is 185 * needed when registering stats 186 */ 187 System *_system; 188 189 190 private: 191 192 // Prevent copying 193 AbstractMemory(const AbstractMemory&); 194 195 // Prevent assignment 196 AbstractMemory& operator=(const AbstractMemory&); 197 198 public: 199 200 typedef AbstractMemoryParams Params; 201 202 AbstractMemory(const Params* p); 203 virtual ~AbstractMemory() {} 204 205 /** 206 * Initialise this memory. 207 */ 208 void init() override; 209 210 /** 211 * See if this is a null memory that should never store data and 212 * always return zero. 213 * 214 * @return true if null 215 */ 216 bool isNull() const { return params()->null; } 217 218 /** 219 * Set the host memory backing store to be used by this memory 220 * controller. 221 * 222 * @param pmem_addr Pointer to a segment of host memory 223 */ 224 void setBackingStore(uint8_t* pmem_addr); 225 226 /** 227 * Get the list of locked addresses to allow checkpointing. 228 */ 229 const std::list<LockedAddr>& getLockedAddrList() const 230 { return lockedAddrList; } 231 232 /** 233 * Add a locked address to allow for checkpointing. 234 */ 235 void addLockedAddr(LockedAddr addr) { lockedAddrList.push_back(addr); } 236 237 /** read the system pointer 238 * Implemented for completeness with the setter 239 * @return pointer to the system object */ 240 System* system() const { return _system; } 241 242 /** Set the system pointer on this memory 243 * This can't be done via a python parameter because the system needs 244 * pointers to all the memories and the reverse would create a cycle in the 245 * object graph. An init() this is set. 246 * @param sys system pointer to set 247 */ 248 void system(System *sys) { _system = sys; } 249 250 const Params * 251 params() const 252 { 253 return dynamic_cast<const Params *>(_params); 254 } 255 256 /** 257 * Get the address range 258 * 259 * @return a single contigous address range 260 */ 261 AddrRange getAddrRange() const; 262 263 /** 264 * Get the memory size. 265 * 266 * @return the size of the memory 267 */ 268 uint64_t size() const { return range.size(); } 269 270 /** 271 * Get the start address. 272 * 273 * @return the start address of the memory 274 */ 275 Addr start() const { return range.start(); } 276 277 /** 278 * Should this memory be passed to the kernel and part of the OS 279 * physical memory layout. 280 * 281 * @return if this memory is reported 282 */ 283 bool isConfReported() const { return confTableReported; } 284 285 /** 286 * Some memories are used as shadow memories or should for other 287 * reasons not be part of the global address map. 288 * 289 * @return if this memory is part of the address map 290 */ 291 bool isInAddrMap() const { return inAddrMap; } 292 293 /** 294 * When shadow memories are in use, KVM may want to make one or the other, 295 * but cannot map both into the guest address space. 296 * 297 * @return if this memory should be mapped into the KVM guest address space 298 */ 299 bool isKvmMap() const { return kvmMap; } 300 301 /** 302 * Perform an untimed memory access and update all the state 303 * (e.g. locked addresses) and statistics accordingly. The packet 304 * is turned into a response if required. 305 * 306 * @param pkt Packet performing the access 307 */ 308 void access(PacketPtr pkt); 309 310 /** 311 * Perform an untimed memory read or write without changing 312 * anything but the memory itself. No stats are affected by this 313 * access. In addition to normal accesses this also facilitates 314 * print requests. 315 * 316 * @param pkt Packet performing the access 317 */ 318 void functionalAccess(PacketPtr pkt); 319 320 /** 321 * Register Statistics 322 */ 323 void regStats() override; 324 325}; 326 327#endif //__MEM_ABSTRACT_MEMORY_HH__ 328