abstract_mem.cc revision 9293
12207SN/A/* 22207SN/A * Copyright (c) 2010-2012 ARM Limited 32207SN/A * All rights reserved 42207SN/A * 52207SN/A * The license below extends only to copyright in the software and shall 62207SN/A * not be construed as granting a license to any other intellectual 72207SN/A * property including but not limited to intellectual property relating 82207SN/A * to a hardware implementation of the functionality of the software 92207SN/A * licensed hereunder. You may use the software subject to the license 102207SN/A * terms below provided that you ensure that this notice is replicated 112207SN/A * unmodified and in its entirety in all distributions of the software, 122207SN/A * modified or unmodified, in source code or in binary form. 132207SN/A * 142207SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 152207SN/A * All rights reserved. 162207SN/A * 172207SN/A * Redistribution and use in source and binary forms, with or without 182207SN/A * modification, are permitted provided that the following conditions are 192207SN/A * met: redistributions of source code must retain the above copyright 202207SN/A * notice, this list of conditions and the following disclaimer; 212207SN/A * redistributions in binary form must reproduce the above copyright 222207SN/A * notice, this list of conditions and the following disclaimer in the 232207SN/A * documentation and/or other materials provided with the distribution; 242207SN/A * neither the name of the copyright holders nor the names of its 252207SN/A * contributors may be used to endorse or promote products derived from 262207SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323589Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334111Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342474SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352207SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363760Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372454SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382976Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392454SN/A * 402680Sktlim@umich.edu * Authors: Ron Dreslinski 412561SN/A * Ali Saidi 424434Ssaidi@eecs.umich.edu * Andreas Hansson 432561SN/A */ 442474SN/A 452207SN/A#include "arch/registers.hh" 462458SN/A#include "config/the_isa.hh" 472474SN/A#include "debug/LLSC.hh" 482458SN/A#include "debug/MemoryAccess.hh" 492207SN/A#include "mem/abstract_mem.hh" 505154Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 515285Sgblack@eecs.umich.edu#include "sim/system.hh" 525285Sgblack@eecs.umich.edu 532474SN/Ausing namespace std; 542474SN/A 552474SN/AAbstractMemory::AbstractMemory(const Params *p) : 562474SN/A MemObject(p), range(params()->range), pmemAddr(NULL), 572474SN/A confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map), 582474SN/A _system(NULL) 592474SN/A{ 602474SN/A if (size() % TheISA::PageBytes != 0) 613415Sgblack@eecs.umich.edu panic("Memory Size not divisible by page size\n"); 623415Sgblack@eecs.umich.edu} 633415Sgblack@eecs.umich.edu 643415Sgblack@eecs.umich.eduvoid 652474SN/AAbstractMemory::setBackingStore(uint8_t* pmem_addr) 662474SN/A{ 674111Sgblack@eecs.umich.edu pmemAddr = pmem_addr; 684111Sgblack@eecs.umich.edu} 694111Sgblack@eecs.umich.edu 704111Sgblack@eecs.umich.eduvoid 715128Sgblack@eecs.umich.eduAbstractMemory::regStats() 725128Sgblack@eecs.umich.edu{ 735128Sgblack@eecs.umich.edu using namespace Stats; 745128Sgblack@eecs.umich.edu 755128Sgblack@eecs.umich.edu assert(system()); 765128Sgblack@eecs.umich.edu 775128Sgblack@eecs.umich.edu bytesRead 784111Sgblack@eecs.umich.edu .init(system()->maxMasters()) 795128Sgblack@eecs.umich.edu .name(name() + ".bytes_read") 805128Sgblack@eecs.umich.edu .desc("Number of bytes read from this memory") 815128Sgblack@eecs.umich.edu .flags(total | nozero | nonan) 825128Sgblack@eecs.umich.edu ; 835128Sgblack@eecs.umich.edu for (int i = 0; i < system()->maxMasters(); i++) { 845128Sgblack@eecs.umich.edu bytesRead.subname(i, system()->getMasterName(i)); 855128Sgblack@eecs.umich.edu } 865128Sgblack@eecs.umich.edu bytesInstRead 875128Sgblack@eecs.umich.edu .init(system()->maxMasters()) 885128Sgblack@eecs.umich.edu .name(name() + ".bytes_inst_read") 895128Sgblack@eecs.umich.edu .desc("Number of instructions bytes read from this memory") 905128Sgblack@eecs.umich.edu .flags(total | nozero | nonan) 915128Sgblack@eecs.umich.edu ; 925128Sgblack@eecs.umich.edu for (int i = 0; i < system()->maxMasters(); i++) { 935128Sgblack@eecs.umich.edu bytesInstRead.subname(i, system()->getMasterName(i)); 945128Sgblack@eecs.umich.edu } 955128Sgblack@eecs.umich.edu bytesWritten 965128Sgblack@eecs.umich.edu .init(system()->maxMasters()) 975128Sgblack@eecs.umich.edu .name(name() + ".bytes_written") 985128Sgblack@eecs.umich.edu .desc("Number of bytes written to this memory") 995128Sgblack@eecs.umich.edu .flags(total | nozero | nonan) 1005128Sgblack@eecs.umich.edu ; 1015128Sgblack@eecs.umich.edu for (int i = 0; i < system()->maxMasters(); i++) { 1025128Sgblack@eecs.umich.edu bytesWritten.subname(i, system()->getMasterName(i)); 1035128Sgblack@eecs.umich.edu } 1044111Sgblack@eecs.umich.edu numReads 1054111Sgblack@eecs.umich.edu .init(system()->maxMasters()) 1064111Sgblack@eecs.umich.edu .name(name() + ".num_reads") 1074111Sgblack@eecs.umich.edu .desc("Number of read requests responded to by this memory") 1084111Sgblack@eecs.umich.edu .flags(total | nozero | nonan) 1094111Sgblack@eecs.umich.edu ; 1102474SN/A for (int i = 0; i < system()->maxMasters(); i++) { 1115285Sgblack@eecs.umich.edu numReads.subname(i, system()->getMasterName(i)); 1124111Sgblack@eecs.umich.edu } 1135285Sgblack@eecs.umich.edu numWrites 1144111Sgblack@eecs.umich.edu .init(system()->maxMasters()) 1154111Sgblack@eecs.umich.edu .name(name() + ".num_writes") 1164111Sgblack@eecs.umich.edu .desc("Number of write requests responded to by this memory") 1172646Ssaidi@eecs.umich.edu .flags(total | nozero | nonan) 1184172Ssaidi@eecs.umich.edu ; 1192646Ssaidi@eecs.umich.edu for (int i = 0; i < system()->maxMasters(); i++) { 1204172Ssaidi@eecs.umich.edu numWrites.subname(i, system()->getMasterName(i)); 1214997Sgblack@eecs.umich.edu } 1222561SN/A numOther 1232561SN/A .init(system()->maxMasters()) 1242561SN/A .name(name() + ".num_other") 1252561SN/A .desc("Number of other requests responded to by this memory") 1262561SN/A .flags(total | nozero | nonan) 1274172Ssaidi@eecs.umich.edu ; 1283761Sgblack@eecs.umich.edu for (int i = 0; i < system()->maxMasters(); i++) { 1292561SN/A numOther.subname(i, system()->getMasterName(i)); 1304172Ssaidi@eecs.umich.edu } 1313761Sgblack@eecs.umich.edu bwRead 1322561SN/A .name(name() + ".bw_read") 1334172Ssaidi@eecs.umich.edu .desc("Total read bandwidth from this memory (bytes/s)") 1343761Sgblack@eecs.umich.edu .precision(0) 1352561SN/A .prereq(bytesRead) 1364172Ssaidi@eecs.umich.edu .flags(total | nozero | nonan) 1373761Sgblack@eecs.umich.edu ; 1382561SN/A for (int i = 0; i < system()->maxMasters(); i++) { 1394172Ssaidi@eecs.umich.edu bwRead.subname(i, system()->getMasterName(i)); 1403415Sgblack@eecs.umich.edu } 1414172Ssaidi@eecs.umich.edu 1423761Sgblack@eecs.umich.edu bwInstRead 1433415Sgblack@eecs.umich.edu .name(name() + ".bw_inst_read") 1444172Ssaidi@eecs.umich.edu .desc("Instruction read bandwidth from this memory (bytes/s)") 1453589Sgblack@eecs.umich.edu .precision(0) 1464172Ssaidi@eecs.umich.edu .prereq(bytesInstRead) 1474997Sgblack@eecs.umich.edu .flags(total | nozero | nonan) 1484997Sgblack@eecs.umich.edu ; 1494997Sgblack@eecs.umich.edu for (int i = 0; i < system()->maxMasters(); i++) { 1504997Sgblack@eecs.umich.edu bwInstRead.subname(i, system()->getMasterName(i)); 1514997Sgblack@eecs.umich.edu } 1524997Sgblack@eecs.umich.edu bwWrite 1532474SN/A .name(name() + ".bw_write") 1542474SN/A .desc("Write bandwidth from this memory (bytes/s)") 1555285Sgblack@eecs.umich.edu .precision(0) 1565285Sgblack@eecs.umich.edu .prereq(bytesWritten) 1572585SN/A .flags(total | nozero | nonan) 1585285Sgblack@eecs.umich.edu ; 1595285Sgblack@eecs.umich.edu for (int i = 0; i < system()->maxMasters(); i++) { 1602585SN/A bwWrite.subname(i, system()->getMasterName(i)); 1615285Sgblack@eecs.umich.edu } 1625285Sgblack@eecs.umich.edu bwTotal 1635285Sgblack@eecs.umich.edu .name(name() + ".bw_total") 1645285Sgblack@eecs.umich.edu .desc("Total bandwidth to/from this memory (bytes/s)") 1655285Sgblack@eecs.umich.edu .precision(0) 1665285Sgblack@eecs.umich.edu .prereq(bwTotal) 1674111Sgblack@eecs.umich.edu .flags(total | nozero | nonan) 1683415Sgblack@eecs.umich.edu ; 1692561SN/A for (int i = 0; i < system()->maxMasters(); i++) { 1705285Sgblack@eecs.umich.edu bwTotal.subname(i, system()->getMasterName(i)); 1712561SN/A } 1725285Sgblack@eecs.umich.edu bwRead = bytesRead / simSeconds; 1735285Sgblack@eecs.umich.edu bwInstRead = bytesInstRead / simSeconds; 1745285Sgblack@eecs.umich.edu bwWrite = bytesWritten / simSeconds; 1755285Sgblack@eecs.umich.edu bwTotal = (bytesRead + bytesWritten) / simSeconds; 1765285Sgblack@eecs.umich.edu} 1775285Sgblack@eecs.umich.edu 1785285Sgblack@eecs.umich.eduAddrRange 1795285Sgblack@eecs.umich.eduAbstractMemory::getAddrRange() const 1805285Sgblack@eecs.umich.edu{ 1815285Sgblack@eecs.umich.edu return range; 1825285Sgblack@eecs.umich.edu} 1835285Sgblack@eecs.umich.edu 1845285Sgblack@eecs.umich.edu// Add load-locked to tracking list. Should only be called if the 1855285Sgblack@eecs.umich.edu// operation is a load and the LLSC flag is set. 1865285Sgblack@eecs.umich.eduvoid 1875285Sgblack@eecs.umich.eduAbstractMemory::trackLoadLocked(PacketPtr pkt) 1885285Sgblack@eecs.umich.edu{ 1895285Sgblack@eecs.umich.edu Request *req = pkt->req; 1905285Sgblack@eecs.umich.edu Addr paddr = LockedAddr::mask(req->getPaddr()); 1915285Sgblack@eecs.umich.edu 1922474SN/A // first we check if we already have a locked addr for this 1933044Sgblack@eecs.umich.edu // xc. Since each xc only gets one, we just update the 1943044Sgblack@eecs.umich.edu // existing record with the new address. 1953044Sgblack@eecs.umich.edu list<LockedAddr>::iterator i; 1963044Sgblack@eecs.umich.edu 1973044Sgblack@eecs.umich.edu for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) { 1983044Sgblack@eecs.umich.edu if (i->matchesContext(req)) { 1995285Sgblack@eecs.umich.edu DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n", 2005285Sgblack@eecs.umich.edu req->contextId(), paddr); 2015286Sgblack@eecs.umich.edu i->addr = paddr; 2022561SN/A return; 2032561SN/A } 2042561SN/A } 2052561SN/A 2062585SN/A // no record for this xc: need to allocate a new one 2072585SN/A DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n", 2082585SN/A req->contextId(), paddr); 2092585SN/A lockedAddrList.push_front(LockedAddr(req)); 2102585SN/A} 2112585SN/A 2122585SN/A 2132585SN/A// Called on *writes* only... both regular stores and 2142585SN/A// store-conditional operations. Check for conventional stores which 2152585SN/A// conflict with locked addresses, and for success/failure of store 2162585SN/A// conditionals. 2172585SN/Abool 2182585SN/AAbstractMemory::checkLockedAddrList(PacketPtr pkt) 2192585SN/A{ 2202585SN/A Request *req = pkt->req; 2212585SN/A Addr paddr = LockedAddr::mask(req->getPaddr()); 2222585SN/A bool isLLSC = pkt->isLLSC(); 2232585SN/A 2242585SN/A // Initialize return value. Non-conditional stores always 2252585SN/A // succeed. Assume conditional stores will fail until proven 2262585SN/A // otherwise. 2272976Sgblack@eecs.umich.edu bool allowStore = !isLLSC; 2282976Sgblack@eecs.umich.edu 2292976Sgblack@eecs.umich.edu // Iterate over list. Note that there could be multiple matching records, 2302976Sgblack@eecs.umich.edu // as more than one context could have done a load locked to this location. 2312976Sgblack@eecs.umich.edu // Only remove records when we succeed in finding a record for (xc, addr); 2322976Sgblack@eecs.umich.edu // then, remove all records with this address. Failed store-conditionals do 2334793Sgblack@eecs.umich.edu // not blow unrelated reservations. 2342976Sgblack@eecs.umich.edu list<LockedAddr>::iterator i = lockedAddrList.begin(); 2354793Sgblack@eecs.umich.edu 2362976Sgblack@eecs.umich.edu if (isLLSC) { 2372976Sgblack@eecs.umich.edu while (i != lockedAddrList.end()) { 2384793Sgblack@eecs.umich.edu if (i->addr == paddr && i->matchesContext(req)) { 2392976Sgblack@eecs.umich.edu // it's a store conditional, and as far as the memory system can 2402976Sgblack@eecs.umich.edu // tell, the requesting context's lock is still valid. 2414793Sgblack@eecs.umich.edu DPRINTF(LLSC, "StCond success: context %d addr %#x\n", 2422976Sgblack@eecs.umich.edu req->contextId(), paddr); 2434793Sgblack@eecs.umich.edu allowStore = true; 2442976Sgblack@eecs.umich.edu break; 2454793Sgblack@eecs.umich.edu } 2462976Sgblack@eecs.umich.edu // If we didn't find a match, keep searching! Someone else may well 2472976Sgblack@eecs.umich.edu // have a reservation on this line here but we may find ours in just 2482976Sgblack@eecs.umich.edu // a little while. 2494793Sgblack@eecs.umich.edu i++; 2502976Sgblack@eecs.umich.edu } 2514793Sgblack@eecs.umich.edu req->setExtraData(allowStore ? 1 : 0); 2522976Sgblack@eecs.umich.edu } 2534793Sgblack@eecs.umich.edu // LLSCs that succeeded AND non-LLSC stores both fall into here: 2542976Sgblack@eecs.umich.edu if (allowStore) { 2554793Sgblack@eecs.umich.edu // We write address paddr. However, there may be several entries with a 2564793Sgblack@eecs.umich.edu // reservation on this address (for other contextIds) and they must all 2574793Sgblack@eecs.umich.edu // be removed. 2584793Sgblack@eecs.umich.edu i = lockedAddrList.begin(); 2592976Sgblack@eecs.umich.edu while (i != lockedAddrList.end()) { 2604793Sgblack@eecs.umich.edu if (i->addr == paddr) { 2612976Sgblack@eecs.umich.edu DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n", 2622585SN/A i->contextId, paddr); 2632561SN/A i = lockedAddrList.erase(i); 2642561SN/A } else { 2654164Sgblack@eecs.umich.edu i++; 2665286Sgblack@eecs.umich.edu } 2674111Sgblack@eecs.umich.edu } 2684111Sgblack@eecs.umich.edu } 2694111Sgblack@eecs.umich.edu 2704111Sgblack@eecs.umich.edu return allowStore; 2714111Sgblack@eecs.umich.edu} 2724111Sgblack@eecs.umich.edu 2734111Sgblack@eecs.umich.edu 2744111Sgblack@eecs.umich.edu#if TRACING_ON 2754111Sgblack@eecs.umich.edu 2764111Sgblack@eecs.umich.edu#define CASE(A, T) \ 2774111Sgblack@eecs.umich.edu case sizeof(T): \ 2784111Sgblack@eecs.umich.edu DPRINTF(MemoryAccess,"%s of size %i on address 0x%x data 0x%x\n", \ 2794111Sgblack@eecs.umich.edu A, pkt->getSize(), pkt->getAddr(), pkt->get<T>()); \ 2804111Sgblack@eecs.umich.edu break 2815286Sgblack@eecs.umich.edu 2825286Sgblack@eecs.umich.edu 2835286Sgblack@eecs.umich.edu#define TRACE_PACKET(A) \ 2845286Sgblack@eecs.umich.edu do { \ 2855286Sgblack@eecs.umich.edu switch (pkt->getSize()) { \ 2865286Sgblack@eecs.umich.edu CASE(A, uint64_t); \ 2875286Sgblack@eecs.umich.edu CASE(A, uint32_t); \ 2884111Sgblack@eecs.umich.edu CASE(A, uint16_t); \ 2895285Sgblack@eecs.umich.edu CASE(A, uint8_t); \ 2904111Sgblack@eecs.umich.edu default: \ 2914111Sgblack@eecs.umich.edu DPRINTF(MemoryAccess, "%s of size %i on address 0x%x\n", \ 2924111Sgblack@eecs.umich.edu A, pkt->getSize(), pkt->getAddr()); \ 2934111Sgblack@eecs.umich.edu DDUMP(MemoryAccess, pkt->getPtr<uint8_t>(), pkt->getSize());\ 2944111Sgblack@eecs.umich.edu } \ 2954111Sgblack@eecs.umich.edu } while (0) 2964111Sgblack@eecs.umich.edu 2974111Sgblack@eecs.umich.edu#else 2985286Sgblack@eecs.umich.edu 2995286Sgblack@eecs.umich.edu#define TRACE_PACKET(A) 3004111Sgblack@eecs.umich.edu 3014111Sgblack@eecs.umich.edu#endif 3024111Sgblack@eecs.umich.edu 3034111Sgblack@eecs.umich.eduvoid 3044111Sgblack@eecs.umich.eduAbstractMemory::access(PacketPtr pkt) 3054111Sgblack@eecs.umich.edu{ 3065286Sgblack@eecs.umich.edu assert(pkt->getAddr() >= range.start && 3075286Sgblack@eecs.umich.edu (pkt->getAddr() + pkt->getSize() - 1) <= range.end); 3085286Sgblack@eecs.umich.edu 3095286Sgblack@eecs.umich.edu if (pkt->memInhibitAsserted()) { 3105286Sgblack@eecs.umich.edu DPRINTF(MemoryAccess, "mem inhibited on 0x%x: not responding\n", 3115286Sgblack@eecs.umich.edu pkt->getAddr()); 3125286Sgblack@eecs.umich.edu return; 3135286Sgblack@eecs.umich.edu } 3145286Sgblack@eecs.umich.edu 3155286Sgblack@eecs.umich.edu uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start; 3164111Sgblack@eecs.umich.edu 3175286Sgblack@eecs.umich.edu if (pkt->cmd == MemCmd::SwapReq) { 3184111Sgblack@eecs.umich.edu TheISA::IntReg overwrite_val; 3194111Sgblack@eecs.umich.edu bool overwrite_mem; 3205285Sgblack@eecs.umich.edu uint64_t condition_val64; 3214111Sgblack@eecs.umich.edu uint32_t condition_val32; 3224111Sgblack@eecs.umich.edu 3234111Sgblack@eecs.umich.edu if (!pmemAddr) 3244111Sgblack@eecs.umich.edu panic("Swap only works if there is real memory (i.e. null=False)"); 3255286Sgblack@eecs.umich.edu assert(sizeof(TheISA::IntReg) >= pkt->getSize()); 3265286Sgblack@eecs.umich.edu 3275286Sgblack@eecs.umich.edu overwrite_mem = true; 3285286Sgblack@eecs.umich.edu // keep a copy of our possible write value, and copy what is at the 3295286Sgblack@eecs.umich.edu // memory address into the packet 3305286Sgblack@eecs.umich.edu std::memcpy(&overwrite_val, pkt->getPtr<uint8_t>(), pkt->getSize()); 3315286Sgblack@eecs.umich.edu std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 3325286Sgblack@eecs.umich.edu 3335286Sgblack@eecs.umich.edu if (pkt->req->isCondSwap()) { 3345286Sgblack@eecs.umich.edu if (pkt->getSize() == sizeof(uint64_t)) { 3355286Sgblack@eecs.umich.edu condition_val64 = pkt->req->getExtraData(); 3365286Sgblack@eecs.umich.edu overwrite_mem = !std::memcmp(&condition_val64, hostAddr, 3374111Sgblack@eecs.umich.edu sizeof(uint64_t)); 3384111Sgblack@eecs.umich.edu } else if (pkt->getSize() == sizeof(uint32_t)) { 3395286Sgblack@eecs.umich.edu condition_val32 = (uint32_t)pkt->req->getExtraData(); 3405286Sgblack@eecs.umich.edu overwrite_mem = !std::memcmp(&condition_val32, hostAddr, 3415285Sgblack@eecs.umich.edu sizeof(uint32_t)); 3425285Sgblack@eecs.umich.edu } else 3435285Sgblack@eecs.umich.edu panic("Invalid size for conditional read/write\n"); 3445285Sgblack@eecs.umich.edu } 3455285Sgblack@eecs.umich.edu 3465285Sgblack@eecs.umich.edu if (overwrite_mem) 3475285Sgblack@eecs.umich.edu std::memcpy(hostAddr, &overwrite_val, pkt->getSize()); 3485285Sgblack@eecs.umich.edu 3495285Sgblack@eecs.umich.edu assert(!pkt->req->isInstFetch()); 3504111Sgblack@eecs.umich.edu TRACE_PACKET("Read/Write"); 3515286Sgblack@eecs.umich.edu numOther[pkt->req->masterId()]++; 3525286Sgblack@eecs.umich.edu } else if (pkt->isRead()) { 3534111Sgblack@eecs.umich.edu assert(!pkt->isWrite()); 3544111Sgblack@eecs.umich.edu if (pkt->isLLSC()) { 3554111Sgblack@eecs.umich.edu trackLoadLocked(pkt); 3565285Sgblack@eecs.umich.edu } 3575567Snate@binkert.org if (pmemAddr) 3584111Sgblack@eecs.umich.edu memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 3595286Sgblack@eecs.umich.edu TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read"); 3605286Sgblack@eecs.umich.edu numReads[pkt->req->masterId()]++; 3615286Sgblack@eecs.umich.edu bytesRead[pkt->req->masterId()] += pkt->getSize(); 3625286Sgblack@eecs.umich.edu if (pkt->req->isInstFetch()) 3634111Sgblack@eecs.umich.edu bytesInstRead[pkt->req->masterId()] += pkt->getSize(); 3644111Sgblack@eecs.umich.edu } else if (pkt->isWrite()) { 3654111Sgblack@eecs.umich.edu if (writeOK(pkt)) { 3664111Sgblack@eecs.umich.edu if (pmemAddr) 3674111Sgblack@eecs.umich.edu memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize()); 3684111Sgblack@eecs.umich.edu assert(!pkt->req->isInstFetch()); 3694111Sgblack@eecs.umich.edu TRACE_PACKET("Write"); 3704111Sgblack@eecs.umich.edu numWrites[pkt->req->masterId()]++; 3714111Sgblack@eecs.umich.edu bytesWritten[pkt->req->masterId()] += pkt->getSize(); 3724111Sgblack@eecs.umich.edu } 3734111Sgblack@eecs.umich.edu } else if (pkt->isInvalidate()) { 3744111Sgblack@eecs.umich.edu // no need to do anything 3755285Sgblack@eecs.umich.edu } else { 3764111Sgblack@eecs.umich.edu panic("unimplemented"); 3775285Sgblack@eecs.umich.edu } 3785286Sgblack@eecs.umich.edu 3795286Sgblack@eecs.umich.edu if (pkt->needsResponse()) { 3805286Sgblack@eecs.umich.edu pkt->makeResponse(); 3815286Sgblack@eecs.umich.edu } 3824111Sgblack@eecs.umich.edu} 3834117Sgblack@eecs.umich.edu 3844117Sgblack@eecs.umich.eduvoid 3854111Sgblack@eecs.umich.eduAbstractMemory::functionalAccess(PacketPtr pkt) 3864111Sgblack@eecs.umich.edu{ 3874111Sgblack@eecs.umich.edu assert(pkt->getAddr() >= range.start && 3885285Sgblack@eecs.umich.edu (pkt->getAddr() + pkt->getSize() - 1) <= range.end); 3895285Sgblack@eecs.umich.edu 3905285Sgblack@eecs.umich.edu uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start; 3914111Sgblack@eecs.umich.edu 3925285Sgblack@eecs.umich.edu if (pkt->isRead()) { 3934111Sgblack@eecs.umich.edu if (pmemAddr) 3944111Sgblack@eecs.umich.edu memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 3954772Sgblack@eecs.umich.edu TRACE_PACKET("Read"); 3964772Sgblack@eecs.umich.edu pkt->makeResponse(); 3974772Sgblack@eecs.umich.edu } else if (pkt->isWrite()) { 3985285Sgblack@eecs.umich.edu if (pmemAddr) 3994111Sgblack@eecs.umich.edu memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize()); 4005231Sgblack@eecs.umich.edu TRACE_PACKET("Write"); 4015231Sgblack@eecs.umich.edu pkt->makeResponse(); 4025231Sgblack@eecs.umich.edu } else if (pkt->isPrint()) { 4035231Sgblack@eecs.umich.edu Packet::PrintReqState *prs = 4045285Sgblack@eecs.umich.edu dynamic_cast<Packet::PrintReqState*>(pkt->senderState); 4054111Sgblack@eecs.umich.edu assert(prs); 4064111Sgblack@eecs.umich.edu // Need to call printLabels() explicitly since we're not going 4074111Sgblack@eecs.umich.edu // through printObj(). 4084111Sgblack@eecs.umich.edu prs->printLabels(); 4094111Sgblack@eecs.umich.edu // Right now we just print the single byte at the specified address. 4104111Sgblack@eecs.umich.edu ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *hostAddr); 4114111Sgblack@eecs.umich.edu } else { 4124111Sgblack@eecs.umich.edu panic("AbstractMemory: unimplemented functional command %s", 4134111Sgblack@eecs.umich.edu pkt->cmdString()); 4145128Sgblack@eecs.umich.edu } 4155285Sgblack@eecs.umich.edu} 4165285Sgblack@eecs.umich.edu