abstract_mem.cc revision 12218
1/* 2 * Copyright (c) 2010-2012,2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ron Dreslinski 41 * Ali Saidi 42 * Andreas Hansson 43 */ 44 45#include "mem/abstract_mem.hh" 46 47#include <vector> 48 49#include "arch/locked_mem.hh" 50#include "cpu/base.hh" 51#include "cpu/thread_context.hh" 52#include "debug/LLSC.hh" 53#include "debug/MemoryAccess.hh" 54#include "mem/packet_access.hh" 55#include "sim/system.hh" 56 57using namespace std; 58 59AbstractMemory::AbstractMemory(const Params *p) : 60 MemObject(p), range(params()->range), pmemAddr(NULL), 61 confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map), 62 kvmMap(p->kvm_map), _system(NULL) 63{ 64} 65 66void 67AbstractMemory::init() 68{ 69 assert(system()); 70 71 if (size() % _system->getPageBytes() != 0) 72 panic("Memory Size not divisible by page size\n"); 73} 74 75void 76AbstractMemory::setBackingStore(uint8_t* pmem_addr) 77{ 78 pmemAddr = pmem_addr; 79} 80 81void 82AbstractMemory::regStats() 83{ 84 MemObject::regStats(); 85 86 using namespace Stats; 87 88 assert(system()); 89 90 bytesRead 91 .init(system()->maxMasters()) 92 .name(name() + ".bytes_read") 93 .desc("Number of bytes read from this memory") 94 .flags(total | nozero | nonan) 95 ; 96 for (int i = 0; i < system()->maxMasters(); i++) { 97 bytesRead.subname(i, system()->getMasterName(i)); 98 } 99 bytesInstRead 100 .init(system()->maxMasters()) 101 .name(name() + ".bytes_inst_read") 102 .desc("Number of instructions bytes read from this memory") 103 .flags(total | nozero | nonan) 104 ; 105 for (int i = 0; i < system()->maxMasters(); i++) { 106 bytesInstRead.subname(i, system()->getMasterName(i)); 107 } 108 bytesWritten 109 .init(system()->maxMasters()) 110 .name(name() + ".bytes_written") 111 .desc("Number of bytes written to this memory") 112 .flags(total | nozero | nonan) 113 ; 114 for (int i = 0; i < system()->maxMasters(); i++) { 115 bytesWritten.subname(i, system()->getMasterName(i)); 116 } 117 numReads 118 .init(system()->maxMasters()) 119 .name(name() + ".num_reads") 120 .desc("Number of read requests responded to by this memory") 121 .flags(total | nozero | nonan) 122 ; 123 for (int i = 0; i < system()->maxMasters(); i++) { 124 numReads.subname(i, system()->getMasterName(i)); 125 } 126 numWrites 127 .init(system()->maxMasters()) 128 .name(name() + ".num_writes") 129 .desc("Number of write requests responded to by this memory") 130 .flags(total | nozero | nonan) 131 ; 132 for (int i = 0; i < system()->maxMasters(); i++) { 133 numWrites.subname(i, system()->getMasterName(i)); 134 } 135 numOther 136 .init(system()->maxMasters()) 137 .name(name() + ".num_other") 138 .desc("Number of other requests responded to by this memory") 139 .flags(total | nozero | nonan) 140 ; 141 for (int i = 0; i < system()->maxMasters(); i++) { 142 numOther.subname(i, system()->getMasterName(i)); 143 } 144 bwRead 145 .name(name() + ".bw_read") 146 .desc("Total read bandwidth from this memory (bytes/s)") 147 .precision(0) 148 .prereq(bytesRead) 149 .flags(total | nozero | nonan) 150 ; 151 for (int i = 0; i < system()->maxMasters(); i++) { 152 bwRead.subname(i, system()->getMasterName(i)); 153 } 154 155 bwInstRead 156 .name(name() + ".bw_inst_read") 157 .desc("Instruction read bandwidth from this memory (bytes/s)") 158 .precision(0) 159 .prereq(bytesInstRead) 160 .flags(total | nozero | nonan) 161 ; 162 for (int i = 0; i < system()->maxMasters(); i++) { 163 bwInstRead.subname(i, system()->getMasterName(i)); 164 } 165 bwWrite 166 .name(name() + ".bw_write") 167 .desc("Write bandwidth from this memory (bytes/s)") 168 .precision(0) 169 .prereq(bytesWritten) 170 .flags(total | nozero | nonan) 171 ; 172 for (int i = 0; i < system()->maxMasters(); i++) { 173 bwWrite.subname(i, system()->getMasterName(i)); 174 } 175 bwTotal 176 .name(name() + ".bw_total") 177 .desc("Total bandwidth to/from this memory (bytes/s)") 178 .precision(0) 179 .prereq(bwTotal) 180 .flags(total | nozero | nonan) 181 ; 182 for (int i = 0; i < system()->maxMasters(); i++) { 183 bwTotal.subname(i, system()->getMasterName(i)); 184 } 185 bwRead = bytesRead / simSeconds; 186 bwInstRead = bytesInstRead / simSeconds; 187 bwWrite = bytesWritten / simSeconds; 188 bwTotal = (bytesRead + bytesWritten) / simSeconds; 189} 190 191AddrRange 192AbstractMemory::getAddrRange() const 193{ 194 return range; 195} 196 197// Add load-locked to tracking list. Should only be called if the 198// operation is a load and the LLSC flag is set. 199void 200AbstractMemory::trackLoadLocked(PacketPtr pkt) 201{ 202 Request *req = pkt->req; 203 Addr paddr = LockedAddr::mask(req->getPaddr()); 204 205 // first we check if we already have a locked addr for this 206 // xc. Since each xc only gets one, we just update the 207 // existing record with the new address. 208 list<LockedAddr>::iterator i; 209 210 for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) { 211 if (i->matchesContext(req)) { 212 DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n", 213 req->contextId(), paddr); 214 i->addr = paddr; 215 return; 216 } 217 } 218 219 // no record for this xc: need to allocate a new one 220 DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n", 221 req->contextId(), paddr); 222 lockedAddrList.push_front(LockedAddr(req)); 223} 224 225 226// Called on *writes* only... both regular stores and 227// store-conditional operations. Check for conventional stores which 228// conflict with locked addresses, and for success/failure of store 229// conditionals. 230bool 231AbstractMemory::checkLockedAddrList(PacketPtr pkt) 232{ 233 Request *req = pkt->req; 234 Addr paddr = LockedAddr::mask(req->getPaddr()); 235 bool isLLSC = pkt->isLLSC(); 236 237 // Initialize return value. Non-conditional stores always 238 // succeed. Assume conditional stores will fail until proven 239 // otherwise. 240 bool allowStore = !isLLSC; 241 242 // Iterate over list. Note that there could be multiple matching records, 243 // as more than one context could have done a load locked to this location. 244 // Only remove records when we succeed in finding a record for (xc, addr); 245 // then, remove all records with this address. Failed store-conditionals do 246 // not blow unrelated reservations. 247 list<LockedAddr>::iterator i = lockedAddrList.begin(); 248 249 if (isLLSC) { 250 while (i != lockedAddrList.end()) { 251 if (i->addr == paddr && i->matchesContext(req)) { 252 // it's a store conditional, and as far as the memory system can 253 // tell, the requesting context's lock is still valid. 254 DPRINTF(LLSC, "StCond success: context %d addr %#x\n", 255 req->contextId(), paddr); 256 allowStore = true; 257 break; 258 } 259 // If we didn't find a match, keep searching! Someone else may well 260 // have a reservation on this line here but we may find ours in just 261 // a little while. 262 i++; 263 } 264 req->setExtraData(allowStore ? 1 : 0); 265 } 266 // LLSCs that succeeded AND non-LLSC stores both fall into here: 267 if (allowStore) { 268 // We write address paddr. However, there may be several entries with a 269 // reservation on this address (for other contextIds) and they must all 270 // be removed. 271 i = lockedAddrList.begin(); 272 while (i != lockedAddrList.end()) { 273 if (i->addr == paddr) { 274 DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n", 275 i->contextId, paddr); 276 ContextID owner_cid = i->contextId; 277 ContextID requester_cid = pkt->req->contextId(); 278 if (owner_cid != requester_cid) { 279 ThreadContext* ctx = system()->getThreadContext(owner_cid); 280 TheISA::globalClearExclusive(ctx); 281 } 282 i = lockedAddrList.erase(i); 283 } else { 284 i++; 285 } 286 } 287 } 288 289 return allowStore; 290} 291 292 293#if TRACING_ON 294 295#define CASE(A, T) \ 296 case sizeof(T): \ 297 DPRINTF(MemoryAccess,"%s from %s of size %i on address 0x%x data " \ 298 "0x%x %c\n", A, system()->getMasterName(pkt->req->masterId()),\ 299 pkt->getSize(), pkt->getAddr(), pkt->get<T>(), \ 300 pkt->req->isUncacheable() ? 'U' : 'C'); \ 301 break 302 303 304#define TRACE_PACKET(A) \ 305 do { \ 306 switch (pkt->getSize()) { \ 307 CASE(A, uint64_t); \ 308 CASE(A, uint32_t); \ 309 CASE(A, uint16_t); \ 310 CASE(A, uint8_t); \ 311 default: \ 312 DPRINTF(MemoryAccess, "%s from %s of size %i on address 0x%x %c\n",\ 313 A, system()->getMasterName(pkt->req->masterId()), \ 314 pkt->getSize(), pkt->getAddr(), \ 315 pkt->req->isUncacheable() ? 'U' : 'C'); \ 316 DDUMP(MemoryAccess, pkt->getConstPtr<uint8_t>(), pkt->getSize()); \ 317 } \ 318 } while (0) 319 320#else 321 322#define TRACE_PACKET(A) 323 324#endif 325 326void 327AbstractMemory::access(PacketPtr pkt) 328{ 329 if (pkt->cacheResponding()) { 330 DPRINTF(MemoryAccess, "Cache responding to %#llx: not responding\n", 331 pkt->getAddr()); 332 return; 333 } 334 335 if (pkt->cmd == MemCmd::CleanEvict || pkt->cmd == MemCmd::WritebackClean) { 336 DPRINTF(MemoryAccess, "CleanEvict on 0x%x: not responding\n", 337 pkt->getAddr()); 338 return; 339 } 340 341 assert(AddrRange(pkt->getAddr(), 342 pkt->getAddr() + (pkt->getSize() - 1)).isSubset(range)); 343 344 uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start(); 345 346 if (pkt->cmd == MemCmd::SwapReq) { 347 if (pkt->isAtomicOp()) { 348 if (pmemAddr) { 349 memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 350 (*(pkt->getAtomicOp()))(hostAddr); 351 } 352 } else { 353 std::vector<uint8_t> overwrite_val(pkt->getSize()); 354 uint64_t condition_val64; 355 uint32_t condition_val32; 356 357 if (!pmemAddr) 358 panic("Swap only works if there is real memory (i.e. null=False)"); 359 360 bool overwrite_mem = true; 361 // keep a copy of our possible write value, and copy what is at the 362 // memory address into the packet 363 std::memcpy(&overwrite_val[0], pkt->getConstPtr<uint8_t>(), 364 pkt->getSize()); 365 std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 366 367 if (pkt->req->isCondSwap()) { 368 if (pkt->getSize() == sizeof(uint64_t)) { 369 condition_val64 = pkt->req->getExtraData(); 370 overwrite_mem = !std::memcmp(&condition_val64, hostAddr, 371 sizeof(uint64_t)); 372 } else if (pkt->getSize() == sizeof(uint32_t)) { 373 condition_val32 = (uint32_t)pkt->req->getExtraData(); 374 overwrite_mem = !std::memcmp(&condition_val32, hostAddr, 375 sizeof(uint32_t)); 376 } else 377 panic("Invalid size for conditional read/write\n"); 378 } 379 380 if (overwrite_mem) 381 std::memcpy(hostAddr, &overwrite_val[0], pkt->getSize()); 382 383 assert(!pkt->req->isInstFetch()); 384 TRACE_PACKET("Read/Write"); 385 numOther[pkt->req->masterId()]++; 386 } 387 } else if (pkt->isRead()) { 388 assert(!pkt->isWrite()); 389 if (pkt->isLLSC()) { 390 assert(!pkt->fromCache()); 391 // if the packet is not coming from a cache then we have 392 // to do the LL/SC tracking here 393 trackLoadLocked(pkt); 394 } 395 if (pmemAddr) 396 memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 397 TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read"); 398 numReads[pkt->req->masterId()]++; 399 bytesRead[pkt->req->masterId()] += pkt->getSize(); 400 if (pkt->req->isInstFetch()) 401 bytesInstRead[pkt->req->masterId()] += pkt->getSize(); 402 } else if (pkt->isInvalidate()) { 403 // no need to do anything 404 // this clause is intentionally before the write clause: the only 405 // transaction that is both a write and an invalidate is 406 // WriteInvalidate, and for the sake of consistency, it does not 407 // write to memory. in a cacheless system, there are no WriteInv's 408 // because the Write -> WriteInvalidate rewrite happens in the cache. 409 } else if (pkt->isWrite()) { 410 if (writeOK(pkt)) { 411 if (pmemAddr) { 412 memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize()); 413 DPRINTF(MemoryAccess, "%s wrote %i bytes to address %x\n", 414 __func__, pkt->getSize(), pkt->getAddr()); 415 } 416 assert(!pkt->req->isInstFetch()); 417 TRACE_PACKET("Write"); 418 numWrites[pkt->req->masterId()]++; 419 bytesWritten[pkt->req->masterId()] += pkt->getSize(); 420 } 421 } else { 422 panic("unimplemented"); 423 } 424 425 if (pkt->needsResponse()) { 426 pkt->makeResponse(); 427 } 428} 429 430void 431AbstractMemory::functionalAccess(PacketPtr pkt) 432{ 433 assert(AddrRange(pkt->getAddr(), 434 pkt->getAddr() + pkt->getSize() - 1).isSubset(range)); 435 436 uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start(); 437 438 if (pkt->isRead()) { 439 if (pmemAddr) 440 memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 441 TRACE_PACKET("Read"); 442 pkt->makeResponse(); 443 } else if (pkt->isWrite()) { 444 if (pmemAddr) 445 memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize()); 446 TRACE_PACKET("Write"); 447 pkt->makeResponse(); 448 } else if (pkt->isPrint()) { 449 Packet::PrintReqState *prs = 450 dynamic_cast<Packet::PrintReqState*>(pkt->senderState); 451 assert(prs); 452 // Need to call printLabels() explicitly since we're not going 453 // through printObj(). 454 prs->printLabels(); 455 // Right now we just print the single byte at the specified address. 456 ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *hostAddr); 457 } else { 458 panic("AbstractMemory: unimplemented functional command %s", 459 pkt->cmdString()); 460 } 461} 462