abstract_mem.cc revision 8992
12391SN/A/*
28931Sandreas.hansson@arm.com * Copyright (c) 2010-2012 ARM Limited
37733SN/A * All rights reserved
47733SN/A *
57733SN/A * The license below extends only to copyright in the software and shall
67733SN/A * not be construed as granting a license to any other intellectual
77733SN/A * property including but not limited to intellectual property relating
87733SN/A * to a hardware implementation of the functionality of the software
97733SN/A * licensed hereunder.  You may use the software subject to the license
107733SN/A * terms below provided that you ensure that this notice is replicated
117733SN/A * unmodified and in its entirety in all distributions of the software,
127733SN/A * modified or unmodified, in source code or in binary form.
137733SN/A *
142391SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan
152391SN/A * All rights reserved.
162391SN/A *
172391SN/A * Redistribution and use in source and binary forms, with or without
182391SN/A * modification, are permitted provided that the following conditions are
192391SN/A * met: redistributions of source code must retain the above copyright
202391SN/A * notice, this list of conditions and the following disclaimer;
212391SN/A * redistributions in binary form must reproduce the above copyright
222391SN/A * notice, this list of conditions and the following disclaimer in the
232391SN/A * documentation and/or other materials provided with the distribution;
242391SN/A * neither the name of the copyright holders nor the names of its
252391SN/A * contributors may be used to endorse or promote products derived from
262391SN/A * this software without specific prior written permission.
272391SN/A *
282391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352391SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362391SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392665SN/A *
402665SN/A * Authors: Ron Dreslinski
412914SN/A *          Ali Saidi
428931Sandreas.hansson@arm.com *          Andreas Hansson
432391SN/A */
442391SN/A
458229SN/A#include <sys/mman.h>
462391SN/A#include <sys/types.h>
477730SN/A#include <sys/user.h>
482391SN/A#include <fcntl.h>
492391SN/A#include <unistd.h>
502391SN/A#include <zlib.h>
512391SN/A
528229SN/A#include <cerrno>
536712SN/A#include <cstdio>
542391SN/A#include <iostream>
552391SN/A#include <string>
562391SN/A
576329SN/A#include "arch/registers.hh"
586658SN/A#include "config/the_isa.hh"
598232SN/A#include "debug/LLSC.hh"
608232SN/A#include "debug/MemoryAccess.hh"
618931Sandreas.hansson@arm.com#include "mem/abstract_mem.hh"
623879SN/A#include "mem/packet_access.hh"
632394SN/A
642391SN/Ausing namespace std;
652391SN/A
668931Sandreas.hansson@arm.comAbstractMemory::AbstractMemory(const Params *p) :
678931Sandreas.hansson@arm.com    MemObject(p), range(params()->range), pmemAddr(NULL),
688931Sandreas.hansson@arm.com    confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map)
692391SN/A{
707730SN/A    if (size() % TheISA::PageBytes != 0)
712391SN/A        panic("Memory Size not divisible by page size\n");
722391SN/A
735477SN/A    if (params()->null)
745477SN/A        return;
755477SN/A
767730SN/A    if (params()->file == "") {
777730SN/A        int map_flags = MAP_ANON | MAP_PRIVATE;
787730SN/A        pmemAddr = (uint8_t *)mmap(NULL, size(),
797730SN/A                                   PROT_READ | PROT_WRITE, map_flags, -1, 0);
807730SN/A    } else {
817730SN/A        int map_flags = MAP_PRIVATE;
827730SN/A        int fd = open(params()->file.c_str(), O_RDONLY);
838931Sandreas.hansson@arm.com        long _size = lseek(fd, 0, SEEK_END);
848931Sandreas.hansson@arm.com        if (_size != range.size()) {
858931Sandreas.hansson@arm.com            warn("Specified size %d does not match file %s %d\n", range.size(),
868931Sandreas.hansson@arm.com                 params()->file, _size);
878931Sandreas.hansson@arm.com            range = RangeSize(range.start, _size);
888931Sandreas.hansson@arm.com        }
897730SN/A        lseek(fd, 0, SEEK_SET);
908931Sandreas.hansson@arm.com        pmemAddr = (uint8_t *)mmap(NULL, roundUp(_size, sysconf(_SC_PAGESIZE)),
917730SN/A                                   PROT_READ | PROT_WRITE, map_flags, fd, 0);
927730SN/A    }
932391SN/A
943012SN/A    if (pmemAddr == (void *)MAP_FAILED) {
952391SN/A        perror("mmap");
967730SN/A        if (params()->file == "")
977730SN/A            fatal("Could not mmap!\n");
987730SN/A        else
997730SN/A            fatal("Could not find file: %s\n", params()->file);
1002391SN/A    }
1012391SN/A
1023751SN/A    //If requested, initialize all the memory to 0
1034762SN/A    if (p->zero)
1047730SN/A        memset(pmemAddr, 0, size());
1052391SN/A}
1062391SN/A
1072541SN/A
1088931Sandreas.hansson@arm.comAbstractMemory::~AbstractMemory()
1092391SN/A{
1103012SN/A    if (pmemAddr)
1117730SN/A        munmap((char*)pmemAddr, size());
1122391SN/A}
1132391SN/A
1148719SN/Avoid
1158931Sandreas.hansson@arm.comAbstractMemory::regStats()
1168719SN/A{
1178719SN/A    using namespace Stats;
1188719SN/A
1198719SN/A    bytesRead
1208719SN/A        .name(name() + ".bytes_read")
1218719SN/A        .desc("Number of bytes read from this memory")
1228719SN/A        ;
1238719SN/A    bytesInstRead
1248719SN/A        .name(name() + ".bytes_inst_read")
1258719SN/A        .desc("Number of instructions bytes read from this memory")
1268719SN/A        ;
1278719SN/A    bytesWritten
1288719SN/A        .name(name() + ".bytes_written")
1298719SN/A        .desc("Number of bytes written to this memory")
1308719SN/A        ;
1318719SN/A    numReads
1328719SN/A        .name(name() + ".num_reads")
1338719SN/A        .desc("Number of read requests responded to by this memory")
1348719SN/A        ;
1358719SN/A    numWrites
1368719SN/A        .name(name() + ".num_writes")
1378719SN/A        .desc("Number of write requests responded to by this memory")
1388719SN/A        ;
1398719SN/A    numOther
1408719SN/A        .name(name() + ".num_other")
1418719SN/A        .desc("Number of other requests responded to by this memory")
1428719SN/A        ;
1438719SN/A    bwRead
1448719SN/A        .name(name() + ".bw_read")
1458719SN/A        .desc("Total read bandwidth from this memory (bytes/s)")
1468719SN/A        .precision(0)
1478719SN/A        .prereq(bytesRead)
1488719SN/A        ;
1498719SN/A    bwInstRead
1508719SN/A        .name(name() + ".bw_inst_read")
1518719SN/A        .desc("Instruction read bandwidth from this memory (bytes/s)")
1528719SN/A        .precision(0)
1538719SN/A        .prereq(bytesInstRead)
1548719SN/A        ;
1558719SN/A    bwWrite
1568719SN/A        .name(name() + ".bw_write")
1578719SN/A        .desc("Write bandwidth from this memory (bytes/s)")
1588719SN/A        .precision(0)
1598719SN/A        .prereq(bytesWritten)
1608719SN/A        ;
1618719SN/A    bwTotal
1628719SN/A        .name(name() + ".bw_total")
1638719SN/A        .desc("Total bandwidth to/from this memory (bytes/s)")
1648719SN/A        .precision(0)
1658719SN/A        .prereq(bwTotal)
1668719SN/A        ;
1678719SN/A    bwRead = bytesRead / simSeconds;
1688719SN/A    bwInstRead = bytesInstRead / simSeconds;
1698719SN/A    bwWrite = bytesWritten / simSeconds;
1708719SN/A    bwTotal = (bytesRead + bytesWritten) / simSeconds;
1718719SN/A}
1728719SN/A
1738931Sandreas.hansson@arm.comRange<Addr>
1748931Sandreas.hansson@arm.comAbstractMemory::getAddrRange()
1752408SN/A{
1768931Sandreas.hansson@arm.com    return range;
1772408SN/A}
1782408SN/A
1793170SN/A// Add load-locked to tracking list.  Should only be called if the
1806076SN/A// operation is a load and the LLSC flag is set.
1813170SN/Avoid
1828931Sandreas.hansson@arm.comAbstractMemory::trackLoadLocked(PacketPtr pkt)
1833170SN/A{
1844626SN/A    Request *req = pkt->req;
1853170SN/A    Addr paddr = LockedAddr::mask(req->getPaddr());
1863170SN/A
1873170SN/A    // first we check if we already have a locked addr for this
1883170SN/A    // xc.  Since each xc only gets one, we just update the
1893170SN/A    // existing record with the new address.
1903170SN/A    list<LockedAddr>::iterator i;
1913170SN/A
1923170SN/A    for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) {
1933170SN/A        if (i->matchesContext(req)) {
1945714SN/A            DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n",
1955714SN/A                    req->contextId(), paddr);
1963170SN/A            i->addr = paddr;
1973170SN/A            return;
1983170SN/A        }
1993170SN/A    }
2003170SN/A
2013170SN/A    // no record for this xc: need to allocate a new one
2025714SN/A    DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n",
2035714SN/A            req->contextId(), paddr);
2043170SN/A    lockedAddrList.push_front(LockedAddr(req));
2053170SN/A}
2063170SN/A
2073170SN/A
2083170SN/A// Called on *writes* only... both regular stores and
2093170SN/A// store-conditional operations.  Check for conventional stores which
2103170SN/A// conflict with locked addresses, and for success/failure of store
2113170SN/A// conditionals.
2123170SN/Abool
2138931Sandreas.hansson@arm.comAbstractMemory::checkLockedAddrList(PacketPtr pkt)
2143170SN/A{
2154626SN/A    Request *req = pkt->req;
2163170SN/A    Addr paddr = LockedAddr::mask(req->getPaddr());
2176102SN/A    bool isLLSC = pkt->isLLSC();
2183170SN/A
2193170SN/A    // Initialize return value.  Non-conditional stores always
2203170SN/A    // succeed.  Assume conditional stores will fail until proven
2213170SN/A    // otherwise.
2226102SN/A    bool success = !isLLSC;
2233170SN/A
2243170SN/A    // Iterate over list.  Note that there could be multiple matching
2253170SN/A    // records, as more than one context could have done a load locked
2263170SN/A    // to this location.
2273170SN/A    list<LockedAddr>::iterator i = lockedAddrList.begin();
2283170SN/A
2293170SN/A    while (i != lockedAddrList.end()) {
2303170SN/A
2313170SN/A        if (i->addr == paddr) {
2323170SN/A            // we have a matching address
2333170SN/A
2346102SN/A            if (isLLSC && i->matchesContext(req)) {
2353170SN/A                // it's a store conditional, and as far as the memory
2363170SN/A                // system can tell, the requesting context's lock is
2373170SN/A                // still valid.
2385714SN/A                DPRINTF(LLSC, "StCond success: context %d addr %#x\n",
2395714SN/A                        req->contextId(), paddr);
2403170SN/A                success = true;
2413170SN/A            }
2423170SN/A
2433170SN/A            // Get rid of our record of this lock and advance to next
2445714SN/A            DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
2455714SN/A                    i->contextId, paddr);
2463170SN/A            i = lockedAddrList.erase(i);
2473170SN/A        }
2483170SN/A        else {
2493170SN/A            // no match: advance to next record
2503170SN/A            ++i;
2513170SN/A        }
2523170SN/A    }
2533170SN/A
2546102SN/A    if (isLLSC) {
2554040SN/A        req->setExtraData(success ? 1 : 0);
2563170SN/A    }
2573170SN/A
2583170SN/A    return success;
2593170SN/A}
2603170SN/A
2614626SN/A
2624626SN/A#if TRACING_ON
2634626SN/A
2644626SN/A#define CASE(A, T)                                                      \
2654626SN/A  case sizeof(T):                                                       \
2666429SN/A    DPRINTF(MemoryAccess,"%s of size %i on address 0x%x data 0x%x\n",   \
2676429SN/A            A, pkt->getSize(), pkt->getAddr(), pkt->get<T>());          \
2684626SN/A  break
2694626SN/A
2704626SN/A
2714626SN/A#define TRACE_PACKET(A)                                                 \
2724626SN/A    do {                                                                \
2734626SN/A        switch (pkt->getSize()) {                                       \
2744626SN/A          CASE(A, uint64_t);                                            \
2754626SN/A          CASE(A, uint32_t);                                            \
2764626SN/A          CASE(A, uint16_t);                                            \
2774626SN/A          CASE(A, uint8_t);                                             \
2784626SN/A          default:                                                      \
2796429SN/A            DPRINTF(MemoryAccess, "%s of size %i on address 0x%x\n",    \
2806429SN/A                    A, pkt->getSize(), pkt->getAddr());                 \
2818077SN/A            DDUMP(MemoryAccess, pkt->getPtr<uint8_t>(), pkt->getSize());\
2824626SN/A        }                                                               \
2834626SN/A    } while (0)
2844626SN/A
2854626SN/A#else
2864626SN/A
2874626SN/A#define TRACE_PACKET(A)
2884626SN/A
2894626SN/A#endif
2904626SN/A
2918931Sandreas.hansson@arm.comvoid
2928931Sandreas.hansson@arm.comAbstractMemory::access(PacketPtr pkt)
2932413SN/A{
2948931Sandreas.hansson@arm.com    assert(pkt->getAddr() >= range.start &&
2958931Sandreas.hansson@arm.com           (pkt->getAddr() + pkt->getSize() - 1) <= range.end);
2962414SN/A
2974626SN/A    if (pkt->memInhibitAsserted()) {
2984626SN/A        DPRINTF(MemoryAccess, "mem inhibited on 0x%x: not responding\n",
2994626SN/A                pkt->getAddr());
3008931Sandreas.hansson@arm.com        return;
3013175SN/A    }
3024626SN/A
3038931Sandreas.hansson@arm.com    uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start;
3044626SN/A
3054626SN/A    if (pkt->cmd == MemCmd::SwapReq) {
3068931Sandreas.hansson@arm.com        TheISA::IntReg overwrite_val;
3074040SN/A        bool overwrite_mem;
3084040SN/A        uint64_t condition_val64;
3094040SN/A        uint32_t condition_val32;
3104040SN/A
3115477SN/A        if (!pmemAddr)
3125477SN/A            panic("Swap only works if there is real memory (i.e. null=False)");
3138931Sandreas.hansson@arm.com        assert(sizeof(TheISA::IntReg) >= pkt->getSize());
3144040SN/A
3154040SN/A        overwrite_mem = true;
3164040SN/A        // keep a copy of our possible write value, and copy what is at the
3174040SN/A        // memory address into the packet
3184052SN/A        std::memcpy(&overwrite_val, pkt->getPtr<uint8_t>(), pkt->getSize());
3194626SN/A        std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
3204040SN/A
3214040SN/A        if (pkt->req->isCondSwap()) {
3224040SN/A            if (pkt->getSize() == sizeof(uint64_t)) {
3234052SN/A                condition_val64 = pkt->req->getExtraData();
3244626SN/A                overwrite_mem = !std::memcmp(&condition_val64, hostAddr,
3254626SN/A                                             sizeof(uint64_t));
3264040SN/A            } else if (pkt->getSize() == sizeof(uint32_t)) {
3274052SN/A                condition_val32 = (uint32_t)pkt->req->getExtraData();
3284626SN/A                overwrite_mem = !std::memcmp(&condition_val32, hostAddr,
3294626SN/A                                             sizeof(uint32_t));
3304040SN/A            } else
3314040SN/A                panic("Invalid size for conditional read/write\n");
3324040SN/A        }
3334040SN/A
3344040SN/A        if (overwrite_mem)
3354626SN/A            std::memcpy(hostAddr, &overwrite_val, pkt->getSize());
3364040SN/A
3376429SN/A        assert(!pkt->req->isInstFetch());
3384626SN/A        TRACE_PACKET("Read/Write");
3398719SN/A        numOther++;
3404626SN/A    } else if (pkt->isRead()) {
3414626SN/A        assert(!pkt->isWrite());
3426102SN/A        if (pkt->isLLSC()) {
3434626SN/A            trackLoadLocked(pkt);
3444040SN/A        }
3455477SN/A        if (pmemAddr)
3465477SN/A            memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
3476429SN/A        TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
3488719SN/A        numReads++;
3498719SN/A        bytesRead += pkt->getSize();
3508719SN/A        if (pkt->req->isInstFetch())
3518719SN/A            bytesInstRead += pkt->getSize();
3524626SN/A    } else if (pkt->isWrite()) {
3534626SN/A        if (writeOK(pkt)) {
3545477SN/A            if (pmemAddr)
3555477SN/A                memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize());
3566429SN/A            assert(!pkt->req->isInstFetch());
3574626SN/A            TRACE_PACKET("Write");
3588719SN/A            numWrites++;
3598719SN/A            bytesWritten += pkt->getSize();
3604626SN/A        }
3614626SN/A    } else if (pkt->isInvalidate()) {
3628931Sandreas.hansson@arm.com        // no need to do anything
3634040SN/A    } else {
3642413SN/A        panic("unimplemented");
3652413SN/A    }
3662420SN/A
3674626SN/A    if (pkt->needsResponse()) {
3688931Sandreas.hansson@arm.com        pkt->makeResponse();
3694626SN/A    }
3702413SN/A}
3712413SN/A
3728931Sandreas.hansson@arm.comvoid
3738931Sandreas.hansson@arm.comAbstractMemory::functionalAccess(PacketPtr pkt)
3748931Sandreas.hansson@arm.com{
3758931Sandreas.hansson@arm.com    assert(pkt->getAddr() >= range.start &&
3768931Sandreas.hansson@arm.com           (pkt->getAddr() + pkt->getSize() - 1) <= range.end);
3774626SN/A
3788931Sandreas.hansson@arm.com    uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start;
3794626SN/A
3805314SN/A    if (pkt->isRead()) {
3815477SN/A        if (pmemAddr)
3825477SN/A            memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
3834626SN/A        TRACE_PACKET("Read");
3848931Sandreas.hansson@arm.com        pkt->makeResponse();
3855314SN/A    } else if (pkt->isWrite()) {
3865477SN/A        if (pmemAddr)
3875477SN/A            memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize());
3884626SN/A        TRACE_PACKET("Write");
3898931Sandreas.hansson@arm.com        pkt->makeResponse();
3905314SN/A    } else if (pkt->isPrint()) {
3915315SN/A        Packet::PrintReqState *prs =
3925315SN/A            dynamic_cast<Packet::PrintReqState*>(pkt->senderState);
3938992SAli.Saidi@ARM.com        assert(prs);
3945315SN/A        // Need to call printLabels() explicitly since we're not going
3955315SN/A        // through printObj().
3965314SN/A        prs->printLabels();
3975315SN/A        // Right now we just print the single byte at the specified address.
3985314SN/A        ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *hostAddr);
3994626SN/A    } else {
4008931Sandreas.hansson@arm.com        panic("AbstractMemory: unimplemented functional command %s",
4014626SN/A              pkt->cmdString());
4024626SN/A    }
4034490SN/A}
4044490SN/A
4052413SN/Avoid
4068931Sandreas.hansson@arm.comAbstractMemory::serialize(ostream &os)
4072391SN/A{
4085477SN/A    if (!pmemAddr)
4095477SN/A        return;
4105477SN/A
4112391SN/A    gzFile compressedMem;
4122391SN/A    string filename = name() + ".physmem";
4138931Sandreas.hansson@arm.com    long _size = range.size();
4142391SN/A
4152391SN/A    SERIALIZE_SCALAR(filename);
4167730SN/A    SERIALIZE_SCALAR(_size);
4172391SN/A
4182391SN/A    // write memory file
4192391SN/A    string thefile = Checkpoint::dir() + "/" + filename.c_str();
4202391SN/A    int fd = creat(thefile.c_str(), 0664);
4212391SN/A    if (fd < 0) {
4222391SN/A        perror("creat");
4232391SN/A        fatal("Can't open physical memory checkpoint file '%s'\n", filename);
4242391SN/A    }
4252391SN/A
4262391SN/A    compressedMem = gzdopen(fd, "wb");
4272391SN/A    if (compressedMem == NULL)
4282391SN/A        fatal("Insufficient memory to allocate compression state for %s\n",
4292391SN/A                filename);
4302391SN/A
4317730SN/A    if (gzwrite(compressedMem, pmemAddr, size()) != (int)size()) {
4322391SN/A        fatal("Write failed on physical memory checkpoint file '%s'\n",
4332391SN/A              filename);
4342391SN/A    }
4352391SN/A
4362391SN/A    if (gzclose(compressedMem))
4372391SN/A        fatal("Close failed on physical memory checkpoint file '%s'\n",
4382391SN/A              filename);
4397733SN/A
4407733SN/A    list<LockedAddr>::iterator i = lockedAddrList.begin();
4417733SN/A
4427733SN/A    vector<Addr> lal_addr;
4437733SN/A    vector<int> lal_cid;
4447733SN/A    while (i != lockedAddrList.end()) {
4457733SN/A        lal_addr.push_back(i->addr);
4467733SN/A        lal_cid.push_back(i->contextId);
4477733SN/A        i++;
4487733SN/A    }
4497733SN/A    arrayParamOut(os, "lal_addr", lal_addr);
4507733SN/A    arrayParamOut(os, "lal_cid", lal_cid);
4512391SN/A}
4522391SN/A
4532391SN/Avoid
4548931Sandreas.hansson@arm.comAbstractMemory::unserialize(Checkpoint *cp, const string &section)
4552391SN/A{
4565477SN/A    if (!pmemAddr)
4575477SN/A        return;
4585477SN/A
4592391SN/A    gzFile compressedMem;
4602391SN/A    long *tempPage;
4612391SN/A    long *pmem_current;
4622391SN/A    uint64_t curSize;
4632391SN/A    uint32_t bytesRead;
4646227SN/A    const uint32_t chunkSize = 16384;
4652391SN/A
4662391SN/A    string filename;
4672391SN/A
4682391SN/A    UNSERIALIZE_SCALAR(filename);
4692391SN/A
4702391SN/A    filename = cp->cptDir + "/" + filename;
4712391SN/A
4722391SN/A    // mmap memoryfile
4732391SN/A    int fd = open(filename.c_str(), O_RDONLY);
4742391SN/A    if (fd < 0) {
4752391SN/A        perror("open");
4762391SN/A        fatal("Can't open physical memory checkpoint file '%s'", filename);
4772391SN/A    }
4782391SN/A
4792391SN/A    compressedMem = gzdopen(fd, "rb");
4802391SN/A    if (compressedMem == NULL)
4812391SN/A        fatal("Insufficient memory to allocate compression state for %s\n",
4822391SN/A                filename);
4832391SN/A
4848105SN/A    // unmap file that was mmapped in the constructor
4853012SN/A    // This is done here to make sure that gzip and open don't muck with our
4863012SN/A    // nice large space of memory before we reallocate it
4877730SN/A    munmap((char*)pmemAddr, size());
4882391SN/A
4898931Sandreas.hansson@arm.com    long _size;
4907730SN/A    UNSERIALIZE_SCALAR(_size);
4918931Sandreas.hansson@arm.com    if (_size > params()->range.size())
4928636SN/A        fatal("Memory size has changed! size %lld, param size %lld\n",
4938931Sandreas.hansson@arm.com              _size, params()->range.size());
4947730SN/A
4957730SN/A    pmemAddr = (uint8_t *)mmap(NULL, size(),
4964762SN/A        PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
4972391SN/A
4983012SN/A    if (pmemAddr == (void *)MAP_FAILED) {
4992391SN/A        perror("mmap");
5002391SN/A        fatal("Could not mmap physical memory!\n");
5012391SN/A    }
5022391SN/A
5032391SN/A    curSize = 0;
5042391SN/A    tempPage = (long*)malloc(chunkSize);
5052391SN/A    if (tempPage == NULL)
5062391SN/A        fatal("Unable to malloc memory to read file %s\n", filename);
5072391SN/A
5082391SN/A    /* Only copy bytes that are non-zero, so we don't give the VM system hell */
5097730SN/A    while (curSize < size()) {
5102391SN/A        bytesRead = gzread(compressedMem, tempPage, chunkSize);
5116820SN/A        if (bytesRead == 0)
5126820SN/A            break;
5132391SN/A
5142391SN/A        assert(bytesRead % sizeof(long) == 0);
5152391SN/A
5166227SN/A        for (uint32_t x = 0; x < bytesRead / sizeof(long); x++)
5172391SN/A        {
5182391SN/A             if (*(tempPage+x) != 0) {
5193012SN/A                 pmem_current = (long*)(pmemAddr + curSize + x * sizeof(long));
5202391SN/A                 *pmem_current = *(tempPage+x);
5212391SN/A             }
5222391SN/A        }
5232391SN/A        curSize += bytesRead;
5242391SN/A    }
5252391SN/A
5262391SN/A    free(tempPage);
5272391SN/A
5282391SN/A    if (gzclose(compressedMem))
5292391SN/A        fatal("Close failed on physical memory checkpoint file '%s'\n",
5302391SN/A              filename);
5312391SN/A
5327733SN/A    vector<Addr> lal_addr;
5337733SN/A    vector<int> lal_cid;
5347733SN/A    arrayParamIn(cp, section, "lal_addr", lal_addr);
5357733SN/A    arrayParamIn(cp, section, "lal_cid", lal_cid);
5367733SN/A    for(int i = 0; i < lal_addr.size(); i++)
5377733SN/A        lockedAddrList.push_front(LockedAddr(lal_addr[i], lal_cid[i]));
5382391SN/A}
539