abstract_mem.cc revision 6102
13170Sstever@eecs.umich.edu/*
29383SAli.Saidi@ARM.com * Copyright (c) 2001-2005 The Regents of The University of Michigan
39383SAli.Saidi@ARM.com * All rights reserved.
49383SAli.Saidi@ARM.com *
59383SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without
69383SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are
79383SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright
89383SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer;
99383SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright
109383SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the
119383SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution;
129383SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its
139383SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from
145254Sksewell@umich.edu * this software without specific prior written permission.
155254Sksewell@umich.edu *
163170Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
175254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
185254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
195254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
205254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
215254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
225254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
235254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
245254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
255254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
265254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
273170Sstever@eecs.umich.edu *
285254Sksewell@umich.edu * Authors: Ron Dreslinski
295254Sksewell@umich.edu *          Ali Saidi
305254Sksewell@umich.edu */
315254Sksewell@umich.edu
325254Sksewell@umich.edu#include <sys/types.h>
335254Sksewell@umich.edu#include <sys/mman.h>
345254Sksewell@umich.edu#include <errno.h>
355254Sksewell@umich.edu#include <fcntl.h>
365254Sksewell@umich.edu#include <unistd.h>
375254Sksewell@umich.edu#include <zlib.h>
385254Sksewell@umich.edu
393170Sstever@eecs.umich.edu#include <iostream>
405254Sksewell@umich.edu#include <string>
413170Sstever@eecs.umich.edu
423170Sstever@eecs.umich.edu#include "arch/isa_traits.hh"
433170Sstever@eecs.umich.edu#include "base/misc.hh"
443170Sstever@eecs.umich.edu#include "base/random.hh"
453170Sstever@eecs.umich.edu#include "config/full_system.hh"
463170Sstever@eecs.umich.edu#include "mem/packet_access.hh"
473170Sstever@eecs.umich.edu#include "mem/physical.hh"
483170Sstever@eecs.umich.edu#include "sim/eventq.hh"
493170Sstever@eecs.umich.edu#include "sim/host.hh"
503170Sstever@eecs.umich.edu
513170Sstever@eecs.umich.eduusing namespace std;
526329Sgblack@eecs.umich.eduusing namespace TheISA;
534661Sksewell@umich.edu
544661Sksewell@umich.eduPhysicalMemory::PhysicalMemory(const Params *p)
558232Snate@binkert.org    : MemObject(p), pmemAddr(NULL), pagePtr(0),
569383SAli.Saidi@ARM.com      lat(p->latency), lat_var(p->latency_var),
573170Sstever@eecs.umich.edu      cachedSize(params()->range.size()), cachedStart(params()->range.start)
583170Sstever@eecs.umich.edu{
593170Sstever@eecs.umich.edu    if (params()->range.size() % TheISA::PageBytes != 0)
603170Sstever@eecs.umich.edu        panic("Memory Size not divisible by page size\n");
619383SAli.Saidi@ARM.com
629383SAli.Saidi@ARM.com    if (params()->null)
639383SAli.Saidi@ARM.com        return;
649383SAli.Saidi@ARM.com
659383SAli.Saidi@ARM.com    int map_flags = MAP_ANON | MAP_PRIVATE;
669383SAli.Saidi@ARM.com    pmemAddr = (uint8_t *)mmap(NULL, params()->range.size(),
679383SAli.Saidi@ARM.com                               PROT_READ | PROT_WRITE, map_flags, -1, 0);
689383SAli.Saidi@ARM.com
699383SAli.Saidi@ARM.com    if (pmemAddr == (void *)MAP_FAILED) {
709383SAli.Saidi@ARM.com        perror("mmap");
719383SAli.Saidi@ARM.com        fatal("Could not mmap!\n");
729383SAli.Saidi@ARM.com    }
739383SAli.Saidi@ARM.com
749383SAli.Saidi@ARM.com    //If requested, initialize all the memory to 0
759383SAli.Saidi@ARM.com    if (p->zero)
769383SAli.Saidi@ARM.com        memset(pmemAddr, 0, p->range.size());
776378Sgblack@eecs.umich.edu}
783170Sstever@eecs.umich.edu
793170Sstever@eecs.umich.eduvoid
803170Sstever@eecs.umich.eduPhysicalMemory::init()
813170Sstever@eecs.umich.edu{
827783SGiacomo.Gabrielli@arm.com    if (ports.size() == 0) {
837783SGiacomo.Gabrielli@arm.com        fatal("PhysicalMemory object %s is unconnected!", name());
846378Sgblack@eecs.umich.edu    }
856378Sgblack@eecs.umich.edu
865715Shsul@eecs.umich.edu    for (PortIterator pi = ports.begin(); pi != ports.end(); ++pi) {
873170Sstever@eecs.umich.edu        if (*pi)
883170Sstever@eecs.umich.edu            (*pi)->sendStatusChange(Port::RangeChange);
893170Sstever@eecs.umich.edu    }
9010030SAli.Saidi@ARM.com}
9110030SAli.Saidi@ARM.com
9210030SAli.Saidi@ARM.comPhysicalMemory::~PhysicalMemory()
9310030SAli.Saidi@ARM.com{
9410030SAli.Saidi@ARM.com    if (pmemAddr)
9510030SAli.Saidi@ARM.com        munmap((char*)pmemAddr, params()->range.size());
963170Sstever@eecs.umich.edu    //Remove memPorts?
9710030SAli.Saidi@ARM.com}
983170Sstever@eecs.umich.edu
994661Sksewell@umich.eduAddr
1004661Sksewell@umich.eduPhysicalMemory::new_page()
1014661Sksewell@umich.edu{
1024661Sksewell@umich.edu    Addr return_addr = pagePtr << LogVMPageSize;
1034661Sksewell@umich.edu    return_addr += start();
1044661Sksewell@umich.edu
1057783SGiacomo.Gabrielli@arm.com    ++pagePtr;
1067783SGiacomo.Gabrielli@arm.com    return return_addr;
1074661Sksewell@umich.edu}
1084661Sksewell@umich.edu
1094661Sksewell@umich.eduint
1104661Sksewell@umich.eduPhysicalMemory::deviceBlockSize()
1114661Sksewell@umich.edu{
1127783SGiacomo.Gabrielli@arm.com    //Can accept anysize request
1134661Sksewell@umich.edu    return 0;
1144661Sksewell@umich.edu}
1154661Sksewell@umich.edu
1164661Sksewell@umich.eduTick
1174661Sksewell@umich.eduPhysicalMemory::calculateLatency(PacketPtr pkt)
1184661Sksewell@umich.edu{
1194661Sksewell@umich.edu    Tick latency = lat;
1204661Sksewell@umich.edu    if (lat_var != 0)
1216425Sksewell@umich.edu        latency += random_mt.random<Tick>(0, lat_var);
1225714Shsul@eecs.umich.edu    return latency;
1234661Sksewell@umich.edu}
1247823Ssteve.reinhardt@amd.com
1254661Sksewell@umich.edu
1264661Sksewell@umich.edu
1274661Sksewell@umich.edu// Add load-locked to tracking list.  Should only be called if the
1286378Sgblack@eecs.umich.edu// operation is a load and the LLSC flag is set.
1296378Sgblack@eecs.umich.eduvoid
1305715Shsul@eecs.umich.eduPhysicalMemory::trackLoadLocked(PacketPtr pkt)
1314661Sksewell@umich.edu{
1326378Sgblack@eecs.umich.edu    Request *req = pkt->req;
1336378Sgblack@eecs.umich.edu    Addr paddr = LockedAddr::mask(req->getPaddr());
1345715Shsul@eecs.umich.edu
1354661Sksewell@umich.edu    // first we check if we already have a locked addr for this
1364661Sksewell@umich.edu    // xc.  Since each xc only gets one, we just update the
1374661Sksewell@umich.edu    // existing record with the new address.
1384661Sksewell@umich.edu    list<LockedAddr>::iterator i;
1394661Sksewell@umich.edu
1404661Sksewell@umich.edu    for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) {
1413170Sstever@eecs.umich.edu        if (i->matchesContext(req)) {
1423170Sstever@eecs.umich.edu            DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n",
1433170Sstever@eecs.umich.edu                    req->contextId(), paddr);
1443170Sstever@eecs.umich.edu            i->addr = paddr;
1453170Sstever@eecs.umich.edu            return;
1463170Sstever@eecs.umich.edu        }
147    }
148
149    // no record for this xc: need to allocate a new one
150    DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n",
151            req->contextId(), paddr);
152    lockedAddrList.push_front(LockedAddr(req));
153}
154
155
156// Called on *writes* only... both regular stores and
157// store-conditional operations.  Check for conventional stores which
158// conflict with locked addresses, and for success/failure of store
159// conditionals.
160bool
161PhysicalMemory::checkLockedAddrList(PacketPtr pkt)
162{
163    Request *req = pkt->req;
164    Addr paddr = LockedAddr::mask(req->getPaddr());
165    bool isLLSC = pkt->isLLSC();
166
167    // Initialize return value.  Non-conditional stores always
168    // succeed.  Assume conditional stores will fail until proven
169    // otherwise.
170    bool success = !isLLSC;
171
172    // Iterate over list.  Note that there could be multiple matching
173    // records, as more than one context could have done a load locked
174    // to this location.
175    list<LockedAddr>::iterator i = lockedAddrList.begin();
176
177    while (i != lockedAddrList.end()) {
178
179        if (i->addr == paddr) {
180            // we have a matching address
181
182            if (isLLSC && i->matchesContext(req)) {
183                // it's a store conditional, and as far as the memory
184                // system can tell, the requesting context's lock is
185                // still valid.
186                DPRINTF(LLSC, "StCond success: context %d addr %#x\n",
187                        req->contextId(), paddr);
188                success = true;
189            }
190
191            // Get rid of our record of this lock and advance to next
192            DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
193                    i->contextId, paddr);
194            i = lockedAddrList.erase(i);
195        }
196        else {
197            // no match: advance to next record
198            ++i;
199        }
200    }
201
202    if (isLLSC) {
203        req->setExtraData(success ? 1 : 0);
204    }
205
206    return success;
207}
208
209
210#if TRACING_ON
211
212#define CASE(A, T)                                                      \
213  case sizeof(T):                                                       \
214    DPRINTF(MemoryAccess, A " of size %i on address 0x%x data 0x%x\n",  \
215            pkt->getSize(), pkt->getAddr(), pkt->get<T>());             \
216  break
217
218
219#define TRACE_PACKET(A)                                                 \
220    do {                                                                \
221        switch (pkt->getSize()) {                                       \
222          CASE(A, uint64_t);                                            \
223          CASE(A, uint32_t);                                            \
224          CASE(A, uint16_t);                                            \
225          CASE(A, uint8_t);                                             \
226          default:                                                      \
227            DPRINTF(MemoryAccess, A " of size %i on address 0x%x\n",    \
228                    pkt->getSize(), pkt->getAddr());                    \
229        }                                                               \
230    } while (0)
231
232#else
233
234#define TRACE_PACKET(A)
235
236#endif
237
238Tick
239PhysicalMemory::doAtomicAccess(PacketPtr pkt)
240{
241    assert(pkt->getAddr() >= start() &&
242           pkt->getAddr() + pkt->getSize() <= start() + size());
243
244    if (pkt->memInhibitAsserted()) {
245        DPRINTF(MemoryAccess, "mem inhibited on 0x%x: not responding\n",
246                pkt->getAddr());
247        return 0;
248    }
249
250    uint8_t *hostAddr = pmemAddr + pkt->getAddr() - start();
251
252    if (pkt->cmd == MemCmd::SwapReq) {
253        IntReg overwrite_val;
254        bool overwrite_mem;
255        uint64_t condition_val64;
256        uint32_t condition_val32;
257
258        if (!pmemAddr)
259            panic("Swap only works if there is real memory (i.e. null=False)");
260        assert(sizeof(IntReg) >= pkt->getSize());
261
262        overwrite_mem = true;
263        // keep a copy of our possible write value, and copy what is at the
264        // memory address into the packet
265        std::memcpy(&overwrite_val, pkt->getPtr<uint8_t>(), pkt->getSize());
266        std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
267
268        if (pkt->req->isCondSwap()) {
269            if (pkt->getSize() == sizeof(uint64_t)) {
270                condition_val64 = pkt->req->getExtraData();
271                overwrite_mem = !std::memcmp(&condition_val64, hostAddr,
272                                             sizeof(uint64_t));
273            } else if (pkt->getSize() == sizeof(uint32_t)) {
274                condition_val32 = (uint32_t)pkt->req->getExtraData();
275                overwrite_mem = !std::memcmp(&condition_val32, hostAddr,
276                                             sizeof(uint32_t));
277            } else
278                panic("Invalid size for conditional read/write\n");
279        }
280
281        if (overwrite_mem)
282            std::memcpy(hostAddr, &overwrite_val, pkt->getSize());
283
284        TRACE_PACKET("Read/Write");
285    } else if (pkt->isRead()) {
286        assert(!pkt->isWrite());
287        if (pkt->isLLSC()) {
288            trackLoadLocked(pkt);
289        }
290        if (pmemAddr)
291            memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
292        TRACE_PACKET("Read");
293    } else if (pkt->isWrite()) {
294        if (writeOK(pkt)) {
295            if (pmemAddr)
296                memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize());
297            TRACE_PACKET("Write");
298        }
299    } else if (pkt->isInvalidate()) {
300        //upgrade or invalidate
301        if (pkt->needsResponse()) {
302            pkt->makeAtomicResponse();
303        }
304    } else {
305        panic("unimplemented");
306    }
307
308    if (pkt->needsResponse()) {
309        pkt->makeAtomicResponse();
310    }
311    return calculateLatency(pkt);
312}
313
314
315void
316PhysicalMemory::doFunctionalAccess(PacketPtr pkt)
317{
318    assert(pkt->getAddr() >= start() &&
319           pkt->getAddr() + pkt->getSize() <= start() + size());
320
321
322    uint8_t *hostAddr = pmemAddr + pkt->getAddr() - start();
323
324    if (pkt->isRead()) {
325        if (pmemAddr)
326            memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
327        TRACE_PACKET("Read");
328        pkt->makeAtomicResponse();
329    } else if (pkt->isWrite()) {
330        if (pmemAddr)
331            memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize());
332        TRACE_PACKET("Write");
333        pkt->makeAtomicResponse();
334    } else if (pkt->isPrint()) {
335        Packet::PrintReqState *prs =
336            dynamic_cast<Packet::PrintReqState*>(pkt->senderState);
337        // Need to call printLabels() explicitly since we're not going
338        // through printObj().
339        prs->printLabels();
340        // Right now we just print the single byte at the specified address.
341        ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *hostAddr);
342    } else {
343        panic("PhysicalMemory: unimplemented functional command %s",
344              pkt->cmdString());
345    }
346}
347
348
349Port *
350PhysicalMemory::getPort(const std::string &if_name, int idx)
351{
352    // Accept request for "functional" port for backwards compatibility
353    // with places where this function is called from C++.  I'd prefer
354    // to move all these into Python someday.
355    if (if_name == "functional") {
356        return new MemoryPort(csprintf("%s-functional", name()), this);
357    }
358
359    if (if_name != "port") {
360        panic("PhysicalMemory::getPort: unknown port %s requested", if_name);
361    }
362
363    if (idx >= ports.size()) {
364        ports.resize(idx+1);
365    }
366
367    if (ports[idx] != NULL) {
368        panic("PhysicalMemory::getPort: port %d already assigned", idx);
369    }
370
371    MemoryPort *port =
372        new MemoryPort(csprintf("%s-port%d", name(), idx), this);
373
374    ports[idx] = port;
375    return port;
376}
377
378
379void
380PhysicalMemory::recvStatusChange(Port::Status status)
381{
382}
383
384PhysicalMemory::MemoryPort::MemoryPort(const std::string &_name,
385                                       PhysicalMemory *_memory)
386    : SimpleTimingPort(_name, _memory), memory(_memory)
387{ }
388
389void
390PhysicalMemory::MemoryPort::recvStatusChange(Port::Status status)
391{
392    memory->recvStatusChange(status);
393}
394
395void
396PhysicalMemory::MemoryPort::getDeviceAddressRanges(AddrRangeList &resp,
397                                                   bool &snoop)
398{
399    memory->getAddressRanges(resp, snoop);
400}
401
402void
403PhysicalMemory::getAddressRanges(AddrRangeList &resp, bool &snoop)
404{
405    snoop = false;
406    resp.clear();
407    resp.push_back(RangeSize(start(), params()->range.size()));
408}
409
410int
411PhysicalMemory::MemoryPort::deviceBlockSize()
412{
413    return memory->deviceBlockSize();
414}
415
416Tick
417PhysicalMemory::MemoryPort::recvAtomic(PacketPtr pkt)
418{
419    return memory->doAtomicAccess(pkt);
420}
421
422void
423PhysicalMemory::MemoryPort::recvFunctional(PacketPtr pkt)
424{
425    pkt->pushLabel(memory->name());
426
427    if (!checkFunctional(pkt)) {
428        // Default implementation of SimpleTimingPort::recvFunctional()
429        // calls recvAtomic() and throws away the latency; we can save a
430        // little here by just not calculating the latency.
431        memory->doFunctionalAccess(pkt);
432    }
433
434    pkt->popLabel();
435}
436
437unsigned int
438PhysicalMemory::drain(Event *de)
439{
440    int count = 0;
441    for (PortIterator pi = ports.begin(); pi != ports.end(); ++pi) {
442        count += (*pi)->drain(de);
443    }
444
445    if (count)
446        changeState(Draining);
447    else
448        changeState(Drained);
449    return count;
450}
451
452void
453PhysicalMemory::serialize(ostream &os)
454{
455    if (!pmemAddr)
456        return;
457
458    gzFile compressedMem;
459    string filename = name() + ".physmem";
460
461    SERIALIZE_SCALAR(filename);
462
463    // write memory file
464    string thefile = Checkpoint::dir() + "/" + filename.c_str();
465    int fd = creat(thefile.c_str(), 0664);
466    if (fd < 0) {
467        perror("creat");
468        fatal("Can't open physical memory checkpoint file '%s'\n", filename);
469    }
470
471    compressedMem = gzdopen(fd, "wb");
472    if (compressedMem == NULL)
473        fatal("Insufficient memory to allocate compression state for %s\n",
474                filename);
475
476    if (gzwrite(compressedMem, pmemAddr, params()->range.size()) !=
477        params()->range.size()) {
478        fatal("Write failed on physical memory checkpoint file '%s'\n",
479              filename);
480    }
481
482    if (gzclose(compressedMem))
483        fatal("Close failed on physical memory checkpoint file '%s'\n",
484              filename);
485}
486
487void
488PhysicalMemory::unserialize(Checkpoint *cp, const string &section)
489{
490    if (!pmemAddr)
491        return;
492
493    gzFile compressedMem;
494    long *tempPage;
495    long *pmem_current;
496    uint64_t curSize;
497    uint32_t bytesRead;
498    const int chunkSize = 16384;
499
500    string filename;
501
502    UNSERIALIZE_SCALAR(filename);
503
504    filename = cp->cptDir + "/" + filename;
505
506    // mmap memoryfile
507    int fd = open(filename.c_str(), O_RDONLY);
508    if (fd < 0) {
509        perror("open");
510        fatal("Can't open physical memory checkpoint file '%s'", filename);
511    }
512
513    compressedMem = gzdopen(fd, "rb");
514    if (compressedMem == NULL)
515        fatal("Insufficient memory to allocate compression state for %s\n",
516                filename);
517
518    // unmap file that was mmaped in the constructor
519    // This is done here to make sure that gzip and open don't muck with our
520    // nice large space of memory before we reallocate it
521    munmap((char*)pmemAddr, params()->range.size());
522
523    pmemAddr = (uint8_t *)mmap(NULL, params()->range.size(),
524        PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
525
526    if (pmemAddr == (void *)MAP_FAILED) {
527        perror("mmap");
528        fatal("Could not mmap physical memory!\n");
529    }
530
531    curSize = 0;
532    tempPage = (long*)malloc(chunkSize);
533    if (tempPage == NULL)
534        fatal("Unable to malloc memory to read file %s\n", filename);
535
536    /* Only copy bytes that are non-zero, so we don't give the VM system hell */
537    while (curSize < params()->range.size()) {
538        bytesRead = gzread(compressedMem, tempPage, chunkSize);
539        if (bytesRead != chunkSize &&
540            bytesRead != params()->range.size() - curSize)
541            fatal("Read failed on physical memory checkpoint file '%s'"
542                  " got %d bytes, expected %d or %d bytes\n",
543                  filename, bytesRead, chunkSize,
544                  params()->range.size() - curSize);
545
546        assert(bytesRead % sizeof(long) == 0);
547
548        for (int x = 0; x < bytesRead/sizeof(long); x++)
549        {
550             if (*(tempPage+x) != 0) {
551                 pmem_current = (long*)(pmemAddr + curSize + x * sizeof(long));
552                 *pmem_current = *(tempPage+x);
553             }
554        }
555        curSize += bytesRead;
556    }
557
558    free(tempPage);
559
560    if (gzclose(compressedMem))
561        fatal("Close failed on physical memory checkpoint file '%s'\n",
562              filename);
563
564}
565
566PhysicalMemory *
567PhysicalMemoryParams::create()
568{
569    return new PhysicalMemory(this);
570}
571