abstract_mem.cc revision 3879
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ron Dreslinski 292665Ssaidi@eecs.umich.edu * Ali Saidi 302665Ssaidi@eecs.umich.edu */ 312665Ssaidi@eecs.umich.edu 322SN/A#include <sys/types.h> 332SN/A#include <sys/mman.h> 342SN/A#include <errno.h> 352SN/A#include <fcntl.h> 362SN/A#include <unistd.h> 372973Sgblack@eecs.umich.edu#include <zlib.h> 3856SN/A 391717SN/A#include <iostream> 402518SN/A#include <string> 4156SN/A 422518SN/A#include "arch/isa_traits.hh" 432518SN/A#include "base/misc.hh" 442SN/A#include "config/full_system.hh" 453065Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 463065Sgblack@eecs.umich.edu#include "mem/physical.hh" 473065Sgblack@eecs.umich.edu#include "sim/builder.hh" 482SN/A#include "sim/eventq.hh" 492973Sgblack@eecs.umich.edu#include "sim/host.hh" 502SN/A 512SN/Ausing namespace std; 522SN/Ausing namespace TheISA; 532SN/A 542SN/APhysicalMemory::PhysicalMemory(Params *p) 552SN/A : MemObject(p->name), pmemAddr(NULL), port(NULL), lat(p->latency), _params(p) 562SN/A{ 572SN/A if (params()->addrRange.size() % TheISA::PageBytes != 0) 582SN/A panic("Memory Size not divisible by page size\n"); 592SN/A 602973Sgblack@eecs.umich.edu int map_flags = MAP_ANON | MAP_PRIVATE; 612973Sgblack@eecs.umich.edu pmemAddr = (uint8_t *)mmap(NULL, params()->addrRange.size(), PROT_READ | PROT_WRITE, 623065Sgblack@eecs.umich.edu map_flags, -1, 0); 633380Sgblack@eecs.umich.edu 643380Sgblack@eecs.umich.edu if (pmemAddr == (void *)MAP_FAILED) { 653380Sgblack@eecs.umich.edu perror("mmap"); 663380Sgblack@eecs.umich.edu fatal("Could not mmap!\n"); 673380Sgblack@eecs.umich.edu } 683380Sgblack@eecs.umich.edu 693380Sgblack@eecs.umich.edu //If requested, initialize all the memory to 0 703380Sgblack@eecs.umich.edu if(params()->zero) 713380Sgblack@eecs.umich.edu memset(pmemAddr, 0, params()->addrRange.size()); 723380Sgblack@eecs.umich.edu 733380Sgblack@eecs.umich.edu pagePtr = 0; 743380Sgblack@eecs.umich.edu} 753380Sgblack@eecs.umich.edu 763380Sgblack@eecs.umich.eduvoid 773065Sgblack@eecs.umich.eduPhysicalMemory::init() 783380Sgblack@eecs.umich.edu{ 793380Sgblack@eecs.umich.edu if (!port) 803059Sgblack@eecs.umich.edu panic("PhysicalMemory not connected to anything!"); 813380Sgblack@eecs.umich.edu port->sendStatusChange(Port::RangeChange); 823059Sgblack@eecs.umich.edu} 833380Sgblack@eecs.umich.edu 843380Sgblack@eecs.umich.eduPhysicalMemory::~PhysicalMemory() 853059Sgblack@eecs.umich.edu{ 863380Sgblack@eecs.umich.edu if (pmemAddr) 873380Sgblack@eecs.umich.edu munmap(pmemAddr, params()->addrRange.size()); 883380Sgblack@eecs.umich.edu //Remove memPorts? 893380Sgblack@eecs.umich.edu} 903380Sgblack@eecs.umich.edu 913380Sgblack@eecs.umich.eduAddr 923380Sgblack@eecs.umich.eduPhysicalMemory::new_page() 933380Sgblack@eecs.umich.edu{ 943380Sgblack@eecs.umich.edu Addr return_addr = pagePtr << LogVMPageSize; 953380Sgblack@eecs.umich.edu return_addr += params()->addrRange.start; 963380Sgblack@eecs.umich.edu 973380Sgblack@eecs.umich.edu ++pagePtr; 983380Sgblack@eecs.umich.edu return return_addr; 993380Sgblack@eecs.umich.edu} 1003059Sgblack@eecs.umich.edu 1013380Sgblack@eecs.umich.eduint 1023380Sgblack@eecs.umich.eduPhysicalMemory::deviceBlockSize() 1033380Sgblack@eecs.umich.edu{ 1043380Sgblack@eecs.umich.edu //Can accept anysize request 1053380Sgblack@eecs.umich.edu return 0; 1063380Sgblack@eecs.umich.edu} 1073380Sgblack@eecs.umich.edu 1083380Sgblack@eecs.umich.eduTick 1093059Sgblack@eecs.umich.eduPhysicalMemory::calculateLatency(PacketPtr pkt) 1103059Sgblack@eecs.umich.edu{ 1113380Sgblack@eecs.umich.edu return lat; 1123380Sgblack@eecs.umich.edu} 1133380Sgblack@eecs.umich.edu 1143380Sgblack@eecs.umich.edu 1153380Sgblack@eecs.umich.edu 1163380Sgblack@eecs.umich.edu// Add load-locked to tracking list. Should only be called if the 1173380Sgblack@eecs.umich.edu// operation is a load and the LOCKED flag is set. 1183380Sgblack@eecs.umich.eduvoid 1193380Sgblack@eecs.umich.eduPhysicalMemory::trackLoadLocked(Request *req) 1203380Sgblack@eecs.umich.edu{ 1213380Sgblack@eecs.umich.edu Addr paddr = LockedAddr::mask(req->getPaddr()); 1223059Sgblack@eecs.umich.edu 1233065Sgblack@eecs.umich.edu // first we check if we already have a locked addr for this 1242973Sgblack@eecs.umich.edu // xc. Since each xc only gets one, we just update the 1252973Sgblack@eecs.umich.edu // existing record with the new address. 1261968SN/A list<LockedAddr>::iterator i; 1273064Sgblack@eecs.umich.edu 1281968SN/A for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) { 1291968SN/A if (i->matchesContext(req)) { 1301968SN/A DPRINTF(LLSC, "Modifying lock record: cpu %d thread %d addr %#x\n", 1311968SN/A req->getCpuNum(), req->getThreadNum(), paddr); 1321967SN/A i->addr = paddr; 1331967SN/A return; 1341967SN/A } 1351967SN/A } 1361967SN/A 1371967SN/A // no record for this xc: need to allocate a new one 1381967SN/A DPRINTF(LLSC, "Adding lock record: cpu %d thread %d addr %#x\n", 1391967SN/A req->getCpuNum(), req->getThreadNum(), paddr); 1401967SN/A lockedAddrList.push_front(LockedAddr(req)); 1411967SN/A} 1421904SN/A 1431904SN/A 1441904SN/A// Called on *writes* only... both regular stores and 1451904SN/A// store-conditional operations. Check for conventional stores which 146452SN/A// conflict with locked addresses, and for success/failure of store 1473064Sgblack@eecs.umich.edu// conditionals. 1482SN/Abool 1491904SN/APhysicalMemory::checkLockedAddrList(Request *req) 1501904SN/A{ 1512SN/A Addr paddr = LockedAddr::mask(req->getPaddr()); 1521904SN/A bool isLocked = req->isLocked(); 1533064Sgblack@eecs.umich.edu 1542SN/A // Initialize return value. Non-conditional stores always 1552SN/A // succeed. Assume conditional stores will fail until proven 1561904SN/A // otherwise. 1571904SN/A bool success = !isLocked; 1581904SN/A 1592299SN/A // Iterate over list. Note that there could be multiple matching 1602299SN/A // records, as more than one context could have done a load locked 1611904SN/A // to this location. 1621904SN/A list<LockedAddr>::iterator i = lockedAddrList.begin(); 1631904SN/A 1641904SN/A while (i != lockedAddrList.end()) { 1651904SN/A 1661904SN/A if (i->addr == paddr) { 1671904SN/A // we have a matching address 168452SN/A 1691904SN/A if (isLocked && i->matchesContext(req)) { 1701904SN/A // it's a store conditional, and as far as the memory 1711904SN/A // system can tell, the requesting context's lock is 1722SN/A // still valid. 1732SN/A DPRINTF(LLSC, "StCond success: cpu %d thread %d addr %#x\n", 1741904SN/A req->getCpuNum(), req->getThreadNum(), paddr); 1751904SN/A success = true; 1761904SN/A } 1771904SN/A 1781904SN/A // Get rid of our record of this lock and advance to next 1791904SN/A DPRINTF(LLSC, "Erasing lock record: cpu %d thread %d addr %#x\n", 1802SN/A i->cpuNum, i->threadNum, paddr); 1811904SN/A i = lockedAddrList.erase(i); 1822SN/A } 1832SN/A else { 1841904SN/A // no match: advance to next record 1852SN/A ++i; 1861904SN/A } 1871904SN/A } 1881904SN/A 1891904SN/A if (isLocked) { 1901904SN/A req->setScResult(success ? 1 : 0); 1911904SN/A } 1921904SN/A 1931904SN/A return success; 1941904SN/A} 1951904SN/A 1961904SN/Avoid 1971904SN/APhysicalMemory::doFunctionalAccess(PacketPtr pkt) 1981904SN/A{ 1991904SN/A assert(pkt->getAddr() >= params()->addrRange.start && 2001904SN/A pkt->getAddr() + pkt->getSize() <= params()->addrRange.start + 2011904SN/A params()->addrRange.size()); 2021904SN/A 2031904SN/A if (pkt->isRead()) { 2041904SN/A if (pkt->req->isLocked()) { 2051904SN/A trackLoadLocked(pkt->req); 2062525SN/A } 2071904SN/A memcpy(pkt->getPtr<uint8_t>(), 2082525SN/A pmemAddr + pkt->getAddr() - params()->addrRange.start, 2092525SN/A pkt->getSize()); 2102525SN/A#if TRACING_ON 2111904SN/A switch (pkt->getSize()) { 2121904SN/A case sizeof(uint64_t): 2131904SN/A DPRINTF(MemoryAccess, "Read of size %i on address 0x%x data 0x%x\n", 2141904SN/A pkt->getSize(), pkt->getAddr(),pkt->get<uint64_t>()); 2151904SN/A break; 2161904SN/A case sizeof(uint32_t): 2171904SN/A DPRINTF(MemoryAccess, "Read of size %i on address 0x%x data 0x%x\n", 2181904SN/A pkt->getSize(), pkt->getAddr(),pkt->get<uint32_t>()); 2191967SN/A break; 2201967SN/A case sizeof(uint16_t): 2211967SN/A DPRINTF(MemoryAccess, "Read of size %i on address 0x%x data 0x%x\n", 2221967SN/A pkt->getSize(), pkt->getAddr(),pkt->get<uint16_t>()); 2231967SN/A break; 2242SN/A case sizeof(uint8_t): 2252SN/A DPRINTF(MemoryAccess, "Read of size %i on address 0x%x data 0x%x\n", 2262SN/A pkt->getSize(), pkt->getAddr(),pkt->get<uint8_t>()); 2272SN/A break; 2282SN/A default: 2291967SN/A DPRINTF(MemoryAccess, "Read of size %i on address 0x%x\n", 2302SN/A pkt->getSize(), pkt->getAddr()); 2312SN/A } 2322SN/A#endif 2332SN/A } 2342SN/A else if (pkt->isWrite()) { 2352SN/A if (writeOK(pkt->req)) { 2362SN/A memcpy(pmemAddr + pkt->getAddr() - params()->addrRange.start, 2372SN/A pkt->getPtr<uint8_t>(), pkt->getSize()); 2382SN/A#if TRACING_ON 2392SN/A switch (pkt->getSize()) { 2402SN/A case sizeof(uint64_t): 2412SN/A DPRINTF(MemoryAccess, "Write of size %i on address 0x%x data 0x%x\n", 2422SN/A pkt->getSize(), pkt->getAddr(),pkt->get<uint64_t>()); 2432SN/A break; 2442SN/A case sizeof(uint32_t): 2452SN/A DPRINTF(MemoryAccess, "Write of size %i on address 0x%x data 0x%x\n", 2462SN/A pkt->getSize(), pkt->getAddr(),pkt->get<uint32_t>()); 2472SN/A break; 2482SN/A case sizeof(uint16_t): 2492SN/A DPRINTF(MemoryAccess, "Write of size %i on address 0x%x data 0x%x\n", 2501413SN/A pkt->getSize(), pkt->getAddr(),pkt->get<uint16_t>()); 2512SN/A break; 2522SN/A case sizeof(uint8_t): 2532SN/A DPRINTF(MemoryAccess, "Write of size %i on address 0x%x data 0x%x\n", 2542SN/A pkt->getSize(), pkt->getAddr(),pkt->get<uint8_t>()); 2552SN/A break; 2562SN/A default: 2572SN/A DPRINTF(MemoryAccess, "Write of size %i on address 0x%x\n", 2582SN/A pkt->getSize(), pkt->getAddr()); 2592SN/A } 2602SN/A#endif 2612SN/A } 2622SN/A } 2632SN/A else if (pkt->isInvalidate()) { 2642SN/A //upgrade or invalidate 2652SN/A pkt->flags |= SATISFIED; 2662SN/A } 2672SN/A else { 2682973Sgblack@eecs.umich.edu panic("unimplemented"); 2692973Sgblack@eecs.umich.edu } 2702299SN/A 2712299SN/A pkt->result = Packet::Success; 2721904SN/A} 2731904SN/A 2741967SN/APort * 2751967SN/APhysicalMemory::getPort(const std::string &if_name, int idx) 2761967SN/A{ 2771904SN/A if (if_name == "port" && idx == -1) { 2782SN/A if (port != NULL) 2792SN/A panic("PhysicalMemory::getPort: additional port requested to memory!"); 2802SN/A port = new MemoryPort(name() + "-port", this); 2812SN/A return port; 2822SN/A } else if (if_name == "functional") { 2832SN/A /* special port for functional writes at startup. And for memtester */ 2842SN/A return new MemoryPort(name() + "-funcport", this); 2852SN/A } else { 2862SN/A panic("PhysicalMemory::getPort: unknown port %s requested", if_name); 2872SN/A } 2882SN/A} 2892SN/A 2902SN/Avoid 2912SN/APhysicalMemory::recvStatusChange(Port::Status status) 2922SN/A{ 2932SN/A} 2942SN/A 2952SN/APhysicalMemory::MemoryPort::MemoryPort(const std::string &_name, 2962973Sgblack@eecs.umich.edu PhysicalMemory *_memory) 2972299SN/A : SimpleTimingPort(_name), memory(_memory) 2981904SN/A{ } 2991967SN/A 3002SN/Avoid 3012SN/APhysicalMemory::MemoryPort::recvStatusChange(Port::Status status) 3022SN/A{ 3032SN/A memory->recvStatusChange(status); 3042SN/A} 3052SN/A 3062SN/Avoid 3072SN/APhysicalMemory::MemoryPort::getDeviceAddressRanges(AddrRangeList &resp, 308 AddrRangeList &snoop) 309{ 310 memory->getAddressRanges(resp, snoop); 311} 312 313void 314PhysicalMemory::getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) 315{ 316 snoop.clear(); 317 resp.clear(); 318 resp.push_back(RangeSize(params()->addrRange.start, 319 params()->addrRange.size())); 320} 321 322int 323PhysicalMemory::MemoryPort::deviceBlockSize() 324{ 325 return memory->deviceBlockSize(); 326} 327 328Tick 329PhysicalMemory::MemoryPort::recvAtomic(PacketPtr pkt) 330{ 331 memory->doFunctionalAccess(pkt); 332 return memory->calculateLatency(pkt); 333} 334 335void 336PhysicalMemory::MemoryPort::recvFunctional(PacketPtr pkt) 337{ 338 //Since we are overriding the function, make sure to have the impl of the 339 //check or functional accesses here. 340 std::list<std::pair<Tick,PacketPtr> >::iterator i = transmitList.begin(); 341 std::list<std::pair<Tick,PacketPtr> >::iterator end = transmitList.end(); 342 bool notDone = true; 343 344 while (i != end && notDone) { 345 PacketPtr target = i->second; 346 // If the target contains data, and it overlaps the 347 // probed request, need to update data 348 if (target->intersect(pkt)) 349 notDone = fixPacket(pkt, target); 350 i++; 351 } 352 353 // Default implementation of SimpleTimingPort::recvFunctional() 354 // calls recvAtomic() and throws away the latency; we can save a 355 // little here by just not calculating the latency. 356 memory->doFunctionalAccess(pkt); 357} 358 359unsigned int 360PhysicalMemory::drain(Event *de) 361{ 362 int count = port->drain(de); 363 if (count) 364 changeState(Draining); 365 else 366 changeState(Drained); 367 return count; 368} 369 370void 371PhysicalMemory::serialize(ostream &os) 372{ 373 gzFile compressedMem; 374 string filename = name() + ".physmem"; 375 376 SERIALIZE_SCALAR(filename); 377 378 // write memory file 379 string thefile = Checkpoint::dir() + "/" + filename.c_str(); 380 int fd = creat(thefile.c_str(), 0664); 381 if (fd < 0) { 382 perror("creat"); 383 fatal("Can't open physical memory checkpoint file '%s'\n", filename); 384 } 385 386 compressedMem = gzdopen(fd, "wb"); 387 if (compressedMem == NULL) 388 fatal("Insufficient memory to allocate compression state for %s\n", 389 filename); 390 391 if (gzwrite(compressedMem, pmemAddr, params()->addrRange.size()) != params()->addrRange.size()) { 392 fatal("Write failed on physical memory checkpoint file '%s'\n", 393 filename); 394 } 395 396 if (gzclose(compressedMem)) 397 fatal("Close failed on physical memory checkpoint file '%s'\n", 398 filename); 399} 400 401void 402PhysicalMemory::unserialize(Checkpoint *cp, const string §ion) 403{ 404 gzFile compressedMem; 405 long *tempPage; 406 long *pmem_current; 407 uint64_t curSize; 408 uint32_t bytesRead; 409 const int chunkSize = 16384; 410 411 412 string filename; 413 414 UNSERIALIZE_SCALAR(filename); 415 416 filename = cp->cptDir + "/" + filename; 417 418 // mmap memoryfile 419 int fd = open(filename.c_str(), O_RDONLY); 420 if (fd < 0) { 421 perror("open"); 422 fatal("Can't open physical memory checkpoint file '%s'", filename); 423 } 424 425 compressedMem = gzdopen(fd, "rb"); 426 if (compressedMem == NULL) 427 fatal("Insufficient memory to allocate compression state for %s\n", 428 filename); 429 430 // unmap file that was mmaped in the constructor 431 // This is done here to make sure that gzip and open don't muck with our 432 // nice large space of memory before we reallocate it 433 munmap(pmemAddr, params()->addrRange.size()); 434 435 pmemAddr = (uint8_t *)mmap(NULL, params()->addrRange.size(), PROT_READ | PROT_WRITE, 436 MAP_ANON | MAP_PRIVATE, -1, 0); 437 438 if (pmemAddr == (void *)MAP_FAILED) { 439 perror("mmap"); 440 fatal("Could not mmap physical memory!\n"); 441 } 442 443 curSize = 0; 444 tempPage = (long*)malloc(chunkSize); 445 if (tempPage == NULL) 446 fatal("Unable to malloc memory to read file %s\n", filename); 447 448 /* Only copy bytes that are non-zero, so we don't give the VM system hell */ 449 while (curSize < params()->addrRange.size()) { 450 bytesRead = gzread(compressedMem, tempPage, chunkSize); 451 if (bytesRead != chunkSize && bytesRead != params()->addrRange.size() - curSize) 452 fatal("Read failed on physical memory checkpoint file '%s'" 453 " got %d bytes, expected %d or %d bytes\n", 454 filename, bytesRead, chunkSize, params()->addrRange.size()-curSize); 455 456 assert(bytesRead % sizeof(long) == 0); 457 458 for (int x = 0; x < bytesRead/sizeof(long); x++) 459 { 460 if (*(tempPage+x) != 0) { 461 pmem_current = (long*)(pmemAddr + curSize + x * sizeof(long)); 462 *pmem_current = *(tempPage+x); 463 } 464 } 465 curSize += bytesRead; 466 } 467 468 free(tempPage); 469 470 if (gzclose(compressedMem)) 471 fatal("Close failed on physical memory checkpoint file '%s'\n", 472 filename); 473 474} 475 476 477BEGIN_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory) 478 479 Param<string> file; 480 Param<Range<Addr> > range; 481 Param<Tick> latency; 482 Param<bool> zero; 483 484END_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory) 485 486BEGIN_INIT_SIM_OBJECT_PARAMS(PhysicalMemory) 487 488 INIT_PARAM_DFLT(file, "memory mapped file", ""), 489 INIT_PARAM(range, "Device Address Range"), 490 INIT_PARAM(latency, "Memory access latency"), 491 INIT_PARAM(zero, "Zero initialize memory") 492 493END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory) 494 495CREATE_SIM_OBJECT(PhysicalMemory) 496{ 497 PhysicalMemory::Params *p = new PhysicalMemory::Params; 498 p->name = getInstanceName(); 499 p->addrRange = range; 500 p->latency = latency; 501 p->zero = zero; 502 return new PhysicalMemory(p); 503} 504 505REGISTER_SIM_OBJECT("PhysicalMemory", PhysicalMemory) 506