abstract_mem.cc revision 11614
12391SN/A/* 28931Sandreas.hansson@arm.com * Copyright (c) 2010-2012 ARM Limited 37733SN/A * All rights reserved 47733SN/A * 57733SN/A * The license below extends only to copyright in the software and shall 67733SN/A * not be construed as granting a license to any other intellectual 77733SN/A * property including but not limited to intellectual property relating 87733SN/A * to a hardware implementation of the functionality of the software 97733SN/A * licensed hereunder. You may use the software subject to the license 107733SN/A * terms below provided that you ensure that this notice is replicated 117733SN/A * unmodified and in its entirety in all distributions of the software, 127733SN/A * modified or unmodified, in source code or in binary form. 137733SN/A * 142391SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 152391SN/A * All rights reserved. 162391SN/A * 172391SN/A * Redistribution and use in source and binary forms, with or without 182391SN/A * modification, are permitted provided that the following conditions are 192391SN/A * met: redistributions of source code must retain the above copyright 202391SN/A * notice, this list of conditions and the following disclaimer; 212391SN/A * redistributions in binary form must reproduce the above copyright 222391SN/A * notice, this list of conditions and the following disclaimer in the 232391SN/A * documentation and/or other materials provided with the distribution; 242391SN/A * neither the name of the copyright holders nor the names of its 252391SN/A * contributors may be used to endorse or promote products derived from 262391SN/A * this software without specific prior written permission. 272391SN/A * 282391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352391SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362391SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Ron Dreslinski 412914SN/A * Ali Saidi 428931Sandreas.hansson@arm.com * Andreas Hansson 432391SN/A */ 442391SN/A 4510466Sandreas.hansson@arm.com#include <vector> 4610466Sandreas.hansson@arm.com 4710102Sali.saidi@arm.com#include "cpu/base.hh" 4810102Sali.saidi@arm.com#include "cpu/thread_context.hh" 498232SN/A#include "debug/LLSC.hh" 508232SN/A#include "debug/MemoryAccess.hh" 518931Sandreas.hansson@arm.com#include "mem/abstract_mem.hh" 523879SN/A#include "mem/packet_access.hh" 539053Sdam.sunwoo@arm.com#include "sim/system.hh" 542394SN/A 552391SN/Ausing namespace std; 562391SN/A 578931Sandreas.hansson@arm.comAbstractMemory::AbstractMemory(const Params *p) : 588931Sandreas.hansson@arm.com MemObject(p), range(params()->range), pmemAddr(NULL), 599053Sdam.sunwoo@arm.com confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map), 6011614Sdavid.j.hashe@gmail.com kvmMap(p->kvm_map), _system(NULL) 612391SN/A{ 6210466Sandreas.hansson@arm.com} 6310466Sandreas.hansson@arm.com 6410466Sandreas.hansson@arm.comvoid 6510466Sandreas.hansson@arm.comAbstractMemory::init() 6610466Sandreas.hansson@arm.com{ 6710466Sandreas.hansson@arm.com assert(system()); 6810466Sandreas.hansson@arm.com 6910466Sandreas.hansson@arm.com if (size() % _system->getPageBytes() != 0) 702391SN/A panic("Memory Size not divisible by page size\n"); 712391SN/A} 722391SN/A 739293Sandreas.hansson@arm.comvoid 749293Sandreas.hansson@arm.comAbstractMemory::setBackingStore(uint8_t* pmem_addr) 752391SN/A{ 769293Sandreas.hansson@arm.com pmemAddr = pmem_addr; 772391SN/A} 782391SN/A 798719SN/Avoid 808931Sandreas.hansson@arm.comAbstractMemory::regStats() 818719SN/A{ 8211522Sstephan.diestelhorst@arm.com MemObject::regStats(); 8311522Sstephan.diestelhorst@arm.com 848719SN/A using namespace Stats; 858719SN/A 869053Sdam.sunwoo@arm.com assert(system()); 879053Sdam.sunwoo@arm.com 888719SN/A bytesRead 899053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 908719SN/A .name(name() + ".bytes_read") 918719SN/A .desc("Number of bytes read from this memory") 929053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 938719SN/A ; 949053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 959053Sdam.sunwoo@arm.com bytesRead.subname(i, system()->getMasterName(i)); 969053Sdam.sunwoo@arm.com } 978719SN/A bytesInstRead 989053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 998719SN/A .name(name() + ".bytes_inst_read") 1008719SN/A .desc("Number of instructions bytes read from this memory") 1019053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1028719SN/A ; 1039053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1049053Sdam.sunwoo@arm.com bytesInstRead.subname(i, system()->getMasterName(i)); 1059053Sdam.sunwoo@arm.com } 1068719SN/A bytesWritten 1079053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1088719SN/A .name(name() + ".bytes_written") 1098719SN/A .desc("Number of bytes written to this memory") 1109053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1118719SN/A ; 1129053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1139053Sdam.sunwoo@arm.com bytesWritten.subname(i, system()->getMasterName(i)); 1149053Sdam.sunwoo@arm.com } 1158719SN/A numReads 1169053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1178719SN/A .name(name() + ".num_reads") 1188719SN/A .desc("Number of read requests responded to by this memory") 1199053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1208719SN/A ; 1219053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1229053Sdam.sunwoo@arm.com numReads.subname(i, system()->getMasterName(i)); 1239053Sdam.sunwoo@arm.com } 1248719SN/A numWrites 1259053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1268719SN/A .name(name() + ".num_writes") 1278719SN/A .desc("Number of write requests responded to by this memory") 1289053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1298719SN/A ; 1309053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1319053Sdam.sunwoo@arm.com numWrites.subname(i, system()->getMasterName(i)); 1329053Sdam.sunwoo@arm.com } 1338719SN/A numOther 1349053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1358719SN/A .name(name() + ".num_other") 1368719SN/A .desc("Number of other requests responded to by this memory") 1379053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1388719SN/A ; 1399053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1409053Sdam.sunwoo@arm.com numOther.subname(i, system()->getMasterName(i)); 1419053Sdam.sunwoo@arm.com } 1428719SN/A bwRead 1438719SN/A .name(name() + ".bw_read") 1448719SN/A .desc("Total read bandwidth from this memory (bytes/s)") 1458719SN/A .precision(0) 1468719SN/A .prereq(bytesRead) 1479053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1488719SN/A ; 1499053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1509053Sdam.sunwoo@arm.com bwRead.subname(i, system()->getMasterName(i)); 1519053Sdam.sunwoo@arm.com } 1529053Sdam.sunwoo@arm.com 1538719SN/A bwInstRead 1548719SN/A .name(name() + ".bw_inst_read") 1558719SN/A .desc("Instruction read bandwidth from this memory (bytes/s)") 1568719SN/A .precision(0) 1578719SN/A .prereq(bytesInstRead) 1589053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1598719SN/A ; 1609053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1619053Sdam.sunwoo@arm.com bwInstRead.subname(i, system()->getMasterName(i)); 1629053Sdam.sunwoo@arm.com } 1638719SN/A bwWrite 1648719SN/A .name(name() + ".bw_write") 1658719SN/A .desc("Write bandwidth from this memory (bytes/s)") 1668719SN/A .precision(0) 1678719SN/A .prereq(bytesWritten) 1689053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1698719SN/A ; 1709053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1719053Sdam.sunwoo@arm.com bwWrite.subname(i, system()->getMasterName(i)); 1729053Sdam.sunwoo@arm.com } 1738719SN/A bwTotal 1748719SN/A .name(name() + ".bw_total") 1758719SN/A .desc("Total bandwidth to/from this memory (bytes/s)") 1768719SN/A .precision(0) 1778719SN/A .prereq(bwTotal) 1789053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1798719SN/A ; 1809053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1819053Sdam.sunwoo@arm.com bwTotal.subname(i, system()->getMasterName(i)); 1829053Sdam.sunwoo@arm.com } 1838719SN/A bwRead = bytesRead / simSeconds; 1848719SN/A bwInstRead = bytesInstRead / simSeconds; 1858719SN/A bwWrite = bytesWritten / simSeconds; 1868719SN/A bwTotal = (bytesRead + bytesWritten) / simSeconds; 1878719SN/A} 1888719SN/A 1899235Sandreas.hansson@arm.comAddrRange 1909098Sandreas.hansson@arm.comAbstractMemory::getAddrRange() const 1912408SN/A{ 1928931Sandreas.hansson@arm.com return range; 1932408SN/A} 1942408SN/A 1953170SN/A// Add load-locked to tracking list. Should only be called if the 1966076SN/A// operation is a load and the LLSC flag is set. 1973170SN/Avoid 1988931Sandreas.hansson@arm.comAbstractMemory::trackLoadLocked(PacketPtr pkt) 1993170SN/A{ 2004626SN/A Request *req = pkt->req; 2013170SN/A Addr paddr = LockedAddr::mask(req->getPaddr()); 2023170SN/A 2033170SN/A // first we check if we already have a locked addr for this 2043170SN/A // xc. Since each xc only gets one, we just update the 2053170SN/A // existing record with the new address. 2063170SN/A list<LockedAddr>::iterator i; 2073170SN/A 2083170SN/A for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) { 2093170SN/A if (i->matchesContext(req)) { 2105714SN/A DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n", 2115714SN/A req->contextId(), paddr); 2123170SN/A i->addr = paddr; 2133170SN/A return; 2143170SN/A } 2153170SN/A } 2163170SN/A 2173170SN/A // no record for this xc: need to allocate a new one 2185714SN/A DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n", 2195714SN/A req->contextId(), paddr); 2203170SN/A lockedAddrList.push_front(LockedAddr(req)); 2213170SN/A} 2223170SN/A 2233170SN/A 2243170SN/A// Called on *writes* only... both regular stores and 2253170SN/A// store-conditional operations. Check for conventional stores which 2263170SN/A// conflict with locked addresses, and for success/failure of store 2273170SN/A// conditionals. 2283170SN/Abool 2298931Sandreas.hansson@arm.comAbstractMemory::checkLockedAddrList(PacketPtr pkt) 2303170SN/A{ 2314626SN/A Request *req = pkt->req; 2323170SN/A Addr paddr = LockedAddr::mask(req->getPaddr()); 2336102SN/A bool isLLSC = pkt->isLLSC(); 2343170SN/A 2353170SN/A // Initialize return value. Non-conditional stores always 2363170SN/A // succeed. Assume conditional stores will fail until proven 2373170SN/A // otherwise. 2389080Smatt.evans@arm.com bool allowStore = !isLLSC; 2393170SN/A 2409080Smatt.evans@arm.com // Iterate over list. Note that there could be multiple matching records, 2419080Smatt.evans@arm.com // as more than one context could have done a load locked to this location. 2429080Smatt.evans@arm.com // Only remove records when we succeed in finding a record for (xc, addr); 2439080Smatt.evans@arm.com // then, remove all records with this address. Failed store-conditionals do 2449080Smatt.evans@arm.com // not blow unrelated reservations. 2453170SN/A list<LockedAddr>::iterator i = lockedAddrList.begin(); 2463170SN/A 2479080Smatt.evans@arm.com if (isLLSC) { 2489080Smatt.evans@arm.com while (i != lockedAddrList.end()) { 2499080Smatt.evans@arm.com if (i->addr == paddr && i->matchesContext(req)) { 2509080Smatt.evans@arm.com // it's a store conditional, and as far as the memory system can 2519080Smatt.evans@arm.com // tell, the requesting context's lock is still valid. 2525714SN/A DPRINTF(LLSC, "StCond success: context %d addr %#x\n", 2535714SN/A req->contextId(), paddr); 2549080Smatt.evans@arm.com allowStore = true; 2559080Smatt.evans@arm.com break; 2563170SN/A } 2579080Smatt.evans@arm.com // If we didn't find a match, keep searching! Someone else may well 2589080Smatt.evans@arm.com // have a reservation on this line here but we may find ours in just 2599080Smatt.evans@arm.com // a little while. 2609080Smatt.evans@arm.com i++; 2613170SN/A } 2629080Smatt.evans@arm.com req->setExtraData(allowStore ? 1 : 0); 2639080Smatt.evans@arm.com } 2649080Smatt.evans@arm.com // LLSCs that succeeded AND non-LLSC stores both fall into here: 2659080Smatt.evans@arm.com if (allowStore) { 2669080Smatt.evans@arm.com // We write address paddr. However, there may be several entries with a 2679080Smatt.evans@arm.com // reservation on this address (for other contextIds) and they must all 2689080Smatt.evans@arm.com // be removed. 2699080Smatt.evans@arm.com i = lockedAddrList.begin(); 2709080Smatt.evans@arm.com while (i != lockedAddrList.end()) { 2719080Smatt.evans@arm.com if (i->addr == paddr) { 2729080Smatt.evans@arm.com DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n", 2739080Smatt.evans@arm.com i->contextId, paddr); 27410102Sali.saidi@arm.com // For ARM, a spinlock would typically include a Wait 27510102Sali.saidi@arm.com // For Event (WFE) to conserve energy. The ARMv8 27610102Sali.saidi@arm.com // architecture specifies that an event is 27710102Sali.saidi@arm.com // automatically generated when clearing the exclusive 27810102Sali.saidi@arm.com // monitor to wake up the processor in WFE. 27911151Smitch.hayenga@arm.com ThreadContext* ctx = system()->getThreadContext(i->contextId); 28011151Smitch.hayenga@arm.com ctx->getCpuPtr()->wakeup(ctx->threadId()); 2819080Smatt.evans@arm.com i = lockedAddrList.erase(i); 2829080Smatt.evans@arm.com } else { 2839080Smatt.evans@arm.com i++; 2849080Smatt.evans@arm.com } 2853170SN/A } 2863170SN/A } 2873170SN/A 2889080Smatt.evans@arm.com return allowStore; 2893170SN/A} 2903170SN/A 2914626SN/A 2924626SN/A#if TRACING_ON 2934626SN/A 2949931SAli.Saidi@ARM.com#define CASE(A, T) \ 2959931SAli.Saidi@ARM.com case sizeof(T): \ 2969931SAli.Saidi@ARM.com DPRINTF(MemoryAccess,"%s from %s of size %i on address 0x%x data " \ 2979931SAli.Saidi@ARM.com "0x%x %c\n", A, system()->getMasterName(pkt->req->masterId()),\ 2989931SAli.Saidi@ARM.com pkt->getSize(), pkt->getAddr(), pkt->get<T>(), \ 2999931SAli.Saidi@ARM.com pkt->req->isUncacheable() ? 'U' : 'C'); \ 3004626SN/A break 3014626SN/A 3024626SN/A 3034626SN/A#define TRACE_PACKET(A) \ 3044626SN/A do { \ 3054626SN/A switch (pkt->getSize()) { \ 3064626SN/A CASE(A, uint64_t); \ 3074626SN/A CASE(A, uint32_t); \ 3084626SN/A CASE(A, uint16_t); \ 3094626SN/A CASE(A, uint8_t); \ 3104626SN/A default: \ 3119931SAli.Saidi@ARM.com DPRINTF(MemoryAccess, "%s from %s of size %i on address 0x%x %c\n",\ 3129931SAli.Saidi@ARM.com A, system()->getMasterName(pkt->req->masterId()), \ 3139931SAli.Saidi@ARM.com pkt->getSize(), pkt->getAddr(), \ 3149931SAli.Saidi@ARM.com pkt->req->isUncacheable() ? 'U' : 'C'); \ 31510563Sandreas.hansson@arm.com DDUMP(MemoryAccess, pkt->getConstPtr<uint8_t>(), pkt->getSize()); \ 3169931SAli.Saidi@ARM.com } \ 3174626SN/A } while (0) 3184626SN/A 3194626SN/A#else 3204626SN/A 3214626SN/A#define TRACE_PACKET(A) 3224626SN/A 3234626SN/A#endif 3244626SN/A 3258931Sandreas.hansson@arm.comvoid 3268931Sandreas.hansson@arm.comAbstractMemory::access(PacketPtr pkt) 3272413SN/A{ 32811284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 32911284Sandreas.hansson@arm.com DPRINTF(MemoryAccess, "Cache responding to %#llx: not responding\n", 3304626SN/A pkt->getAddr()); 3318931Sandreas.hansson@arm.com return; 3323175SN/A } 3334626SN/A 33411199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::CleanEvict || pkt->cmd == MemCmd::WritebackClean) { 33510883Sali.jafri@arm.com DPRINTF(MemoryAccess, "CleanEvict on 0x%x: not responding\n", 33610883Sali.jafri@arm.com pkt->getAddr()); 33710883Sali.jafri@arm.com return; 33810883Sali.jafri@arm.com } 33910883Sali.jafri@arm.com 34010883Sali.jafri@arm.com assert(AddrRange(pkt->getAddr(), 34110883Sali.jafri@arm.com pkt->getAddr() + (pkt->getSize() - 1)).isSubset(range)); 34210883Sali.jafri@arm.com 3439405Sandreas.hansson@arm.com uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start(); 3444626SN/A 3454626SN/A if (pkt->cmd == MemCmd::SwapReq) { 34611306Santhony.gutierrez@amd.com if (pkt->isAtomicOp()) { 34711306Santhony.gutierrez@amd.com if (pmemAddr) { 34811306Santhony.gutierrez@amd.com memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 34911306Santhony.gutierrez@amd.com (*(pkt->getAtomicOp()))(hostAddr); 35011306Santhony.gutierrez@amd.com } 35111306Santhony.gutierrez@amd.com } else { 35211306Santhony.gutierrez@amd.com std::vector<uint8_t> overwrite_val(pkt->getSize()); 35311306Santhony.gutierrez@amd.com uint64_t condition_val64; 35411306Santhony.gutierrez@amd.com uint32_t condition_val32; 3554040SN/A 35611306Santhony.gutierrez@amd.com if (!pmemAddr) 35711306Santhony.gutierrez@amd.com panic("Swap only works if there is real memory (i.e. null=False)"); 3584040SN/A 35911306Santhony.gutierrez@amd.com bool overwrite_mem = true; 36011306Santhony.gutierrez@amd.com // keep a copy of our possible write value, and copy what is at the 36111306Santhony.gutierrez@amd.com // memory address into the packet 36211306Santhony.gutierrez@amd.com std::memcpy(&overwrite_val[0], pkt->getConstPtr<uint8_t>(), 36311306Santhony.gutierrez@amd.com pkt->getSize()); 36411306Santhony.gutierrez@amd.com std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 3654040SN/A 36611306Santhony.gutierrez@amd.com if (pkt->req->isCondSwap()) { 36711306Santhony.gutierrez@amd.com if (pkt->getSize() == sizeof(uint64_t)) { 36811306Santhony.gutierrez@amd.com condition_val64 = pkt->req->getExtraData(); 36911306Santhony.gutierrez@amd.com overwrite_mem = !std::memcmp(&condition_val64, hostAddr, 37011306Santhony.gutierrez@amd.com sizeof(uint64_t)); 37111306Santhony.gutierrez@amd.com } else if (pkt->getSize() == sizeof(uint32_t)) { 37211306Santhony.gutierrez@amd.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 37311306Santhony.gutierrez@amd.com overwrite_mem = !std::memcmp(&condition_val32, hostAddr, 37411306Santhony.gutierrez@amd.com sizeof(uint32_t)); 37511306Santhony.gutierrez@amd.com } else 37611306Santhony.gutierrez@amd.com panic("Invalid size for conditional read/write\n"); 37711306Santhony.gutierrez@amd.com } 37811306Santhony.gutierrez@amd.com 37911306Santhony.gutierrez@amd.com if (overwrite_mem) 38011306Santhony.gutierrez@amd.com std::memcpy(hostAddr, &overwrite_val[0], pkt->getSize()); 38111306Santhony.gutierrez@amd.com 38211306Santhony.gutierrez@amd.com assert(!pkt->req->isInstFetch()); 38311306Santhony.gutierrez@amd.com TRACE_PACKET("Read/Write"); 38411306Santhony.gutierrez@amd.com numOther[pkt->req->masterId()]++; 3854040SN/A } 3864626SN/A } else if (pkt->isRead()) { 3874626SN/A assert(!pkt->isWrite()); 3886102SN/A if (pkt->isLLSC()) { 3894626SN/A trackLoadLocked(pkt); 3904040SN/A } 3915477SN/A if (pmemAddr) 3925477SN/A memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 3936429SN/A TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read"); 3949053Sdam.sunwoo@arm.com numReads[pkt->req->masterId()]++; 3959053Sdam.sunwoo@arm.com bytesRead[pkt->req->masterId()] += pkt->getSize(); 3968719SN/A if (pkt->req->isInstFetch()) 3979053Sdam.sunwoo@arm.com bytesInstRead[pkt->req->masterId()] += pkt->getSize(); 39810583SCurtis.Dunham@arm.com } else if (pkt->isInvalidate()) { 39910583SCurtis.Dunham@arm.com // no need to do anything 40010583SCurtis.Dunham@arm.com // this clause is intentionally before the write clause: the only 40110583SCurtis.Dunham@arm.com // transaction that is both a write and an invalidate is 40210583SCurtis.Dunham@arm.com // WriteInvalidate, and for the sake of consistency, it does not 40310583SCurtis.Dunham@arm.com // write to memory. in a cacheless system, there are no WriteInv's 40410583SCurtis.Dunham@arm.com // because the Write -> WriteInvalidate rewrite happens in the cache. 4054626SN/A } else if (pkt->isWrite()) { 4064626SN/A if (writeOK(pkt)) { 4079663Suri.wiener@arm.com if (pmemAddr) { 40810563Sandreas.hansson@arm.com memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize()); 4099663Suri.wiener@arm.com DPRINTF(MemoryAccess, "%s wrote %x bytes to address %x\n", 4109663Suri.wiener@arm.com __func__, pkt->getSize(), pkt->getAddr()); 4119663Suri.wiener@arm.com } 4126429SN/A assert(!pkt->req->isInstFetch()); 4134626SN/A TRACE_PACKET("Write"); 4149053Sdam.sunwoo@arm.com numWrites[pkt->req->masterId()]++; 4159053Sdam.sunwoo@arm.com bytesWritten[pkt->req->masterId()] += pkt->getSize(); 4164626SN/A } 4174040SN/A } else { 4182413SN/A panic("unimplemented"); 4192413SN/A } 4202420SN/A 4214626SN/A if (pkt->needsResponse()) { 4228931Sandreas.hansson@arm.com pkt->makeResponse(); 4234626SN/A } 4242413SN/A} 4252413SN/A 4268931Sandreas.hansson@arm.comvoid 4278931Sandreas.hansson@arm.comAbstractMemory::functionalAccess(PacketPtr pkt) 4288931Sandreas.hansson@arm.com{ 4299405Sandreas.hansson@arm.com assert(AddrRange(pkt->getAddr(), 4309405Sandreas.hansson@arm.com pkt->getAddr() + pkt->getSize() - 1).isSubset(range)); 4314626SN/A 4329405Sandreas.hansson@arm.com uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start(); 4334626SN/A 4345314SN/A if (pkt->isRead()) { 4355477SN/A if (pmemAddr) 4365477SN/A memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 4374626SN/A TRACE_PACKET("Read"); 4388931Sandreas.hansson@arm.com pkt->makeResponse(); 4395314SN/A } else if (pkt->isWrite()) { 4405477SN/A if (pmemAddr) 44110563Sandreas.hansson@arm.com memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize()); 4424626SN/A TRACE_PACKET("Write"); 4438931Sandreas.hansson@arm.com pkt->makeResponse(); 4445314SN/A } else if (pkt->isPrint()) { 4455315SN/A Packet::PrintReqState *prs = 4465315SN/A dynamic_cast<Packet::PrintReqState*>(pkt->senderState); 4478992SAli.Saidi@ARM.com assert(prs); 4485315SN/A // Need to call printLabels() explicitly since we're not going 4495315SN/A // through printObj(). 4505314SN/A prs->printLabels(); 4515315SN/A // Right now we just print the single byte at the specified address. 4525314SN/A ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *hostAddr); 4534626SN/A } else { 4548931Sandreas.hansson@arm.com panic("AbstractMemory: unimplemented functional command %s", 4554626SN/A pkt->cmdString()); 4564626SN/A } 4574490SN/A} 458