abstract_mem.cc revision 10883
12391SN/A/* 28931Sandreas.hansson@arm.com * Copyright (c) 2010-2012 ARM Limited 37733SN/A * All rights reserved 47733SN/A * 57733SN/A * The license below extends only to copyright in the software and shall 67733SN/A * not be construed as granting a license to any other intellectual 77733SN/A * property including but not limited to intellectual property relating 87733SN/A * to a hardware implementation of the functionality of the software 97733SN/A * licensed hereunder. You may use the software subject to the license 107733SN/A * terms below provided that you ensure that this notice is replicated 117733SN/A * unmodified and in its entirety in all distributions of the software, 127733SN/A * modified or unmodified, in source code or in binary form. 137733SN/A * 142391SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 152391SN/A * All rights reserved. 162391SN/A * 172391SN/A * Redistribution and use in source and binary forms, with or without 182391SN/A * modification, are permitted provided that the following conditions are 192391SN/A * met: redistributions of source code must retain the above copyright 202391SN/A * notice, this list of conditions and the following disclaimer; 212391SN/A * redistributions in binary form must reproduce the above copyright 222391SN/A * notice, this list of conditions and the following disclaimer in the 232391SN/A * documentation and/or other materials provided with the distribution; 242391SN/A * neither the name of the copyright holders nor the names of its 252391SN/A * contributors may be used to endorse or promote products derived from 262391SN/A * this software without specific prior written permission. 272391SN/A * 282391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352391SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362391SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Ron Dreslinski 412914SN/A * Ali Saidi 428931Sandreas.hansson@arm.com * Andreas Hansson 432391SN/A */ 442391SN/A 4510466Sandreas.hansson@arm.com#include <vector> 4610466Sandreas.hansson@arm.com 4710102Sali.saidi@arm.com#include "cpu/base.hh" 4810102Sali.saidi@arm.com#include "cpu/thread_context.hh" 498232SN/A#include "debug/LLSC.hh" 508232SN/A#include "debug/MemoryAccess.hh" 518931Sandreas.hansson@arm.com#include "mem/abstract_mem.hh" 523879SN/A#include "mem/packet_access.hh" 539053Sdam.sunwoo@arm.com#include "sim/system.hh" 542394SN/A 552391SN/Ausing namespace std; 562391SN/A 578931Sandreas.hansson@arm.comAbstractMemory::AbstractMemory(const Params *p) : 588931Sandreas.hansson@arm.com MemObject(p), range(params()->range), pmemAddr(NULL), 599053Sdam.sunwoo@arm.com confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map), 609053Sdam.sunwoo@arm.com _system(NULL) 612391SN/A{ 6210466Sandreas.hansson@arm.com} 6310466Sandreas.hansson@arm.com 6410466Sandreas.hansson@arm.comvoid 6510466Sandreas.hansson@arm.comAbstractMemory::init() 6610466Sandreas.hansson@arm.com{ 6710466Sandreas.hansson@arm.com assert(system()); 6810466Sandreas.hansson@arm.com 6910466Sandreas.hansson@arm.com if (size() % _system->getPageBytes() != 0) 702391SN/A panic("Memory Size not divisible by page size\n"); 712391SN/A} 722391SN/A 739293Sandreas.hansson@arm.comvoid 749293Sandreas.hansson@arm.comAbstractMemory::setBackingStore(uint8_t* pmem_addr) 752391SN/A{ 769293Sandreas.hansson@arm.com pmemAddr = pmem_addr; 772391SN/A} 782391SN/A 798719SN/Avoid 808931Sandreas.hansson@arm.comAbstractMemory::regStats() 818719SN/A{ 828719SN/A using namespace Stats; 838719SN/A 849053Sdam.sunwoo@arm.com assert(system()); 859053Sdam.sunwoo@arm.com 868719SN/A bytesRead 879053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 888719SN/A .name(name() + ".bytes_read") 898719SN/A .desc("Number of bytes read from this memory") 909053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 918719SN/A ; 929053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 939053Sdam.sunwoo@arm.com bytesRead.subname(i, system()->getMasterName(i)); 949053Sdam.sunwoo@arm.com } 958719SN/A bytesInstRead 969053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 978719SN/A .name(name() + ".bytes_inst_read") 988719SN/A .desc("Number of instructions bytes read from this memory") 999053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1008719SN/A ; 1019053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1029053Sdam.sunwoo@arm.com bytesInstRead.subname(i, system()->getMasterName(i)); 1039053Sdam.sunwoo@arm.com } 1048719SN/A bytesWritten 1059053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1068719SN/A .name(name() + ".bytes_written") 1078719SN/A .desc("Number of bytes written to this memory") 1089053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1098719SN/A ; 1109053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1119053Sdam.sunwoo@arm.com bytesWritten.subname(i, system()->getMasterName(i)); 1129053Sdam.sunwoo@arm.com } 1138719SN/A numReads 1149053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1158719SN/A .name(name() + ".num_reads") 1168719SN/A .desc("Number of read requests responded to by this memory") 1179053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1188719SN/A ; 1199053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1209053Sdam.sunwoo@arm.com numReads.subname(i, system()->getMasterName(i)); 1219053Sdam.sunwoo@arm.com } 1228719SN/A numWrites 1239053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1248719SN/A .name(name() + ".num_writes") 1258719SN/A .desc("Number of write requests responded to by this memory") 1269053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1278719SN/A ; 1289053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1299053Sdam.sunwoo@arm.com numWrites.subname(i, system()->getMasterName(i)); 1309053Sdam.sunwoo@arm.com } 1318719SN/A numOther 1329053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1338719SN/A .name(name() + ".num_other") 1348719SN/A .desc("Number of other requests responded to by this memory") 1359053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1368719SN/A ; 1379053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1389053Sdam.sunwoo@arm.com numOther.subname(i, system()->getMasterName(i)); 1399053Sdam.sunwoo@arm.com } 1408719SN/A bwRead 1418719SN/A .name(name() + ".bw_read") 1428719SN/A .desc("Total read bandwidth from this memory (bytes/s)") 1438719SN/A .precision(0) 1448719SN/A .prereq(bytesRead) 1459053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1468719SN/A ; 1479053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1489053Sdam.sunwoo@arm.com bwRead.subname(i, system()->getMasterName(i)); 1499053Sdam.sunwoo@arm.com } 1509053Sdam.sunwoo@arm.com 1518719SN/A bwInstRead 1528719SN/A .name(name() + ".bw_inst_read") 1538719SN/A .desc("Instruction read bandwidth from this memory (bytes/s)") 1548719SN/A .precision(0) 1558719SN/A .prereq(bytesInstRead) 1569053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1578719SN/A ; 1589053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1599053Sdam.sunwoo@arm.com bwInstRead.subname(i, system()->getMasterName(i)); 1609053Sdam.sunwoo@arm.com } 1618719SN/A bwWrite 1628719SN/A .name(name() + ".bw_write") 1638719SN/A .desc("Write bandwidth from this memory (bytes/s)") 1648719SN/A .precision(0) 1658719SN/A .prereq(bytesWritten) 1669053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1678719SN/A ; 1689053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1699053Sdam.sunwoo@arm.com bwWrite.subname(i, system()->getMasterName(i)); 1709053Sdam.sunwoo@arm.com } 1718719SN/A bwTotal 1728719SN/A .name(name() + ".bw_total") 1738719SN/A .desc("Total bandwidth to/from this memory (bytes/s)") 1748719SN/A .precision(0) 1758719SN/A .prereq(bwTotal) 1769053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1778719SN/A ; 1789053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1799053Sdam.sunwoo@arm.com bwTotal.subname(i, system()->getMasterName(i)); 1809053Sdam.sunwoo@arm.com } 1818719SN/A bwRead = bytesRead / simSeconds; 1828719SN/A bwInstRead = bytesInstRead / simSeconds; 1838719SN/A bwWrite = bytesWritten / simSeconds; 1848719SN/A bwTotal = (bytesRead + bytesWritten) / simSeconds; 1858719SN/A} 1868719SN/A 1879235Sandreas.hansson@arm.comAddrRange 1889098Sandreas.hansson@arm.comAbstractMemory::getAddrRange() const 1892408SN/A{ 1908931Sandreas.hansson@arm.com return range; 1912408SN/A} 1922408SN/A 1933170SN/A// Add load-locked to tracking list. Should only be called if the 1946076SN/A// operation is a load and the LLSC flag is set. 1953170SN/Avoid 1968931Sandreas.hansson@arm.comAbstractMemory::trackLoadLocked(PacketPtr pkt) 1973170SN/A{ 1984626SN/A Request *req = pkt->req; 1993170SN/A Addr paddr = LockedAddr::mask(req->getPaddr()); 2003170SN/A 2013170SN/A // first we check if we already have a locked addr for this 2023170SN/A // xc. Since each xc only gets one, we just update the 2033170SN/A // existing record with the new address. 2043170SN/A list<LockedAddr>::iterator i; 2053170SN/A 2063170SN/A for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) { 2073170SN/A if (i->matchesContext(req)) { 2085714SN/A DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n", 2095714SN/A req->contextId(), paddr); 2103170SN/A i->addr = paddr; 2113170SN/A return; 2123170SN/A } 2133170SN/A } 2143170SN/A 2153170SN/A // no record for this xc: need to allocate a new one 2165714SN/A DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n", 2175714SN/A req->contextId(), paddr); 2183170SN/A lockedAddrList.push_front(LockedAddr(req)); 2193170SN/A} 2203170SN/A 2213170SN/A 2223170SN/A// Called on *writes* only... both regular stores and 2233170SN/A// store-conditional operations. Check for conventional stores which 2243170SN/A// conflict with locked addresses, and for success/failure of store 2253170SN/A// conditionals. 2263170SN/Abool 2278931Sandreas.hansson@arm.comAbstractMemory::checkLockedAddrList(PacketPtr pkt) 2283170SN/A{ 2294626SN/A Request *req = pkt->req; 2303170SN/A Addr paddr = LockedAddr::mask(req->getPaddr()); 2316102SN/A bool isLLSC = pkt->isLLSC(); 2323170SN/A 2333170SN/A // Initialize return value. Non-conditional stores always 2343170SN/A // succeed. Assume conditional stores will fail until proven 2353170SN/A // otherwise. 2369080Smatt.evans@arm.com bool allowStore = !isLLSC; 2373170SN/A 2389080Smatt.evans@arm.com // Iterate over list. Note that there could be multiple matching records, 2399080Smatt.evans@arm.com // as more than one context could have done a load locked to this location. 2409080Smatt.evans@arm.com // Only remove records when we succeed in finding a record for (xc, addr); 2419080Smatt.evans@arm.com // then, remove all records with this address. Failed store-conditionals do 2429080Smatt.evans@arm.com // not blow unrelated reservations. 2433170SN/A list<LockedAddr>::iterator i = lockedAddrList.begin(); 2443170SN/A 2459080Smatt.evans@arm.com if (isLLSC) { 2469080Smatt.evans@arm.com while (i != lockedAddrList.end()) { 2479080Smatt.evans@arm.com if (i->addr == paddr && i->matchesContext(req)) { 2489080Smatt.evans@arm.com // it's a store conditional, and as far as the memory system can 2499080Smatt.evans@arm.com // tell, the requesting context's lock is still valid. 2505714SN/A DPRINTF(LLSC, "StCond success: context %d addr %#x\n", 2515714SN/A req->contextId(), paddr); 2529080Smatt.evans@arm.com allowStore = true; 2539080Smatt.evans@arm.com break; 2543170SN/A } 2559080Smatt.evans@arm.com // If we didn't find a match, keep searching! Someone else may well 2569080Smatt.evans@arm.com // have a reservation on this line here but we may find ours in just 2579080Smatt.evans@arm.com // a little while. 2589080Smatt.evans@arm.com i++; 2593170SN/A } 2609080Smatt.evans@arm.com req->setExtraData(allowStore ? 1 : 0); 2619080Smatt.evans@arm.com } 2629080Smatt.evans@arm.com // LLSCs that succeeded AND non-LLSC stores both fall into here: 2639080Smatt.evans@arm.com if (allowStore) { 2649080Smatt.evans@arm.com // We write address paddr. However, there may be several entries with a 2659080Smatt.evans@arm.com // reservation on this address (for other contextIds) and they must all 2669080Smatt.evans@arm.com // be removed. 2679080Smatt.evans@arm.com i = lockedAddrList.begin(); 2689080Smatt.evans@arm.com while (i != lockedAddrList.end()) { 2699080Smatt.evans@arm.com if (i->addr == paddr) { 2709080Smatt.evans@arm.com DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n", 2719080Smatt.evans@arm.com i->contextId, paddr); 27210102Sali.saidi@arm.com // For ARM, a spinlock would typically include a Wait 27310102Sali.saidi@arm.com // For Event (WFE) to conserve energy. The ARMv8 27410102Sali.saidi@arm.com // architecture specifies that an event is 27510102Sali.saidi@arm.com // automatically generated when clearing the exclusive 27610102Sali.saidi@arm.com // monitor to wake up the processor in WFE. 27710102Sali.saidi@arm.com system()->getThreadContext(i->contextId)->getCpuPtr()->wakeup(); 2789080Smatt.evans@arm.com i = lockedAddrList.erase(i); 2799080Smatt.evans@arm.com } else { 2809080Smatt.evans@arm.com i++; 2819080Smatt.evans@arm.com } 2823170SN/A } 2833170SN/A } 2843170SN/A 2859080Smatt.evans@arm.com return allowStore; 2863170SN/A} 2873170SN/A 2884626SN/A 2894626SN/A#if TRACING_ON 2904626SN/A 2919931SAli.Saidi@ARM.com#define CASE(A, T) \ 2929931SAli.Saidi@ARM.com case sizeof(T): \ 2939931SAli.Saidi@ARM.com DPRINTF(MemoryAccess,"%s from %s of size %i on address 0x%x data " \ 2949931SAli.Saidi@ARM.com "0x%x %c\n", A, system()->getMasterName(pkt->req->masterId()),\ 2959931SAli.Saidi@ARM.com pkt->getSize(), pkt->getAddr(), pkt->get<T>(), \ 2969931SAli.Saidi@ARM.com pkt->req->isUncacheable() ? 'U' : 'C'); \ 2974626SN/A break 2984626SN/A 2994626SN/A 3004626SN/A#define TRACE_PACKET(A) \ 3014626SN/A do { \ 3024626SN/A switch (pkt->getSize()) { \ 3034626SN/A CASE(A, uint64_t); \ 3044626SN/A CASE(A, uint32_t); \ 3054626SN/A CASE(A, uint16_t); \ 3064626SN/A CASE(A, uint8_t); \ 3074626SN/A default: \ 3089931SAli.Saidi@ARM.com DPRINTF(MemoryAccess, "%s from %s of size %i on address 0x%x %c\n",\ 3099931SAli.Saidi@ARM.com A, system()->getMasterName(pkt->req->masterId()), \ 3109931SAli.Saidi@ARM.com pkt->getSize(), pkt->getAddr(), \ 3119931SAli.Saidi@ARM.com pkt->req->isUncacheable() ? 'U' : 'C'); \ 31210563Sandreas.hansson@arm.com DDUMP(MemoryAccess, pkt->getConstPtr<uint8_t>(), pkt->getSize()); \ 3139931SAli.Saidi@ARM.com } \ 3144626SN/A } while (0) 3154626SN/A 3164626SN/A#else 3174626SN/A 3184626SN/A#define TRACE_PACKET(A) 3194626SN/A 3204626SN/A#endif 3214626SN/A 3228931Sandreas.hansson@arm.comvoid 3238931Sandreas.hansson@arm.comAbstractMemory::access(PacketPtr pkt) 3242413SN/A{ 3254626SN/A if (pkt->memInhibitAsserted()) { 3264626SN/A DPRINTF(MemoryAccess, "mem inhibited on 0x%x: not responding\n", 3274626SN/A pkt->getAddr()); 3288931Sandreas.hansson@arm.com return; 3293175SN/A } 3304626SN/A 33110883Sali.jafri@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 33210883Sali.jafri@arm.com DPRINTF(MemoryAccess, "CleanEvict on 0x%x: not responding\n", 33310883Sali.jafri@arm.com pkt->getAddr()); 33410883Sali.jafri@arm.com return; 33510883Sali.jafri@arm.com } 33610883Sali.jafri@arm.com 33710883Sali.jafri@arm.com assert(AddrRange(pkt->getAddr(), 33810883Sali.jafri@arm.com pkt->getAddr() + (pkt->getSize() - 1)).isSubset(range)); 33910883Sali.jafri@arm.com 3409405Sandreas.hansson@arm.com uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start(); 3414626SN/A 3424626SN/A if (pkt->cmd == MemCmd::SwapReq) { 34310466Sandreas.hansson@arm.com std::vector<uint8_t> overwrite_val(pkt->getSize()); 3444040SN/A uint64_t condition_val64; 3454040SN/A uint32_t condition_val32; 3464040SN/A 3475477SN/A if (!pmemAddr) 3485477SN/A panic("Swap only works if there is real memory (i.e. null=False)"); 3494040SN/A 35010466Sandreas.hansson@arm.com bool overwrite_mem = true; 3514040SN/A // keep a copy of our possible write value, and copy what is at the 3524040SN/A // memory address into the packet 35310563Sandreas.hansson@arm.com std::memcpy(&overwrite_val[0], pkt->getConstPtr<uint8_t>(), 35410563Sandreas.hansson@arm.com pkt->getSize()); 3554626SN/A std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 3564040SN/A 3574040SN/A if (pkt->req->isCondSwap()) { 3584040SN/A if (pkt->getSize() == sizeof(uint64_t)) { 3594052SN/A condition_val64 = pkt->req->getExtraData(); 3604626SN/A overwrite_mem = !std::memcmp(&condition_val64, hostAddr, 3614626SN/A sizeof(uint64_t)); 3624040SN/A } else if (pkt->getSize() == sizeof(uint32_t)) { 3634052SN/A condition_val32 = (uint32_t)pkt->req->getExtraData(); 3644626SN/A overwrite_mem = !std::memcmp(&condition_val32, hostAddr, 3654626SN/A sizeof(uint32_t)); 3664040SN/A } else 3674040SN/A panic("Invalid size for conditional read/write\n"); 3684040SN/A } 3694040SN/A 3704040SN/A if (overwrite_mem) 37110466Sandreas.hansson@arm.com std::memcpy(hostAddr, &overwrite_val[0], pkt->getSize()); 3724040SN/A 3736429SN/A assert(!pkt->req->isInstFetch()); 3744626SN/A TRACE_PACKET("Read/Write"); 3759053Sdam.sunwoo@arm.com numOther[pkt->req->masterId()]++; 3764626SN/A } else if (pkt->isRead()) { 3774626SN/A assert(!pkt->isWrite()); 3786102SN/A if (pkt->isLLSC()) { 3794626SN/A trackLoadLocked(pkt); 3804040SN/A } 3815477SN/A if (pmemAddr) 3825477SN/A memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 3836429SN/A TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read"); 3849053Sdam.sunwoo@arm.com numReads[pkt->req->masterId()]++; 3859053Sdam.sunwoo@arm.com bytesRead[pkt->req->masterId()] += pkt->getSize(); 3868719SN/A if (pkt->req->isInstFetch()) 3879053Sdam.sunwoo@arm.com bytesInstRead[pkt->req->masterId()] += pkt->getSize(); 38810583SCurtis.Dunham@arm.com } else if (pkt->isInvalidate()) { 38910583SCurtis.Dunham@arm.com // no need to do anything 39010583SCurtis.Dunham@arm.com // this clause is intentionally before the write clause: the only 39110583SCurtis.Dunham@arm.com // transaction that is both a write and an invalidate is 39210583SCurtis.Dunham@arm.com // WriteInvalidate, and for the sake of consistency, it does not 39310583SCurtis.Dunham@arm.com // write to memory. in a cacheless system, there are no WriteInv's 39410583SCurtis.Dunham@arm.com // because the Write -> WriteInvalidate rewrite happens in the cache. 3954626SN/A } else if (pkt->isWrite()) { 3964626SN/A if (writeOK(pkt)) { 3979663Suri.wiener@arm.com if (pmemAddr) { 39810563Sandreas.hansson@arm.com memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize()); 3999663Suri.wiener@arm.com DPRINTF(MemoryAccess, "%s wrote %x bytes to address %x\n", 4009663Suri.wiener@arm.com __func__, pkt->getSize(), pkt->getAddr()); 4019663Suri.wiener@arm.com } 4026429SN/A assert(!pkt->req->isInstFetch()); 4034626SN/A TRACE_PACKET("Write"); 4049053Sdam.sunwoo@arm.com numWrites[pkt->req->masterId()]++; 4059053Sdam.sunwoo@arm.com bytesWritten[pkt->req->masterId()] += pkt->getSize(); 4064626SN/A } 4074040SN/A } else { 4082413SN/A panic("unimplemented"); 4092413SN/A } 4102420SN/A 4114626SN/A if (pkt->needsResponse()) { 4128931Sandreas.hansson@arm.com pkt->makeResponse(); 4134626SN/A } 4142413SN/A} 4152413SN/A 4168931Sandreas.hansson@arm.comvoid 4178931Sandreas.hansson@arm.comAbstractMemory::functionalAccess(PacketPtr pkt) 4188931Sandreas.hansson@arm.com{ 4199405Sandreas.hansson@arm.com assert(AddrRange(pkt->getAddr(), 4209405Sandreas.hansson@arm.com pkt->getAddr() + pkt->getSize() - 1).isSubset(range)); 4214626SN/A 4229405Sandreas.hansson@arm.com uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start(); 4234626SN/A 4245314SN/A if (pkt->isRead()) { 4255477SN/A if (pmemAddr) 4265477SN/A memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 4274626SN/A TRACE_PACKET("Read"); 4288931Sandreas.hansson@arm.com pkt->makeResponse(); 4295314SN/A } else if (pkt->isWrite()) { 4305477SN/A if (pmemAddr) 43110563Sandreas.hansson@arm.com memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize()); 4324626SN/A TRACE_PACKET("Write"); 4338931Sandreas.hansson@arm.com pkt->makeResponse(); 4345314SN/A } else if (pkt->isPrint()) { 4355315SN/A Packet::PrintReqState *prs = 4365315SN/A dynamic_cast<Packet::PrintReqState*>(pkt->senderState); 4378992SAli.Saidi@ARM.com assert(prs); 4385315SN/A // Need to call printLabels() explicitly since we're not going 4395315SN/A // through printObj(). 4405314SN/A prs->printLabels(); 4415315SN/A // Right now we just print the single byte at the specified address. 4425314SN/A ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *hostAddr); 4434626SN/A } else { 4448931Sandreas.hansson@arm.com panic("AbstractMemory: unimplemented functional command %s", 4454626SN/A pkt->cmdString()); 4464626SN/A } 4474490SN/A} 448