xref: /gem5/src/mem/SerialLink.py

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# Copyright (c) 2015 The University of Bologna
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# Authors: Ali Saidi
#          Andreas Hansson
#          Erfan Azarkhish

from m5.params import *
from MemObject import MemObject

# SerialLink is a simple variation of the Bridge class, with the ability to
# account for the latency of packet serialization.

class SerialLink(MemObject):
    type = 'SerialLink'
    cxx_header = "mem/serial_link.hh"
    slave = SlavePort('Slave port')
    master = MasterPort('Master port')
    req_size = Param.Unsigned(16, "The number of requests to buffer")
    resp_size = Param.Unsigned(16, "The number of responses to buffer")
    delay = Param.Latency('0ns', "The latency of this serial_link")
    ranges = VectorParam.AddrRange([AllMemory],
                            "Address ranges to pass through the serial_link")
    # Bandwidth of the serial link is determined by the clock domain which the
    #  link belongs to and the number of lanes:
    num_lanes = Param.Unsigned(1, "Number of parallel lanes inside the serial"
        "link. (aka. lane width)")