SConscript revision 8762 
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Nathan Binkert
30
31Import('*')
32
33SimObject('Bridge.py')
34SimObject('Bus.py')
35SimObject('MemObject.py')
36
37Source('bridge.cc')
38Source('bus.cc')
39Source('mem_object.cc')
40Source('mport.cc')
41Source('packet.cc')
42Source('port.cc')
43Source('tport.cc')
44Source('vport.cc')
45
46if env['TARGET_ISA'] != 'no':
47    SimObject('PhysicalMemory.py')
48    Source('dram.cc')
49    Source('physical.cc')
50    Source('translating_port.cc')
51
52if not env['FULL_SYSTEM'] and env['TARGET_ISA'] != 'no':
53    Source('page_table.cc')
54
55DebugFlag('Bus')
56DebugFlag('BusAddrRanges')
57DebugFlag('BusBridge')
58DebugFlag('LLSC')
59DebugFlag('MMU')
60DebugFlag('MemoryAccess')
61
62DebugFlag('ProtocolTrace')
63DebugFlag('RubyCache')
64DebugFlag('RubyDma')
65DebugFlag('RubyGenerated')
66DebugFlag('RubyMemory')
67DebugFlag('RubyNetwork')
68DebugFlag('RubyPort')
69DebugFlag('RubyQueue')
70DebugFlag('RubySlicc')
71DebugFlag('RubyStorebuffer')
72DebugFlag('RubyTester')
73
74CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
75    'RubyGenerated', 'RubySlicc', 'RubyStorebuffer', 'RubyCache', 
76    'RubyMemory', 'RubyDma', 'RubyPort'])
77