SConscript revision 11765 
12086SN/A# -*- mode:python -*-
22086SN/A
32086SN/A# Copyright (c) 2006 The Regents of The University of Michigan
42086SN/A# All rights reserved.
52086SN/A#
62086SN/A# Redistribution and use in source and binary forms, with or without
72086SN/A# modification, are permitted provided that the following conditions are
82086SN/A# met: redistributions of source code must retain the above copyright
92086SN/A# notice, this list of conditions and the following disclaimer;
102086SN/A# redistributions in binary form must reproduce the above copyright
112086SN/A# notice, this list of conditions and the following disclaimer in the
122086SN/A# documentation and/or other materials provided with the distribution;
132086SN/A# neither the name of the copyright holders nor the names of its
142086SN/A# contributors may be used to endorse or promote products derived from
152086SN/A# this software without specific prior written permission.
162086SN/A#
172086SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182086SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192086SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202086SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212086SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
222086SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
232086SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
242086SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
252086SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
262086SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272086SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282665Ssaidi@eecs.umich.edu#
292665Ssaidi@eecs.umich.edu# Authors: Nathan Binkert
302665Ssaidi@eecs.umich.edu
312086SN/AImport('*')
324202Sbinkertn@umich.edu
332086SN/ASimObject('CommMonitor.py')
344202Sbinkertn@umich.eduSource('comm_monitor.cc')
354202Sbinkertn@umich.edu
369022Sgblack@eecs.umich.eduSimObject('AbstractMemory.py')
374202Sbinkertn@umich.eduSimObject('AddrMapper.py')
388745Sgblack@eecs.umich.eduSimObject('Bridge.py')
396313Sgblack@eecs.umich.eduSimObject('DRAMCtrl.py')
408778Sgblack@eecs.umich.eduSimObject('ExternalMaster.py')
418778Sgblack@eecs.umich.eduSimObject('ExternalSlave.py')
428778Sgblack@eecs.umich.eduSimObject('MemObject.py')
436365Sgblack@eecs.umich.eduSimObject('SimpleMemory.py')
444997Sgblack@eecs.umich.eduSimObject('XBar.py')
458778Sgblack@eecs.umich.eduSimObject('HMCController.py')
464202Sbinkertn@umich.eduSimObject('SerialLink.py')
478778Sgblack@eecs.umich.edu
488778Sgblack@eecs.umich.eduSource('abstract_mem.cc')
498778Sgblack@eecs.umich.eduSource('addr_mapper.cc')
504997Sgblack@eecs.umich.eduSource('bridge.cc')
518747Sgblack@eecs.umich.eduSource('coherent_xbar.cc')
524826Ssaidi@eecs.umich.eduSource('drampower.cc')
538760Sgblack@eecs.umich.eduSource('dram_ctrl.cc')
542086SN/ASource('external_master.cc')
558745Sgblack@eecs.umich.eduSource('external_slave.cc')
569384SAndreas.Sandberg@arm.comSource('mem_object.cc')
576365Sgblack@eecs.umich.eduSource('mport.cc')
588778Sgblack@eecs.umich.eduSource('noncoherent_xbar.cc')
598745Sgblack@eecs.umich.eduSource('packet.cc')
606365Sgblack@eecs.umich.eduSource('port.cc')
618335Snate@binkert.orgSource('packet_queue.cc')
628335Snate@binkert.orgSource('port_proxy.cc')
634997Sgblack@eecs.umich.eduSource('physical.cc')
644202Sbinkertn@umich.eduSource('simple_mem.cc')
654202Sbinkertn@umich.eduSource('snoop_filter.cc')
664202Sbinkertn@umich.eduSource('stack_dist_calc.cc')
674202Sbinkertn@umich.eduSource('tport.cc')
684202Sbinkertn@umich.eduSource('xbar.cc')
694202Sbinkertn@umich.eduSource('hmc_controller.cc')
70Source('serial_link.cc')
71
72if env['TARGET_ISA'] != 'null':
73    Source('fs_translating_port_proxy.cc')
74    Source('se_translating_port_proxy.cc')
75    Source('page_table.cc')
76if env['TARGET_ISA'] == 'x86':
77    Source('multi_level_page_table.cc')
78
79if env['HAVE_DRAMSIM']:
80    SimObject('DRAMSim2.py')
81    Source('dramsim2_wrapper.cc')
82    Source('dramsim2.cc')
83
84SimObject('MemChecker.py')
85Source('mem_checker.cc')
86Source('mem_checker_monitor.cc')
87
88DebugFlag('AddrRanges')
89DebugFlag('BaseXBar')
90DebugFlag('CoherentXBar')
91DebugFlag('NoncoherentXBar')
92DebugFlag('SnoopFilter')
93CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
94                      'SnoopFilter'])
95
96DebugFlag('Bridge')
97DebugFlag('CommMonitor')
98DebugFlag('DRAM')
99DebugFlag('DRAMPower')
100DebugFlag('DRAMState')
101DebugFlag('ExternalPort')
102DebugFlag('LLSC')
103DebugFlag('MMU')
104DebugFlag('MemoryAccess')
105DebugFlag('PacketQueue')
106DebugFlag('StackDist')
107DebugFlag("DRAMSim2")
108DebugFlag('HMCController')
109DebugFlag('SerialLink')
110
111DebugFlag("MemChecker")
112DebugFlag("MemCheckerMonitor")
113