SConscript revision 10405 
14202Sbinkertn@umich.edu# -*- mode:python -*-
24202Sbinkertn@umich.edu
34202Sbinkertn@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan
44202Sbinkertn@umich.edu# All rights reserved.
54202Sbinkertn@umich.edu#
64202Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without
74202Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are
84202Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright
94202Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer;
104202Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright
114202Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the
124202Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution;
134202Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its
144202Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from
154202Sbinkertn@umich.edu# this software without specific prior written permission.
164202Sbinkertn@umich.edu#
174202Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
184202Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
194202Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
204202Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
214202Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
224202Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
234202Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
244202Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
254202Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
264202Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
274202Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
284202Sbinkertn@umich.edu#
294202Sbinkertn@umich.edu# Authors: Nathan Binkert
304202Sbinkertn@umich.edu
314202Sbinkertn@umich.eduImport('*')
324202Sbinkertn@umich.edu
335628Sgblack@eecs.umich.edu# Only build the communication if we have support for protobuf as the
344486Sbinkertn@umich.edu# tracing relies on it
354776Sgblack@eecs.umich.eduif env['HAVE_PROTOBUF']:
364486Sbinkertn@umich.edu    SimObject('CommMonitor.py')
378774Sgblack@eecs.umich.edu    Source('comm_monitor.cc')
384202Sbinkertn@umich.edu
394202Sbinkertn@umich.eduSimObject('AbstractMemory.py')
404202Sbinkertn@umich.eduSimObject('AddrMapper.py')
414202Sbinkertn@umich.eduSimObject('Bridge.py')
425522Snate@binkert.orgSimObject('DRAMCtrl.py')
438233Snate@binkert.orgSimObject('MemObject.py')
444202Sbinkertn@umich.eduSimObject('SimpleMemory.py')
454202Sbinkertn@umich.eduSimObject('XBar.py')
464202Sbinkertn@umich.edu
474202Sbinkertn@umich.eduSource('abstract_mem.cc')
484202Sbinkertn@umich.eduSource('addr_mapper.cc')
494202Sbinkertn@umich.eduSource('bridge.cc')
508770Sgblack@eecs.umich.eduSource('coherent_xbar.cc')
517768SAli.Saidi@ARM.comSource('dram_ctrl.cc')
527768SAli.Saidi@ARM.comSource('mem_object.cc')
538766Sgblack@eecs.umich.eduSource('mport.cc')
547768SAli.Saidi@ARM.comSource('noncoherent_xbar.cc')
557768SAli.Saidi@ARM.comSource('packet.cc')
568766Sgblack@eecs.umich.eduSource('port.cc')
577768SAli.Saidi@ARM.comSource('packet_queue.cc')
587768SAli.Saidi@ARM.comSource('port_proxy.cc')
594202Sbinkertn@umich.eduSource('physical.cc')
608784Sgblack@eecs.umich.eduSource('simple_mem.cc')
615016Sgblack@eecs.umich.eduSource('snoop_filter.cc')
624486Sbinkertn@umich.eduSource('tport.cc')
638335Snate@binkert.orgSource('xbar.cc')
648335Snate@binkert.org
658335Snate@binkert.orgif env['TARGET_ISA'] != 'null':
668335Snate@binkert.org    Source('fs_translating_port_proxy.cc')
678335Snate@binkert.org    Source('se_translating_port_proxy.cc')
688335Snate@binkert.org    Source('page_table.cc')
698335Snate@binkert.orgif env['TARGET_ISA'] == 'x86':
708335Snate@binkert.org    Source('multi_level_page_table.cc')
718335Snate@binkert.org
728335Snate@binkert.orgif env['HAVE_DRAMSIM']:
738335Snate@binkert.org    SimObject('DRAMSim2.py')
748335Snate@binkert.org    Source('dramsim2_wrapper.cc')
758335Snate@binkert.org    Source('dramsim2.cc')
768335Snate@binkert.org
778335Snate@binkert.orgDebugFlag('AddrRanges')
788335Snate@binkert.orgDebugFlag('BaseXBar')
798335Snate@binkert.orgDebugFlag('CoherentXBar')
80DebugFlag('NoncoherentXBar')
81DebugFlag('SnoopFilter')
82CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
83                      'SnoopFilter'])
84
85DebugFlag('Bridge')
86DebugFlag('CommMonitor')
87DebugFlag('DRAM')
88DebugFlag('DRAMPower')
89DebugFlag('DRAMState')
90DebugFlag('LLSC')
91DebugFlag('MMU')
92DebugFlag('MemoryAccess')
93DebugFlag('PacketQueue')
94
95DebugFlag("DRAMSim2")
96