SConscript revision 10391
110235Syasuko.eckert@amd.com# -*- mode:python -*- 210235Syasuko.eckert@amd.com 310235Syasuko.eckert@amd.com# Copyright (c) 2006 The Regents of The University of Michigan 410235Syasuko.eckert@amd.com# All rights reserved. 510235Syasuko.eckert@amd.com# 610235Syasuko.eckert@amd.com# Redistribution and use in source and binary forms, with or without 710235Syasuko.eckert@amd.com# modification, are permitted provided that the following conditions are 810235Syasuko.eckert@amd.com# met: redistributions of source code must retain the above copyright 910235Syasuko.eckert@amd.com# notice, this list of conditions and the following disclaimer; 1010235Syasuko.eckert@amd.com# redistributions in binary form must reproduce the above copyright 1110235Syasuko.eckert@amd.com# notice, this list of conditions and the following disclaimer in the 1210235Syasuko.eckert@amd.com# documentation and/or other materials provided with the distribution; 1310235Syasuko.eckert@amd.com# neither the name of the copyright holders nor the names of its 1410235Syasuko.eckert@amd.com# contributors may be used to endorse or promote products derived from 1510235Syasuko.eckert@amd.com# this software without specific prior written permission. 1610235Syasuko.eckert@amd.com# 1710235Syasuko.eckert@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1810235Syasuko.eckert@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1910235Syasuko.eckert@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2010235Syasuko.eckert@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2110235Syasuko.eckert@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2210235Syasuko.eckert@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2310235Syasuko.eckert@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2410235Syasuko.eckert@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2510235Syasuko.eckert@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2610235Syasuko.eckert@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2710235Syasuko.eckert@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2810235Syasuko.eckert@amd.com# 2910235Syasuko.eckert@amd.com# Authors: Nathan Binkert 3010235Syasuko.eckert@amd.com 3110235Syasuko.eckert@amd.comImport('*') 3210235Syasuko.eckert@amd.com 3310235Syasuko.eckert@amd.com# Only build the communication if we have support for protobuf as the 3410235Syasuko.eckert@amd.com# tracing relies on it 3510235Syasuko.eckert@amd.comif env['HAVE_PROTOBUF']: 3610235Syasuko.eckert@amd.com SimObject('CommMonitor.py') 3710235Syasuko.eckert@amd.com Source('comm_monitor.cc') 3810235Syasuko.eckert@amd.com 3910235Syasuko.eckert@amd.comSimObject('AbstractMemory.py') 4010235Syasuko.eckert@amd.comSimObject('AddrMapper.py') 4110235Syasuko.eckert@amd.comSimObject('Bridge.py') 4210235Syasuko.eckert@amd.comSimObject('Bus.py') 4310235Syasuko.eckert@amd.comSimObject('DRAMCtrl.py') 4410235Syasuko.eckert@amd.comSimObject('MemObject.py') 4510235Syasuko.eckert@amd.comSimObject('SimpleMemory.py') 4610235Syasuko.eckert@amd.com 4710235Syasuko.eckert@amd.comSource('abstract_mem.cc') 4810235Syasuko.eckert@amd.comSource('addr_mapper.cc') 4910235Syasuko.eckert@amd.comSource('bridge.cc') 5010235Syasuko.eckert@amd.comSource('bus.cc') 5110235Syasuko.eckert@amd.comSource('coherent_bus.cc') 5210235Syasuko.eckert@amd.comSource('dram_ctrl.cc') 5310235Syasuko.eckert@amd.comSource('mem_object.cc') 5410235Syasuko.eckert@amd.comSource('mport.cc') 5510235Syasuko.eckert@amd.comSource('noncoherent_bus.cc') 5610235Syasuko.eckert@amd.comSource('packet.cc') 5710235Syasuko.eckert@amd.comSource('port.cc') 5810235Syasuko.eckert@amd.comSource('packet_queue.cc') 5910235Syasuko.eckert@amd.comSource('tport.cc') 6010235Syasuko.eckert@amd.comSource('port_proxy.cc') 6110235Syasuko.eckert@amd.comSource('simple_mem.cc') 6210235Syasuko.eckert@amd.comSource('physical.cc') 6310235Syasuko.eckert@amd.com 6410235Syasuko.eckert@amd.comif env['TARGET_ISA'] != 'null': 6510235Syasuko.eckert@amd.com Source('fs_translating_port_proxy.cc') 6610235Syasuko.eckert@amd.com Source('se_translating_port_proxy.cc') 6710235Syasuko.eckert@amd.com Source('page_table.cc') 6810235Syasuko.eckert@amd.comif env['TARGET_ISA'] == 'x86': 6910235Syasuko.eckert@amd.com Source('multi_level_page_table.cc') 7010235Syasuko.eckert@amd.com 7110235Syasuko.eckert@amd.comif env['HAVE_DRAMSIM']: 7210235Syasuko.eckert@amd.com SimObject('DRAMSim2.py') 7310235Syasuko.eckert@amd.com Source('dramsim2_wrapper.cc') 7410235Syasuko.eckert@amd.com Source('dramsim2.cc') 7510235Syasuko.eckert@amd.com 7610235Syasuko.eckert@amd.comDebugFlag('BaseBus') 7710235Syasuko.eckert@amd.comDebugFlag('BusAddrRanges') 7810235Syasuko.eckert@amd.comDebugFlag('CoherentBus') 7910235Syasuko.eckert@amd.comDebugFlag('NoncoherentBus') 8010235Syasuko.eckert@amd.comCompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus', 8110235Syasuko.eckert@amd.com 'NoncoherentBus']) 8210235Syasuko.eckert@amd.com 8310235Syasuko.eckert@amd.comDebugFlag('Bridge') 8410235Syasuko.eckert@amd.comDebugFlag('CommMonitor') 8510235Syasuko.eckert@amd.comDebugFlag('DRAM') 8610235Syasuko.eckert@amd.comDebugFlag('DRAMPower') 8710235Syasuko.eckert@amd.comDebugFlag('DRAMState') 8810235Syasuko.eckert@amd.comDebugFlag('LLSC') 8910235Syasuko.eckert@amd.comDebugFlag('MMU') 9010235Syasuko.eckert@amd.comDebugFlag('MemoryAccess') 9110235Syasuko.eckert@amd.comDebugFlag('PacketQueue') 9210235Syasuko.eckert@amd.com 9310235Syasuko.eckert@amd.comDebugFlag("DRAMSim2") 9410235Syasuko.eckert@amd.com