SConscript revision 10299:bec0c5ffc323
1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright 9# notice, this list of conditions and the following disclaimer; 10# redistributions in binary form must reproduce the above copyright 11# notice, this list of conditions and the following disclaimer in the 12# documentation and/or other materials provided with the distribution; 13# neither the name of the copyright holders nor the names of its 14# contributors may be used to endorse or promote products derived from 15# this software without specific prior written permission. 16# 17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28# 29# Authors: Nathan Binkert 30 31Import('*') 32 33# Only build the communication if we have support for protobuf as the 34# tracing relies on it 35if env['HAVE_PROTOBUF']: 36 SimObject('CommMonitor.py') 37 Source('comm_monitor.cc') 38 39SimObject('AbstractMemory.py') 40SimObject('AddrMapper.py') 41SimObject('Bridge.py') 42SimObject('Bus.py') 43SimObject('DRAMCtrl.py') 44SimObject('MemObject.py') 45SimObject('SimpleMemory.py') 46 47Source('abstract_mem.cc') 48Source('addr_mapper.cc') 49Source('bridge.cc') 50Source('bus.cc') 51Source('coherent_bus.cc') 52Source('dram_ctrl.cc') 53Source('mem_object.cc') 54Source('mport.cc') 55Source('noncoherent_bus.cc') 56Source('packet.cc') 57Source('port.cc') 58Source('packet_queue.cc') 59Source('tport.cc') 60Source('port_proxy.cc') 61Source('simple_mem.cc') 62Source('physical.cc') 63 64if env['TARGET_ISA'] != 'null': 65 Source('fs_translating_port_proxy.cc') 66 Source('se_translating_port_proxy.cc') 67 Source('page_table.cc') 68if env['TARGET_ISA'] == 'x86': 69 Source('multi_level_page_table.cc') 70 71if env['HAVE_DRAMSIM']: 72 SimObject('DRAMSim2.py') 73 Source('dramsim2_wrapper.cc') 74 Source('dramsim2.cc') 75 76DebugFlag('BaseBus') 77DebugFlag('BusAddrRanges') 78DebugFlag('CoherentBus') 79DebugFlag('NoncoherentBus') 80CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus', 81 'NoncoherentBus']) 82 83DebugFlag('Bridge') 84DebugFlag('CommMonitor') 85DebugFlag('DRAM') 86DebugFlag('DRAMPower') 87DebugFlag('DRAMState') 88DebugFlag('LLSC') 89DebugFlag('MMU') 90DebugFlag('MemoryAccess') 91DebugFlag('PacketQueue') 92 93DebugFlag("DRAMSim2") 94