SConscript revision 10208:c249f7660eb7 
13534Sgblack@eecs.umich.edu# -*- mode:python -*-
23534Sgblack@eecs.umich.edu
33534Sgblack@eecs.umich.edu# Copyright (c) 2006 The Regents of The University of Michigan
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53534Sgblack@eecs.umich.edu#
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83534Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright
93534Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
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153534Sgblack@eecs.umich.edu# this software without specific prior written permission.
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283534Sgblack@eecs.umich.edu#
293534Sgblack@eecs.umich.edu# Authors: Nathan Binkert
303534Sgblack@eecs.umich.edu
313534Sgblack@eecs.umich.eduImport('*')
324202Sbinkertn@umich.edu
333534Sgblack@eecs.umich.edu# Only build the communication if we have support for protobuf as the
344202Sbinkertn@umich.edu# tracing relies on it
355480Snate@binkert.orgif env['HAVE_PROTOBUF']:
364486Sbinkertn@umich.edu    SimObject('CommMonitor.py')
374486Sbinkertn@umich.edu    Source('comm_monitor.cc')
385480Snate@binkert.org
394202Sbinkertn@umich.eduSimObject('AbstractMemory.py')
404202Sbinkertn@umich.eduSimObject('AddrMapper.py')
414202Sbinkertn@umich.eduSimObject('Bridge.py')
424202Sbinkertn@umich.eduSimObject('Bus.py')
435192Ssaidi@eecs.umich.eduSimObject('DRAMCtrl.py')
445480Snate@binkert.orgSimObject('MemObject.py')
455192Ssaidi@eecs.umich.eduSimObject('SimpleMemory.py')
46
47Source('abstract_mem.cc')
48Source('addr_mapper.cc')
49Source('bridge.cc')
50Source('bus.cc')
51Source('coherent_bus.cc')
52Source('dram_ctrl.cc')
53Source('mem_object.cc')
54Source('mport.cc')
55Source('noncoherent_bus.cc')
56Source('packet.cc')
57Source('port.cc')
58Source('packet_queue.cc')
59Source('tport.cc')
60Source('port_proxy.cc')
61Source('simple_mem.cc')
62Source('physical.cc')
63
64if env['TARGET_ISA'] != 'null':
65    Source('fs_translating_port_proxy.cc')
66    Source('se_translating_port_proxy.cc')
67    Source('page_table.cc')
68
69if env['HAVE_DRAMSIM']:
70    SimObject('DRAMSim2.py')
71    Source('dramsim2_wrapper.cc')
72    Source('dramsim2.cc')
73
74DebugFlag('BaseBus')
75DebugFlag('BusAddrRanges')
76DebugFlag('CoherentBus')
77DebugFlag('NoncoherentBus')
78CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
79                     'NoncoherentBus'])
80
81DebugFlag('Bridge')
82DebugFlag('CommMonitor')
83DebugFlag('DRAM')
84DebugFlag('DRAMState')
85DebugFlag('LLSC')
86DebugFlag('MMU')
87DebugFlag('MemoryAccess')
88DebugFlag('PacketQueue')
89
90DebugFlag("DRAMSim2")
91