xref: /gem5/src/mem/SConscript

# -*- mode:python -*-

# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert

Import('*')

SimObject('Bridge.py')
SimObject('Bus.py')
SimObject('MemObject.py')

Source('bridge.cc')
Source('bus.cc')
Source('mem_object.cc')
Source('packet.cc')
Source('port.cc')
Source('tport.cc')
Source('mport.cc')

if env['TARGET_ISA'] != 'no':
    SimObject('PhysicalMemory.py')
    Source('dram.cc')
    Source('physical.cc')

if env['FULL_SYSTEM']:
    Source('vport.cc')
elif env['TARGET_ISA'] != 'no':
    Source('page_table.cc')
    Source('translating_port.cc')

TraceFlag('Bus')
TraceFlag('BusAddrRanges')
TraceFlag('BusBridge')
TraceFlag('LLSC')
TraceFlag('MMU')
TraceFlag('MemoryAccess')

TraceFlag('ProtocolTrace')
TraceFlag('RubyCache')
TraceFlag('RubyDma')
TraceFlag('RubyGenerated')
TraceFlag('RubyMemory')
TraceFlag('RubyNetwork')
TraceFlag('RubyPort')
TraceFlag('RubyQueue')
TraceFlag('RubySlicc')
TraceFlag('RubyStorebuffer')
TraceFlag('RubyTester')

CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
    'RubyGenerated', 'RubySlicc', 'RubyStorebuffer', 'RubyCache', 
    'RubyMemory', 'RubyDma', 'RubyPort'])