HMCController.py revision 13665:9c7fe3811b88
12SN/A# Copyright (c) 2012-2013 ARM Limited 21762SN/A# All rights reserved. 32SN/A# 42SN/A# The license below extends only to copyright in the software and shall 52SN/A# not be construed as granting a license to any other intellectual 62SN/A# property including but not limited to intellectual property relating 72SN/A# to a hardware implementation of the functionality of the software 82SN/A# licensed hereunder. You may use the software subject to the license 92SN/A# terms below provided that you ensure that this notice is replicated 102SN/A# unmodified and in its entirety in all distributions of the software, 112SN/A# modified or unmodified, in source code or in binary form. 122SN/A# 132SN/A# Copyright (c) 2015 The University of Bologna 142SN/A# All rights reserved. 152SN/A# 162SN/A# Redistribution and use in source and binary forms, with or without 172SN/A# modification, are permitted provided that the following conditions are 182SN/A# met: redistributions of source code must retain the above copyright 192SN/A# notice, this list of conditions and the following disclaimer; 202SN/A# redistributions in binary form must reproduce the above copyright 212SN/A# notice, this list of conditions and the following disclaimer in the 222SN/A# documentation and/or other materials provided with the distribution; 232SN/A# neither the name of the copyright holders nor the names of its 242SN/A# contributors may be used to endorse or promote products derived from 252SN/A# this software without specific prior written permission. 262SN/A# 272665Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282665Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3477SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3577SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362986Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3756SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3856SN/A# 3956SN/A# Authors: Erfan Azarkhish 4056SN/A 412SN/Afrom m5.params import * 422SN/Afrom m5.objects.XBar import * 432680Sktlim@umich.edu 442SN/A# References: 452SN/A# [1] http://www.open-silicon.com/open-silicon-ips/hmc/ 461910SN/A# [2] Ahn, J.; Yoo, S.; Choi, K., "Low-Power Hybrid Memory Cubes With Link 472SN/A# Power Management and Two-Level Prefetching," TVLSI 2015 482SN/A 492107SN/A# The HMCController class highlights the fact that a component is required 502107SN/A# between host and HMC to convert the host protocol (AXI for example) to the 511910SN/A# serial links protocol. Moreover, this component should have large internal 521910SN/A# queueing to hide the access latency of the HMC. 531910SN/A# Plus, this controller can implement more advanced global scheduling policies 541910SN/A# and can reorder and steer transactions if required. A good example of such 552SN/A# component is available in [1]. 562SN/A# Also in [2] there is a similar component which is connected to all serial 572SN/A# links, and it schedules the requests to the ones which are not busy. 582SN/A# These two references clarify two things: 592SN/A# 1. The serial links support the same address range and packets can travel 602SN/A# over any of them. 612SN/A# 2. One host can be connected to more than 1 serial link simply to achieve 622SN/A# higher bandwidth, and not for any other reason. 632SN/A 642SN/A# In this model, we have used a round-robin counter, because it is the 652SN/A# simplest way to schedule packets over the non-busy serial links. However, 662SN/A# more advanced scheduling algorithms are possible and even host can dedicate 672SN/A# each serial link to a portion of the address space and interleave packets 681910SN/A# over them. Yet in this model, we have not made any such assumptions on the 691910SN/A# address space. 702SN/A 712SN/Aclass HMCController(NoncoherentXBar): 722SN/A type = 'HMCController' 732SN/A cxx_header = "mem/hmc_controller.hh" 742SN/A