111184Serfan.azarkhish@unibo.it# Copyright (c) 2012-2013 ARM Limited 211184Serfan.azarkhish@unibo.it# All rights reserved. 311184Serfan.azarkhish@unibo.it# 411184Serfan.azarkhish@unibo.it# The license below extends only to copyright in the software and shall 511184Serfan.azarkhish@unibo.it# not be construed as granting a license to any other intellectual 611184Serfan.azarkhish@unibo.it# property including but not limited to intellectual property relating 711184Serfan.azarkhish@unibo.it# to a hardware implementation of the functionality of the software 811184Serfan.azarkhish@unibo.it# licensed hereunder. You may use the software subject to the license 911184Serfan.azarkhish@unibo.it# terms below provided that you ensure that this notice is replicated 1011184Serfan.azarkhish@unibo.it# unmodified and in its entirety in all distributions of the software, 1111184Serfan.azarkhish@unibo.it# modified or unmodified, in source code or in binary form. 1211184Serfan.azarkhish@unibo.it# 1311184Serfan.azarkhish@unibo.it# Copyright (c) 2015 The University of Bologna 1411184Serfan.azarkhish@unibo.it# All rights reserved. 1511184Serfan.azarkhish@unibo.it# 1611184Serfan.azarkhish@unibo.it# Redistribution and use in source and binary forms, with or without 1711184Serfan.azarkhish@unibo.it# modification, are permitted provided that the following conditions are 1811184Serfan.azarkhish@unibo.it# met: redistributions of source code must retain the above copyright 1911184Serfan.azarkhish@unibo.it# notice, this list of conditions and the following disclaimer; 2011184Serfan.azarkhish@unibo.it# redistributions in binary form must reproduce the above copyright 2111184Serfan.azarkhish@unibo.it# notice, this list of conditions and the following disclaimer in the 2211184Serfan.azarkhish@unibo.it# documentation and/or other materials provided with the distribution; 2311184Serfan.azarkhish@unibo.it# neither the name of the copyright holders nor the names of its 2411184Serfan.azarkhish@unibo.it# contributors may be used to endorse or promote products derived from 2511184Serfan.azarkhish@unibo.it# this software without specific prior written permission. 2611184Serfan.azarkhish@unibo.it# 2711184Serfan.azarkhish@unibo.it# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2811184Serfan.azarkhish@unibo.it# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2911184Serfan.azarkhish@unibo.it# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3011184Serfan.azarkhish@unibo.it# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3111184Serfan.azarkhish@unibo.it# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3211184Serfan.azarkhish@unibo.it# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3311184Serfan.azarkhish@unibo.it# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3411184Serfan.azarkhish@unibo.it# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3511184Serfan.azarkhish@unibo.it# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3611184Serfan.azarkhish@unibo.it# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3711184Serfan.azarkhish@unibo.it# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3811184Serfan.azarkhish@unibo.it# 3911184Serfan.azarkhish@unibo.it# Authors: Erfan Azarkhish 4011184Serfan.azarkhish@unibo.it 4111184Serfan.azarkhish@unibo.itfrom m5.params import * 4213665Sandreas.sandberg@arm.comfrom m5.objects.XBar import * 4311184Serfan.azarkhish@unibo.it 4411184Serfan.azarkhish@unibo.it# References: 4511184Serfan.azarkhish@unibo.it# [1] http://www.open-silicon.com/open-silicon-ips/hmc/ 4611184Serfan.azarkhish@unibo.it# [2] Ahn, J.; Yoo, S.; Choi, K., "Low-Power Hybrid Memory Cubes With Link 4711184Serfan.azarkhish@unibo.it# Power Management and Two-Level Prefetching," TVLSI 2015 4811184Serfan.azarkhish@unibo.it 4911184Serfan.azarkhish@unibo.it# The HMCController class highlights the fact that a component is required 5011184Serfan.azarkhish@unibo.it# between host and HMC to convert the host protocol (AXI for example) to the 5111184Serfan.azarkhish@unibo.it# serial links protocol. Moreover, this component should have large internal 5211184Serfan.azarkhish@unibo.it# queueing to hide the access latency of the HMC. 5311184Serfan.azarkhish@unibo.it# Plus, this controller can implement more advanced global scheduling policies 5411184Serfan.azarkhish@unibo.it# and can reorder and steer transactions if required. A good example of such 5511184Serfan.azarkhish@unibo.it# component is available in [1]. 5611184Serfan.azarkhish@unibo.it# Also in [2] there is a similar component which is connected to all serial 5711184Serfan.azarkhish@unibo.it# links, and it schedules the requests to the ones which are not busy. 5811184Serfan.azarkhish@unibo.it# These two references clarify two things: 5911184Serfan.azarkhish@unibo.it# 1. The serial links support the same address range and packets can travel 6011184Serfan.azarkhish@unibo.it# over any of them. 6111184Serfan.azarkhish@unibo.it# 2. One host can be connected to more than 1 serial link simply to achieve 6211184Serfan.azarkhish@unibo.it# higher bandwidth, and not for any other reason. 6311184Serfan.azarkhish@unibo.it 6411184Serfan.azarkhish@unibo.it# In this model, we have used a round-robin counter, because it is the 6511184Serfan.azarkhish@unibo.it# simplest way to schedule packets over the non-busy serial links. However, 6611184Serfan.azarkhish@unibo.it# more advanced scheduling algorithms are possible and even host can dedicate 6711184Serfan.azarkhish@unibo.it# each serial link to a portion of the address space and interleave packets 6811184Serfan.azarkhish@unibo.it# over them. Yet in this model, we have not made any such assumptions on the 6911184Serfan.azarkhish@unibo.it# address space. 7011184Serfan.azarkhish@unibo.it 7111184Serfan.azarkhish@unibo.itclass HMCController(NoncoherentXBar): 7211184Serfan.azarkhish@unibo.it type = 'HMCController' 7311184Serfan.azarkhish@unibo.it cxx_header = "mem/hmc_controller.hh" 74