ExternalMaster.py revision 13892:0182a0601f66
12207SN/A# Copyright (c) 2014 ARM Limited
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72207SN/A# to a hardware implementation of the functionality of the software
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348229Snate@binkert.org# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
352454SN/A#
362454SN/A# Authors: Andrew Bardsley
372680Sktlim@umich.edu#          Curtis Dunham
388232Snate@binkert.org#          Christian Menard
395759Shsul@eecs.umich.edu
407678Sgblack@eecs.umich.edufrom m5.params import *
415759Shsul@eecs.umich.edufrom m5.proxy import *
422474SN/Afrom m5.SimObject import SimObject
432207SN/A
442474SN/Aclass ExternalMaster(SimObject):
452474SN/A    type = 'ExternalMaster'
462474SN/A    cxx_header = "mem/external_master.hh"
475569Snate@binkert.org
485569Snate@binkert.org    port = MasterPort("Master port")
495154Sgblack@eecs.umich.edu
502474SN/A    port_type = Param.String('stub', 'Registered external port handler'
512474SN/A        ' to pass this port to in instantiation')
522474SN/A    port_data = Param.String('stub', 'A string to pass to the port'
532474SN/A        ' handler (in a format specific to the handler) to describe how'
542474SN/A        ' the port should be bound/bindable/discoverable')
552474SN/A
562474SN/A    system = Param.System(Parent.any, 'System this external port belongs to')
572474SN/A