DRAMCtrl.py revision 9970
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2013 Amin Farmahini-Farahani 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Andreas Hansson 40# Ani Udipi 41 42from m5.params import * 43from AbstractMemory import * 44 45# Enum for memory scheduling algorithms, currently First-Come 46# First-Served and a First-Row Hit then First-Come First-Served 47class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 48 49# Enum for the address mapping. With Ra, Co, Ba and Ch denoting rank, 50# column, bank and channel, respectively, and going from MSB to LSB. 51# Available are RaBaChCo and RaBaCoCh, that are suitable for an 52# open-page policy, optimising for sequential accesses hitting in the 53# open row. For a closed-page policy, CoRaBaCh maximises parallelism. 54class AddrMap(Enum): vals = ['RaBaChCo', 'RaBaCoCh', 'CoRaBaCh'] 55 56# Enum for the page policy, either open or close. 57class PageManage(Enum): vals = ['open', 'close'] 58 59# SimpleDRAM is a single-channel single-ported DRAM controller model 60# that aims to model the most important system-level performance 61# effects of a DRAM without getting into too much detail of the DRAM 62# itself. 63class SimpleDRAM(AbstractMemory): 64 type = 'SimpleDRAM' 65 cxx_header = "mem/simple_dram.hh" 66 67 # single-ported on the system interface side, instantiate with a 68 # bus in front of the controller for multiple ports 69 port = SlavePort("Slave port") 70 71 # the basic configuration of the controller architecture 72 write_buffer_size = Param.Unsigned(32, "Number of read queue entries") 73 read_buffer_size = Param.Unsigned(32, "Number of write queue entries") 74 75 # threshold in percent for when to trigger writes and start 76 # emptying the write buffer as it starts to get full 77 write_thresh_perc = Param.Percent(70, "Threshold to trigger writes") 78 79 # scheduler, address map and page policy 80 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 81 addr_mapping = Param.AddrMap('RaBaChCo', "Address mapping policy") 82 page_policy = Param.PageManage('open', "Page closure management policy") 83 84 # pipeline latency of the controller and PHY, split into a 85 # frontend part and a backend part, with reads and writes serviced 86 # by the queues only seeing the frontend contribution, and reads 87 # serviced by the memory seeing the sum of the two 88 static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 89 static_backend_latency = Param.Latency("10ns", "Static backend latency") 90 91 # the physical organisation of the DRAM 92 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 93 "device/chip") 94 burst_length = Param.Unsigned("Burst lenght (BL) in beats") 95 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 96 "device/chip") 97 devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 98 ranks_per_channel = Param.Unsigned("Number of ranks per channel") 99 banks_per_rank = Param.Unsigned("Number of banks per rank") 100 # only used for the address mapping as the controller by 101 # construction is a single channel and multiple controllers have 102 # to be instantiated for a multi-channel configuration 103 channels = Param.Unsigned(1, "Number of channels") 104 105 # timing behaviour and constraints - all in nanoseconds 106 107 # the amount of time in nanoseconds from issuing an activate command 108 # to the data being available in the row buffer for a read/write 109 tRCD = Param.Latency("RAS to CAS delay") 110 111 # the time from issuing a read/write command to seeing the actual data 112 tCL = Param.Latency("CAS latency") 113 114 # minimum time between a precharge and subsequent activate 115 tRP = Param.Latency("Row precharge time") 116 117 # minimum time between an activate and a precharge to the same row 118 tRAS = Param.Latency("ACT to PRE delay") 119 120 # time to complete a burst transfer, typically the burst length 121 # divided by two due to the DDR bus, but by making it a parameter 122 # it is easier to also evaluate SDR memories like WideIO. 123 # This parameter has to account for burst length. 124 # Read/Write requests with data size larger than one full burst are broken 125 # down into multiple requests in the SimpleDRAM controller 126 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 127 128 # time taken to complete one refresh cycle (N rows in all banks) 129 tRFC = Param.Latency("Refresh cycle time") 130 131 # refresh command interval, how often a "ref" command needs 132 # to be sent. It is 7.8 us for a 64ms refresh requirement 133 tREFI = Param.Latency("Refresh command interval") 134 135 # write-to-read turn around penalty, assumed same as read-to-write 136 tWTR = Param.Latency("Write to read switching time") 137 138 # time window in which a maximum number of activates are allowed 139 # to take place, set to 0 to disable 140 tXAW = Param.Latency("X activation window") 141 activation_limit = Param.Unsigned("Max number of activates in window") 142 143 # Currently rolled into other params 144 ###################################################################### 145 146 # tRC - assumed to be tRAS + tRP 147 148# A single DDR3 x64 interface (one command and address bus), with 149# default timings based on DDR3-1600 4 Gbit parts in an 8x8 150# configuration, which would amount to 4 Gbyte of memory. 151class DDR3_1600_x64(SimpleDRAM): 152 # 8x8 configuration, 8 devices each with an 8-bit interface 153 device_bus_width = 8 154 155 # DDR3 is a BL8 device 156 burst_length = 8 157 158 # Each device has a page (row buffer) size of 1KB 159 # (this depends on the memory density) 160 device_rowbuffer_size = '1kB' 161 162 # 8x8 configuration, so 8 devices 163 devices_per_rank = 8 164 165 # Use two ranks 166 ranks_per_channel = 2 167 168 # DDR3 has 8 banks in all configurations 169 banks_per_rank = 8 170 171 # DDR3-1600 11-11-11-28 172 tRCD = '13.75ns' 173 tCL = '13.75ns' 174 tRP = '13.75ns' 175 tRAS = '35ns' 176 177 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 178 # Note this is a BL8 DDR device. 179 tBURST = '5ns' 180 181 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 182 tRFC = '300ns' 183 184 # DDR3, <=85C, half for >85C 185 tREFI = '7.8us' 186 187 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 188 tWTR = '7.5ns' 189 190 # With a 2kbyte page size, DDR3-1600 lands around 40 ns 191 tXAW = '40ns' 192 activation_limit = 4 193 194 195# A single LPDDR2-S4 x32 interface (one command/address bus), with 196# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 197# configuration. 198class LPDDR2_S4_1066_x32(SimpleDRAM): 199 # 1x32 configuration, 1 device with a 32-bit interface 200 device_bus_width = 32 201 202 # LPDDR2_S4 is a BL4 and BL8 device 203 burst_length = 8 204 205 # Each device has a page (row buffer) size of 1KB 206 # (this depends on the memory density) 207 device_rowbuffer_size = '1kB' 208 209 # 1x32 configuration, so 1 device 210 devices_per_rank = 1 211 212 # Use a single rank 213 ranks_per_channel = 1 214 215 # LPDDR2-S4 has 8 banks in all configurations 216 banks_per_rank = 8 217 218 # Fixed at 15 ns 219 tRCD = '15ns' 220 221 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 222 tCL = '15ns' 223 224 # Pre-charge one bank 15 ns (all banks 18 ns) 225 tRP = '15ns' 226 227 tRAS = '42ns' 228 229 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 230 # Note this is a BL8 DDR device. 231 # Requests larger than 32 bytes are broken down into multiple requests 232 # in the SimpleDRAM controller 233 tBURST = '7.5ns' 234 235 # LPDDR2-S4, 4 Gbit 236 tRFC = '130ns' 237 tREFI = '3.9us' 238 239 # Irrespective of speed grade, tWTR is 7.5 ns 240 tWTR = '7.5ns' 241 242 # Irrespective of density, tFAW is 50 ns 243 tXAW = '50ns' 244 activation_limit = 4 245 246# A single WideIO x128 interface (one command and address bus), with 247# default timings based on an estimated WIO-200 8 Gbit part. 248class WideIO_200_x128(SimpleDRAM): 249 # 1x128 configuration, 1 device with a 128-bit interface 250 device_bus_width = 128 251 252 # This is a BL4 device 253 burst_length = 4 254 255 # Each device has a page (row buffer) size of 4KB 256 # (this depends on the memory density) 257 device_rowbuffer_size = '4kB' 258 259 # 1x128 configuration, so 1 device 260 devices_per_rank = 1 261 262 # Use one rank for a one-high die stack 263 ranks_per_channel = 1 264 265 # WideIO has 4 banks in all configurations 266 banks_per_rank = 4 267 268 # WIO-200 269 tRCD = '18ns' 270 tCL = '18ns' 271 tRP = '18ns' 272 tRAS = '42ns' 273 274 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 275 # Note this is a BL4 SDR device. 276 tBURST = '20ns' 277 278 # WIO 8 Gb 279 tRFC = '210ns' 280 281 # WIO 8 Gb, <=85C, half for >85C 282 tREFI = '3.9us' 283 284 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 285 tWTR = '15ns' 286 287 # Two instead of four activation window 288 tXAW = '50ns' 289 activation_limit = 2 290 291# A single LPDDR3 x32 interface (one command/address bus), with 292# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32 293# configuration 294class LPDDR3_1600_x32(SimpleDRAM): 295 # 1x32 configuration, 1 device with a 32-bit interface 296 device_bus_width = 32 297 298 # LPDDR3 is a BL8 device 299 burst_length = 8 300 301 # Each device has a page (row buffer) size of 1KB 302 # (this depends on the memory density) 303 device_rowbuffer_size = '1kB' 304 305 # 1x32 configuration, so 1 device 306 devices_per_rank = 1 307 308 # Use a single rank 309 ranks_per_channel = 1 310 311 # LPDDR3 has 8 banks in all configurations 312 banks_per_rank = 8 313 314 # Fixed at 15 ns 315 tRCD = '15ns' 316 317 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 318 tCL = '15ns' 319 320 tRAS = '42ns' 321 322 # Pre-charge one bank 15 ns (all banks 18 ns) 323 tRP = '15ns' 324 325 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 326 # Note this is a BL8 DDR device. 327 # Requests larger than 32 bytes are broken down into multiple requests 328 # in the SimpleDRAM controller 329 tBURST = '5ns' 330 331 # LPDDR3, 4 Gb 332 tRFC = '130ns' 333 tREFI = '3.9us' 334 335 # Irrespective of speed grade, tWTR is 7.5 ns 336 tWTR = '7.5ns' 337 338 # Irrespective of size, tFAW is 50 ns 339 tXAW = '50ns' 340 activation_limit = 4 341