DRAMCtrl.py revision 9831
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2013 Amin Farmahini-Farahani 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Andreas Hansson 40# Ani Udipi 41 42from m5.params import * 43from AbstractMemory import * 44 45# Enum for memory scheduling algorithms, currently First-Come 46# First-Served and a First-Row Hit then First-Come First-Served 47class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 48 49# Enum for the address mapping. With Ra, Co, Ba and Ch denoting rank, 50# column, bank and channel, respectively, and going from MSB to LSB. 51# Available are RaBaChCo and RaBaCoCh, that are suitable for an 52# open-page policy, optimising for sequential accesses hitting in the 53# open row. For a closed-page policy, CoRaBaCh maximises parallelism. 54class AddrMap(Enum): vals = ['RaBaChCo', 'RaBaCoCh', 'CoRaBaCh'] 55 56# Enum for the page policy, either open or close. 57class PageManage(Enum): vals = ['open', 'close'] 58 59# SimpleDRAM is a single-channel single-ported DRAM controller model 60# that aims to model the most important system-level performance 61# effects of a DRAM without getting into too much detail of the DRAM 62# itself. 63class SimpleDRAM(AbstractMemory): 64 type = 'SimpleDRAM' 65 cxx_header = "mem/simple_dram.hh" 66 67 @classmethod 68 def makeMultiChannel(cls, nbr_mem_ctrls, mem_start_addr, mem_size, 69 intlv_high_bit = 11): 70 """ 71 Make a multi-channel configuration of this class. 72 73 Create multiple instances of the specific class and set their 74 parameters such that the address range is interleaved between 75 them. 76 77 Returns a list of controllers. 78 """ 79 import math 80 from m5.util import fatal 81 intlv_bits = int(math.log(nbr_mem_ctrls, 2)) 82 if 2 ** intlv_bits != nbr_mem_ctrls: 83 fatal("Number of memory channels must be a power of 2") 84 mem_ctrls = [] 85 for i in xrange(nbr_mem_ctrls): 86 # The default interleaving granularity is tuned to match a 87 # row buffer size of 32 cache lines of 64 bytes (starting 88 # at bit 11 for 2048 bytes). There is unfortunately no 89 # good way of checking this at instantiation time. 90 mem_ctrls.append(cls(range = AddrRange(mem_start_addr, 91 size = mem_size, 92 intlvHighBit = \ 93 intlv_high_bit, 94 intlvBits = intlv_bits, 95 intlvMatch = i), 96 channels = nbr_mem_ctrls)) 97 return mem_ctrls 98 99 # single-ported on the system interface side, instantiate with a 100 # bus in front of the controller for multiple ports 101 port = SlavePort("Slave port") 102 103 # the basic configuration of the controller architecture 104 write_buffer_size = Param.Unsigned(32, "Number of read queue entries") 105 read_buffer_size = Param.Unsigned(32, "Number of write queue entries") 106 107 # threshold in percent for when to trigger writes and start 108 # emptying the write buffer as it starts to get full 109 write_thresh_perc = Param.Percent(70, "Threshold to trigger writes") 110 111 # scheduler, address map and page policy 112 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 113 addr_mapping = Param.AddrMap('RaBaChCo', "Address mapping policy") 114 page_policy = Param.PageManage('open', "Page closure management policy") 115 116 # pipeline latency of the controller and PHY, split into a 117 # frontend part and a backend part, with reads and writes serviced 118 # by the queues only seeing the frontend contribution, and reads 119 # serviced by the memory seeing the sum of the two 120 static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 121 static_backend_latency = Param.Latency("10ns", "Static backend latency") 122 123 # the physical organisation of the DRAM 124 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 125 "device/chip") 126 burst_length = Param.Unsigned("Burst lenght (BL) in beats") 127 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 128 "device/chip") 129 devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 130 ranks_per_channel = Param.Unsigned("Number of ranks per channel") 131 banks_per_rank = Param.Unsigned("Number of banks per rank") 132 # only used for the address mapping as the controller by 133 # construction is a single channel and multiple controllers have 134 # to be instantiated for a multi-channel configuration 135 channels = Param.Unsigned(1, "Number of channels") 136 137 # timing behaviour and constraints - all in nanoseconds 138 139 # the amount of time in nanoseconds from issuing an activate command 140 # to the data being available in the row buffer for a read/write 141 tRCD = Param.Latency("RAS to CAS delay") 142 143 # the time from issuing a read/write command to seeing the actual data 144 tCL = Param.Latency("CAS latency") 145 146 # minimum time between a precharge and subsequent activate 147 tRP = Param.Latency("Row precharge time") 148 149 # time to complete a burst transfer, typically the burst length 150 # divided by two due to the DDR bus, but by making it a parameter 151 # it is easier to also evaluate SDR memories like WideIO. 152 # This parameter has to account for burst length. 153 # Read/Write requests with data size larger than one full burst are broken 154 # down into multiple requests in the SimpleDRAM controller 155 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 156 157 # time taken to complete one refresh cycle (N rows in all banks) 158 tRFC = Param.Latency("Refresh cycle time") 159 160 # refresh command interval, how often a "ref" command needs 161 # to be sent. It is 7.8 us for a 64ms refresh requirement 162 tREFI = Param.Latency("Refresh command interval") 163 164 # write-to-read turn around penalty, assumed same as read-to-write 165 tWTR = Param.Latency("Write to read switching time") 166 167 # time window in which a maximum number of activates are allowed 168 # to take place, set to 0 to disable 169 tXAW = Param.Latency("X activation window") 170 activation_limit = Param.Unsigned("Max number of activates in window") 171 172 # Currently rolled into other params 173 ###################################################################### 174 175 # the minimum amount of time between a row being activated, and 176 # precharged (de-activated) 177 # tRAS - assumed to be 3 * tRP 178 179 # tRC - assumed to be 4 * tRP 180 181# A single DDR3 x64 interface (one command and address bus), with 182# default timings based on DDR3-1600 4 Gbit parts in an 8x8 183# configuration, which would amount to 4 Gbyte of memory. 184class DDR3_1600_x64(SimpleDRAM): 185 # 8x8 configuration, 8 devices each with an 8-bit interface 186 device_bus_width = 8 187 188 # DDR3 is a BL8 device 189 burst_length = 8 190 191 # Each device has a page (row buffer) size of 1KB 192 # (this depends on the memory density) 193 device_rowbuffer_size = '1kB' 194 195 # 8x8 configuration, so 8 devices 196 devices_per_rank = 8 197 198 # Use two ranks 199 ranks_per_channel = 2 200 201 # DDR3 has 8 banks in all configurations 202 banks_per_rank = 8 203 204 # DDR3-1600 11-11-11 205 tRCD = '13.75ns' 206 tCL = '13.75ns' 207 tRP = '13.75ns' 208 209 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 210 # Note this is a BL8 DDR device. 211 tBURST = '5ns' 212 213 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 214 tRFC = '300ns' 215 216 # DDR3, <=85C, half for >85C 217 tREFI = '7.8us' 218 219 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 220 tWTR = '7.5ns' 221 222 # With a 2kbyte page size, DDR3-1600 lands around 40 ns 223 tXAW = '40ns' 224 activation_limit = 4 225 226 227# A single LPDDR2-S4 x32 interface (one command/address bus), with 228# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 229# configuration. 230class LPDDR2_S4_1066_x32(SimpleDRAM): 231 # 1x32 configuration, 1 device with a 32-bit interface 232 device_bus_width = 32 233 234 # LPDDR2_S4 is a BL4 and BL8 device 235 burst_length = 8 236 237 # Each device has a page (row buffer) size of 1KB 238 # (this depends on the memory density) 239 device_rowbuffer_size = '1kB' 240 241 # 1x32 configuration, so 1 device 242 devices_per_rank = 1 243 244 # Use a single rank 245 ranks_per_channel = 1 246 247 # LPDDR2-S4 has 8 banks in all configurations 248 banks_per_rank = 8 249 250 # Fixed at 15 ns 251 tRCD = '15ns' 252 253 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 254 tCL = '15ns' 255 256 # Pre-charge one bank 15 ns (all banks 18 ns) 257 tRP = '15ns' 258 259 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 260 # Note this is a BL8 DDR device. 261 # Requests larger than 32 bytes are broken down into multiple requests 262 # in the SimpleDRAM controller 263 tBURST = '7.5ns' 264 265 # LPDDR2-S4, 4 Gbit 266 tRFC = '130ns' 267 tREFI = '3.9us' 268 269 # Irrespective of speed grade, tWTR is 7.5 ns 270 tWTR = '7.5ns' 271 272 # Irrespective of density, tFAW is 50 ns 273 tXAW = '50ns' 274 activation_limit = 4 275 276# A single WideIO x128 interface (one command and address bus), with 277# default timings based on an estimated WIO-200 8 Gbit part. 278class WideIO_200_x128(SimpleDRAM): 279 # 1x128 configuration, 1 device with a 128-bit interface 280 device_bus_width = 128 281 282 # This is a BL4 device 283 burst_length = 4 284 285 # Each device has a page (row buffer) size of 4KB 286 # (this depends on the memory density) 287 device_rowbuffer_size = '4kB' 288 289 # 1x128 configuration, so 1 device 290 devices_per_rank = 1 291 292 # Use one rank for a one-high die stack 293 ranks_per_channel = 1 294 295 # WideIO has 4 banks in all configurations 296 banks_per_rank = 4 297 298 # WIO-200 299 tRCD = '18ns' 300 tCL = '18ns' 301 tRP = '18ns' 302 303 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 304 # Note this is a BL4 SDR device. 305 tBURST = '20ns' 306 307 # WIO 8 Gb 308 tRFC = '210ns' 309 310 # WIO 8 Gb, <=85C, half for >85C 311 tREFI = '3.9us' 312 313 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 314 tWTR = '15ns' 315 316 # Two instead of four activation window 317 tXAW = '50ns' 318 activation_limit = 2 319 320# A single LPDDR3 x32 interface (one command/address bus), with 321# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32 322# configuration 323class LPDDR3_1600_x32(SimpleDRAM): 324 # 1x32 configuration, 1 device with a 32-bit interface 325 device_bus_width = 32 326 327 # LPDDR3 is a BL8 device 328 burst_length = 8 329 330 # Each device has a page (row buffer) size of 1KB 331 # (this depends on the memory density) 332 device_rowbuffer_size = '1kB' 333 334 # 1x32 configuration, so 1 device 335 devices_per_rank = 1 336 337 # Use a single rank 338 ranks_per_channel = 1 339 340 # LPDDR3 has 8 banks in all configurations 341 banks_per_rank = 8 342 343 # Fixed at 15 ns 344 tRCD = '15ns' 345 346 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 347 tCL = '15ns' 348 349 # Pre-charge one bank 15 ns (all banks 18 ns) 350 tRP = '15ns' 351 352 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 353 # Note this is a BL8 DDR device. 354 # Requests larger than 32 bytes are broken down into multiple requests 355 # in the SimpleDRAM controller 356 tBURST = '5ns' 357 358 # LPDDR3, 4 Gb 359 tRFC = '130ns' 360 tREFI = '3.9us' 361 362 # Irrespective of speed grade, tWTR is 7.5 ns 363 tWTR = '7.5ns' 364 365 # Irrespective of size, tFAW is 50 ns 366 tXAW = '50ns' 367 activation_limit = 4 368