DRAMCtrl.py revision 9708
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Hansson 37# Ani Udipi 38 39from m5.params import * 40from AbstractMemory import * 41 42# Enum for memory scheduling algorithms, currently First-Come 43# First-Served and a First-Row Hit then First-Come First-Served 44class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 45 46# Enum for the address mapping. With Ra, Co, Ba and Ch denoting rank, 47# column, bank and channel, respectively, and going from MSB to LSB. 48# Available are RaBaChCo and RaBaCoCh, that are suitable for an 49# open-page policy, optimising for sequential accesses hitting in the 50# open row. For a closed-page policy, CoRaBaCh maximises parallelism. 51class AddrMap(Enum): vals = ['RaBaChCo', 'RaBaCoCh', 'CoRaBaCh'] 52 53# Enum for the page policy, either open or close. 54class PageManage(Enum): vals = ['open', 'close'] 55 56# SimpleDRAM is a single-channel single-ported DRAM controller model 57# that aims to model the most important system-level performance 58# effects of a DRAM without getting into too much detail of the DRAM 59# itself. 60class SimpleDRAM(AbstractMemory): 61 type = 'SimpleDRAM' 62 cxx_header = "mem/simple_dram.hh" 63 64 @classmethod 65 def makeMultiChannel(cls, nbr_mem_ctrls, mem_start_addr, mem_size, 66 intlv_high_bit = 11): 67 """ 68 Make a multi-channel configuration of this class. 69 70 Create multiple instances of the specific class and set their 71 parameters such that the address range is interleaved between 72 them. 73 74 Returns a list of controllers. 75 """ 76 import math 77 from m5.util import fatal 78 intlv_bits = int(math.log(nbr_mem_ctrls, 2)) 79 if 2 ** intlv_bits != nbr_mem_ctrls: 80 fatal("Number of memory channels must be a power of 2") 81 mem_ctrls = [] 82 for i in xrange(nbr_mem_ctrls): 83 # The default interleaving granularity is tuned to match a 84 # row buffer size of 32 cache lines of 64 bytes (starting 85 # at bit 11 for 2048 bytes). There is unfortunately no 86 # good way of checking this at instantiation time. 87 mem_ctrls.append(cls(range = AddrRange(mem_start_addr, 88 size = mem_size, 89 intlvHighBit = \ 90 intlv_high_bit, 91 intlvBits = intlv_bits, 92 intlvMatch = i), 93 channels = nbr_mem_ctrls)) 94 return mem_ctrls 95 96 # single-ported on the system interface side, instantiate with a 97 # bus in front of the controller for multiple ports 98 port = SlavePort("Slave port") 99 100 # the basic configuration of the controller architecture 101 write_buffer_size = Param.Unsigned(32, "Number of read queue entries") 102 read_buffer_size = Param.Unsigned(32, "Number of write queue entries") 103 104 # threshold in percent for when to trigger writes and start 105 # emptying the write buffer as it starts to get full 106 write_thresh_perc = Param.Percent(70, "Threshold to trigger writes") 107 108 # scheduler, address map and page policy 109 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 110 addr_mapping = Param.AddrMap('RaBaChCo', "Address mapping policy") 111 page_policy = Param.PageManage('open', "Page closure management policy") 112 113 # the physical organisation of the DRAM 114 lines_per_rowbuffer = Param.Unsigned("Row buffer size in cache lines") 115 ranks_per_channel = Param.Unsigned("Number of ranks per channel") 116 banks_per_rank = Param.Unsigned("Number of banks per rank") 117 # only used for the address mapping as the controller by 118 # construction is a single channel and multiple controllers have 119 # to be instantiated for a multi-channel configuration 120 channels = Param.Unsigned(1, "Number of channels") 121 122 # timing behaviour and constraints - all in nanoseconds 123 124 # the amount of time in nanoseconds from issuing an activate command 125 # to the data being available in the row buffer for a read/write 126 tRCD = Param.Latency("RAS to CAS delay") 127 128 # the time from issuing a read/write command to seeing the actual data 129 tCL = Param.Latency("CAS latency") 130 131 # minimum time between a precharge and subsequent activate 132 tRP = Param.Latency("Row precharge time") 133 134 # time to complete a burst transfer, typically the burst length 135 # divided by two due to the DDR bus, but by making it a parameter 136 # it is easier to also evaluate SDR memories like WideIO. 137 # This parameter has to account for bus width and burst length. 138 # Adjustment also necessary if cache line size is greater than 139 # data size read/written by one full burst. 140 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 141 142 # time taken to complete one refresh cycle (N rows in all banks) 143 tRFC = Param.Latency("Refresh cycle time") 144 145 # refresh command interval, how often a "ref" command needs 146 # to be sent. It is 7.8 us for a 64ms refresh requirement 147 tREFI = Param.Latency("Refresh command interval") 148 149 # write-to-read turn around penalty, assumed same as read-to-write 150 tWTR = Param.Latency("Write to read switching time") 151 152 # time window in which a maximum number of activates are allowed 153 # to take place, set to 0 to disable 154 tXAW = Param.Latency("X activation window") 155 activation_limit = Param.Unsigned("Max number of activates in window") 156 157 # Currently rolled into other params 158 ###################################################################### 159 160 # the minimum amount of time between a row being activated, and 161 # precharged (de-activated) 162 # tRAS - assumed to be 3 * tRP 163 164 # tRC - assumed to be 4 * tRP 165 166 # burst length for an access derived from peerBlockSize 167 168# High-level model of a single DDR3 x64 interface (one command and 169# address bus), with default timings based on a DDR3-1600 4 Gbit part, 170# which would amount to 4 Gbyte of memory in 8x8 or 8 GByte in 16x4 171# configuration. 172class SimpleDDR3(SimpleDRAM): 173 # Assuming 64 byte cache lines, use a 2kbyte page size, this 174 # depends on the memory density 175 lines_per_rowbuffer = 32 176 177 # Use two ranks 178 ranks_per_channel = 2 179 180 # DDR3 has 8 banks in all configurations 181 banks_per_rank = 8 182 183 # DDR3-1600 11-11-11 184 tRCD = '13.75ns' 185 tCL = '13.75ns' 186 tRP = '13.75ns' 187 188 # Assuming 64 byte cache lines, across an x64 (8x8 or 16x4) 189 # interface, translates to BL8, 4 clocks @ 800 MHz 190 tBURST = '5ns' 191 192 # DDR3, 4 Gb has a tRFC of 240 CK and tCK = 1.25 ns 193 tRFC = '300ns' 194 195 # DDR3, <=85C, half for >85C 196 tREFI = '7.8us' 197 198 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 199 tWTR = '7.5ns' 200 201 # With a 2kbyte page size, DDR3-1600 lands around 40 ns 202 tXAW = '40ns' 203 activation_limit = 4 204 205 206# High-level model of a single LPDDR2-S4 x32 interface (one 207# command/address bus), with default timings based on a LPDDR2-1066 208# 4 Gbit part 209class SimpleLPDDR2_S4(SimpleDRAM): 210 # Assuming 64 byte cache lines, use a 1kbyte page size, this 211 # depends on the memory density 212 lines_per_rowbuffer = 16 213 214 # Use a single rank 215 ranks_per_channel = 1 216 217 # LPDDR2-S4 has 8 banks in all configurations 218 banks_per_rank = 8 219 220 # Fixed at 15 ns 221 tRCD = '15ns' 222 223 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 224 tCL = '15ns' 225 226 # Pre-charge one bank 15 ns and all banks 18 ns 227 tRP = '18ns' 228 229 # Assuming 64 byte cache lines, across a x32 DDR interface 230 # translates to two BL8, 8 clocks @ 533 MHz. Note that this is a 231 # simplification 232 tBURST = '15ns' 233 234 # LPDDR2-S4, 4 Gbit 235 tRFC = '130ns' 236 tREFI = '3.9us' 237 238 # Irrespective of speed grade, tWTR is 7.5 ns 239 tWTR = '7.5ns' 240 241 # Irrespective of density, tFAW is 50 ns 242 tXAW = '50ns' 243 activation_limit = 4 244 245# High-level model of a single WideIO x128 interface (one command and 246# address bus), with default timings based on an estimated WIO-200 8 247# Gbit part. 248class SimpleWideIO(SimpleDRAM): 249 # Assuming 64 byte cache lines, use a 4kbyte page size, this 250 # depends on the memory density 251 lines_per_rowbuffer = 64 252 253 # Use one rank for a one-high die stack 254 ranks_per_channel = 1 255 256 # WideIO has 4 banks in all configurations 257 banks_per_rank = 4 258 259 # WIO-200 260 tRCD = '18ns' 261 tCL = '18ns' 262 tRP = '18ns' 263 264 # Assuming 64 byte cache lines, across an x128 SDR interface, 265 # translates to BL4, 4 clocks @ 200 MHz 266 tBURST = '20ns' 267 268 # WIO 8 Gb 269 tRFC = '210ns' 270 271 # WIO 8 Gb, <=85C, half for >85C 272 tREFI = '3.9us' 273 274 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 275 tWTR = '15ns' 276 277 # Two instead of four activation window 278 tXAW = '50ns' 279 activation_limit = 2 280