DRAMCtrl.py revision 9569
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Hansson 37# Ani Udipi 38 39from m5.params import * 40from AbstractMemory import * 41 42# Enum for memory scheduling algorithms, currently First-Come 43# First-Served and a First-Row Hit then First-Come First-Served 44class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 45 46# Enum for the address mapping, currently corresponding to either 47# optimising for sequential accesses hitting in the open row, or 48# striping across banks. 49class AddrMap(Enum): vals = ['openmap', 'closemap'] 50 51# Enum for the page policy, either open or close. 52class PageManage(Enum): vals = ['open', 'close'] 53 54# SimpleDRAM is a single-channel single-ported DRAM controller model 55# that aims to model the most important system-level performance 56# effects of a DRAM without getting into too much detail of the DRAM 57# itself. 58class SimpleDRAM(AbstractMemory): 59 type = 'SimpleDRAM' 60 cxx_header = "mem/simple_dram.hh" 61 62 @classmethod 63 def makeMultiChannel(cls, nbr_mem_ctrls, mem_start_addr, mem_size, 64 intlv_high_bit = 11): 65 """ 66 Make a multi-channel configuration of this class. 67 68 Create multiple instances of the specific class and set their 69 parameters such that the address range is interleaved between 70 them. 71 72 Returns a list of controllers. 73 """ 74 import math 75 from m5.util import fatal 76 intlv_bits = int(math.log(nbr_mem_ctrls, 2)) 77 if 2 ** intlv_bits != nbr_mem_ctrls: 78 fatal("Number of memory channels must be a power of 2") 79 mem_ctrls = [] 80 for i in xrange(nbr_mem_ctrls): 81 # The default interleaving granularity is tuned to match a 82 # row buffer size of 32 cache lines of 64 bytes (starting 83 # at bit 11 for 2048 bytes). There is unfortunately no 84 # good way of checking this at instantiation time. 85 mem_ctrls.append(cls(range = AddrRange(mem_start_addr, 86 size = mem_size, 87 intlvHighBit = \ 88 intlv_high_bit, 89 intlvBits = intlv_bits, 90 intlvMatch = i), 91 channels = nbr_mem_ctrls)) 92 return mem_ctrls 93 94 # single-ported on the system interface side, instantiate with a 95 # bus in front of the controller for multiple ports 96 port = SlavePort("Slave port") 97 98 # the basic configuration of the controller architecture 99 write_buffer_size = Param.Unsigned(32, "Number of read queue entries") 100 read_buffer_size = Param.Unsigned(32, "Number of write queue entries") 101 102 # threshold in percent for when to trigger writes and start 103 # emptying the write buffer as it starts to get full 104 write_thresh_perc = Param.Percent(70, "Threshold to trigger writes") 105 106 # scheduler, address map and page policy 107 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 108 addr_mapping = Param.AddrMap('openmap', "Address mapping policy") 109 page_policy = Param.PageManage('open', "Page closure management policy") 110 111 # the physical organisation of the DRAM 112 lines_per_rowbuffer = Param.Unsigned("Row buffer size in cache lines") 113 ranks_per_channel = Param.Unsigned("Number of ranks per channel") 114 banks_per_rank = Param.Unsigned("Number of banks per rank") 115 # only used for the address mapping as the controller by 116 # construction is a single channel and multiple controllers have 117 # to be instantiated for a multi-channel configuration 118 channels = Param.Unsigned(1, "Number of channels") 119 120 # timing behaviour and constraints - all in nanoseconds 121 122 # the amount of time in nanoseconds from issuing an activate command 123 # to the data being available in the row buffer for a read/write 124 tRCD = Param.Latency("RAS to CAS delay") 125 126 # the time from issuing a read/write command to seeing the actual data 127 tCL = Param.Latency("CAS latency") 128 129 # minimum time between a precharge and subsequent activate 130 tRP = Param.Latency("Row precharge time") 131 132 # time to complete a burst transfer, typically the burst length 133 # divided by two due to the DDR bus, but by making it a parameter 134 # it is easier to also evaluate SDR memories like WideIO. 135 # This parameter has to account for bus width and burst length. 136 # Adjustment also necessary if cache line size is greater than 137 # data size read/written by one full burst. 138 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 139 140 # time taken to complete one refresh cycle (N rows in all banks) 141 tRFC = Param.Latency("Refresh cycle time") 142 143 # refresh command interval, how often a "ref" command needs 144 # to be sent. It is 7.8 us for a 64ms refresh requirement 145 tREFI = Param.Latency("Refresh command interval") 146 147 # write-to-read turn around penalty, assumed same as read-to-write 148 tWTR = Param.Latency("Write to read switching time") 149 150 # time window in which a maximum number of activates are allowed 151 # to take place, set to 0 to disable 152 tXAW = Param.Latency("X activation window") 153 activation_limit = Param.Unsigned("Max number of activates in window") 154 155 # Currently rolled into other params 156 ###################################################################### 157 158 # the minimum amount of time between a row being activated, and 159 # precharged (de-activated) 160 # tRAS - assumed to be 3 * tRP 161 162 # tRC - assumed to be 4 * tRP 163 164 # burst length for an access derived from peerBlockSize 165 166# High-level model of a single DDR3 x64 interface (one command and 167# address bus), with default timings based on a DDR3-1600 4 Gbit part, 168# which would amount to 4 Gbyte of memory in 8x8 or 8 GByte in 16x4 169# configuration. 170class SimpleDDR3(SimpleDRAM): 171 # Assuming 64 byte cache lines, use a 2kbyte page size, this 172 # depends on the memory density 173 lines_per_rowbuffer = 32 174 175 # Use two ranks 176 ranks_per_channel = 2 177 178 # DDR3 has 8 banks in all configurations 179 banks_per_rank = 8 180 181 # DDR3-1600 11-11-11 182 tRCD = '13.75ns' 183 tCL = '13.75ns' 184 tRP = '13.75ns' 185 186 # Assuming 64 byte cache lines, across an x64 (8x8 or 16x4) 187 # interface, translates to BL8, 4 clocks @ 800 MHz 188 tBURST = '5ns' 189 190 # DDR3, 4 Gb has a tRFC of 240 CK and tCK = 1.25 ns 191 tRFC = '300ns' 192 193 # DDR3, <=85C, half for >85C 194 tREFI = '7.8us' 195 196 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 197 tWTR = '7.5ns' 198 199 # With a 2kbyte page size, DDR3-1600 lands around 40 ns 200 tXAW = '40ns' 201 activation_limit = 4 202 203 204# High-level model of a single LPDDR2-S4 x64 interface (one 205# command/address bus), with default timings based on a LPDDR2-1066 206# 4Gbit part, which whould amount to 1 GByte of memory in 2x32 or 207# 2GByte in 4x16 configuration. 208class SimpleLPDDR2_S4(SimpleDRAM): 209 # Assuming 64 byte cache lines, use a 2kbyte page size, this 210 # depends on the memory density 211 lines_per_rowbuffer = 32 212 213 # Use two ranks 214 ranks_per_channel = 2 215 216 # LPDDR2-S4 has 8 banks in all configurations 217 banks_per_rank = 8 218 219 # Fixed at 15 ns 220 tRCD = '15ns' 221 222 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 223 tCL = '15ns' 224 225 # Pre-charge one bank 15 ns and all banks 18 ns 226 tRP = '18ns' 227 228 # Assuming 64 byte cache lines, across a x64 interface (2x32 or 229 # 4x16), translates to BL8, 4 clocks @ 533 MHz 230 tBURST = '7.5ns' 231 232 # LPDDR2-S4, 4 Gb 233 tRFC = '130ns' 234 tREFI = '3.9us' 235 236 # Irrespective of speed grade, tWTR is 7.5 ns 237 tWTR = '7.5ns' 238 239 # Irrespective of size, tFAW is 50 ns 240 tXAW = '50ns' 241 activation_limit = 4 242